diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -64,6 +64,7 @@
                          MachineBasicBlock::iterator MBBI, unsigned Opcode);
   bool expandVSPILL(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
   bool expandVRELOAD(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
+  bool expandpair(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
 };
 
 char RISCVExpandPseudo::ID = 0;
@@ -89,6 +90,13 @@
   return Modified;
 }
 
+bool RISCVExpandPseudo::expandpair(MachineBasicBlock &MBB,
+                                   MachineBasicBlock::iterator MBBI) {
+  MBBI->eraseFromParent();
+
+  return true;
+}
+
 bool RISCVExpandPseudo::expandMI(MachineBasicBlock &MBB,
                                  MachineBasicBlock::iterator MBBI,
                                  MachineBasicBlock::iterator &NextMBBI) {
@@ -96,6 +104,8 @@
   // expanded instructions for each pseudo is correct in the Size field of the
   // tablegen definition for the pseudo.
   switch (MBBI->getOpcode()) {
+  case RISCV::BuildPairF64Pseudo_INX:
+    return expandpair(MBB, MBBI);
   case RISCV::PseudoLLA:
     return expandLoadLocalAddress(MBB, MBBI, NextMBBI);
   case RISCV::PseudoLA:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -9334,10 +9334,8 @@
   case RISCV::Select_FPR64_Using_CC_GPR:
     return emitSelectPseudo(MI, BB, Subtarget);
   case RISCV::BuildPairF64Pseudo:
-  case RISCV::BuildPairF64Pseudo_INX:
     return emitBuildPairF64Pseudo(MI, BB, Subtarget);
   case RISCV::SplitF64Pseudo:
-  case RISCV::SplitF64Pseudo_INX:
     return emitSplitF64Pseudo(MI, BB, Subtarget);
   case RISCV::PseudoQuietFLE_H:
     return emitQuietFCMP(MI, BB, RISCV::FLE_H, RISCV::FEQ_H, Subtarget);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -364,13 +364,11 @@
 let Predicates = [HasStdExtZdinx] in {
 
 // Moves two GPRs to an FPR.
-let usesCustomInserter = 1 in
 def BuildPairF64Pseudo_INX
     : Pseudo<(outs GPRPF64:$dst), (ins GPR:$src1, GPR:$src2),
              [(set GPRPF64:$dst, (RISCVBuildPairF64 GPR:$src1, GPR:$src2))]>;
 
 // Moves an FPR to two GPRs.
-let usesCustomInserter = 1 in
 def SplitF64Pseudo_INX
     : Pseudo<(outs GPR:$dst1, GPR:$dst2), (ins GPRPF64:$src),
              [(set GPR:$dst1, GPR:$dst2, (RISCVSplitF64 GPRPF64:$src))]>;
diff --git a/llvm/test/CodeGen/RISCV/double-fcmp.ll b/llvm/test/CodeGen/RISCV/double-fcmp.ll
--- a/llvm/test/CodeGen/RISCV/double-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/double-fcmp.ll
@@ -60,15 +60,7 @@
 ;
 ; RV32ZDINX-LABEL: fcmp_oeq:
 ; RV32ZDINX:       # %bb.0:
-; RV32ZDINX-NEXT:    addi sp, sp, -16
-; RV32ZDINX-NEXT:    sw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a3, 12(sp)
-; RV32ZDINX-NEXT:    lw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a1, 12(sp)
-; RV32ZDINX-NEXT:    lw a0, 8(sp)
 ; RV32ZDINX-NEXT:    feq.d a0, a0, a2
-; RV32ZDINX-NEXT:    addi sp, sp, 16
 ; RV32ZDINX-NEXT:    ret
 ;
 ; RV64ZDINX-LABEL: fcmp_oeq:
@@ -113,15 +105,7 @@
 ;
 ; RV32ZDINX-LABEL: fcmp_ogt:
 ; RV32ZDINX:       # %bb.0:
-; RV32ZDINX-NEXT:    addi sp, sp, -16
-; RV32ZDINX-NEXT:    sw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a1, 12(sp)
-; RV32ZDINX-NEXT:    lw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a3, 12(sp)
-; RV32ZDINX-NEXT:    lw a2, 8(sp)
 ; RV32ZDINX-NEXT:    flt.d a0, a2, a0
-; RV32ZDINX-NEXT:    addi sp, sp, 16
 ; RV32ZDINX-NEXT:    ret
 ;
 ; RV64ZDINX-LABEL: fcmp_ogt:
@@ -166,15 +150,7 @@
 ;
 ; RV32ZDINX-LABEL: fcmp_oge:
 ; RV32ZDINX:       # %bb.0:
-; RV32ZDINX-NEXT:    addi sp, sp, -16
-; RV32ZDINX-NEXT:    sw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a1, 12(sp)
-; RV32ZDINX-NEXT:    lw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a3, 12(sp)
-; RV32ZDINX-NEXT:    lw a2, 8(sp)
 ; RV32ZDINX-NEXT:    fle.d a0, a2, a0
-; RV32ZDINX-NEXT:    addi sp, sp, 16
 ; RV32ZDINX-NEXT:    ret
 ;
 ; RV64ZDINX-LABEL: fcmp_oge:
@@ -221,15 +197,7 @@
 ;
 ; RV32ZDINX-LABEL: fcmp_olt:
 ; RV32ZDINX:       # %bb.0:
-; RV32ZDINX-NEXT:    addi sp, sp, -16
-; RV32ZDINX-NEXT:    sw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a3, 12(sp)
-; RV32ZDINX-NEXT:    lw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a1, 12(sp)
-; RV32ZDINX-NEXT:    lw a0, 8(sp)
 ; RV32ZDINX-NEXT:    flt.d a0, a0, a2
-; RV32ZDINX-NEXT:    addi sp, sp, 16
 ; RV32ZDINX-NEXT:    ret
 ;
 ; RV64ZDINX-LABEL: fcmp_olt:
@@ -274,15 +242,7 @@
 ;
 ; RV32ZDINX-LABEL: fcmp_ole:
 ; RV32ZDINX:       # %bb.0:
-; RV32ZDINX-NEXT:    addi sp, sp, -16
-; RV32ZDINX-NEXT:    sw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a3, 12(sp)
-; RV32ZDINX-NEXT:    lw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a1, 12(sp)
-; RV32ZDINX-NEXT:    lw a0, 8(sp)
 ; RV32ZDINX-NEXT:    fle.d a0, a0, a2
-; RV32ZDINX-NEXT:    addi sp, sp, 16
 ; RV32ZDINX-NEXT:    ret
 ;
 ; RV64ZDINX-LABEL: fcmp_ole:
@@ -331,17 +291,9 @@
 ;
 ; RV32ZDINX-LABEL: fcmp_one:
 ; RV32ZDINX:       # %bb.0:
-; RV32ZDINX-NEXT:    addi sp, sp, -16
-; RV32ZDINX-NEXT:    sw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a3, 12(sp)
-; RV32ZDINX-NEXT:    lw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a1, 12(sp)
-; RV32ZDINX-NEXT:    lw a0, 8(sp)
 ; RV32ZDINX-NEXT:    flt.d a4, a0, a2
 ; RV32ZDINX-NEXT:    flt.d a0, a2, a0
 ; RV32ZDINX-NEXT:    or a0, a0, a4
-; RV32ZDINX-NEXT:    addi sp, sp, 16
 ; RV32ZDINX-NEXT:    ret
 ;
 ; RV64ZDINX-LABEL: fcmp_one:
@@ -426,17 +378,9 @@
 ;
 ; RV32ZDINX-LABEL: fcmp_ord:
 ; RV32ZDINX:       # %bb.0:
-; RV32ZDINX-NEXT:    addi sp, sp, -16
-; RV32ZDINX-NEXT:    sw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a1, 12(sp)
-; RV32ZDINX-NEXT:    lw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a3, 12(sp)
-; RV32ZDINX-NEXT:    lw a2, 8(sp)
 ; RV32ZDINX-NEXT:    feq.d a2, a2, a2
 ; RV32ZDINX-NEXT:    feq.d a0, a0, a0
 ; RV32ZDINX-NEXT:    and a0, a0, a2
-; RV32ZDINX-NEXT:    addi sp, sp, 16
 ; RV32ZDINX-NEXT:    ret
 ;
 ; RV64ZDINX-LABEL: fcmp_ord:
@@ -489,18 +433,10 @@
 ;
 ; RV32ZDINX-LABEL: fcmp_ueq:
 ; RV32ZDINX:       # %bb.0:
-; RV32ZDINX-NEXT:    addi sp, sp, -16
-; RV32ZDINX-NEXT:    sw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a3, 12(sp)
-; RV32ZDINX-NEXT:    lw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a1, 12(sp)
-; RV32ZDINX-NEXT:    lw a0, 8(sp)
 ; RV32ZDINX-NEXT:    flt.d a4, a0, a2
 ; RV32ZDINX-NEXT:    flt.d a0, a2, a0
 ; RV32ZDINX-NEXT:    or a0, a0, a4
 ; RV32ZDINX-NEXT:    xori a0, a0, 1
-; RV32ZDINX-NEXT:    addi sp, sp, 16
 ; RV32ZDINX-NEXT:    ret
 ;
 ; RV64ZDINX-LABEL: fcmp_ueq:
@@ -584,16 +520,8 @@
 ;
 ; RV32ZDINX-LABEL: fcmp_ugt:
 ; RV32ZDINX:       # %bb.0:
-; RV32ZDINX-NEXT:    addi sp, sp, -16
-; RV32ZDINX-NEXT:    sw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a3, 12(sp)
-; RV32ZDINX-NEXT:    lw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a1, 12(sp)
-; RV32ZDINX-NEXT:    lw a0, 8(sp)
 ; RV32ZDINX-NEXT:    fle.d a0, a0, a2
 ; RV32ZDINX-NEXT:    xori a0, a0, 1
-; RV32ZDINX-NEXT:    addi sp, sp, 16
 ; RV32ZDINX-NEXT:    ret
 ;
 ; RV64ZDINX-LABEL: fcmp_ugt:
@@ -641,16 +569,8 @@
 ;
 ; RV32ZDINX-LABEL: fcmp_uge:
 ; RV32ZDINX:       # %bb.0:
-; RV32ZDINX-NEXT:    addi sp, sp, -16
-; RV32ZDINX-NEXT:    sw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a3, 12(sp)
-; RV32ZDINX-NEXT:    lw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a1, 12(sp)
-; RV32ZDINX-NEXT:    lw a0, 8(sp)
 ; RV32ZDINX-NEXT:    flt.d a0, a0, a2
 ; RV32ZDINX-NEXT:    xori a0, a0, 1
-; RV32ZDINX-NEXT:    addi sp, sp, 16
 ; RV32ZDINX-NEXT:    ret
 ;
 ; RV64ZDINX-LABEL: fcmp_uge:
@@ -700,16 +620,8 @@
 ;
 ; RV32ZDINX-LABEL: fcmp_ult:
 ; RV32ZDINX:       # %bb.0:
-; RV32ZDINX-NEXT:    addi sp, sp, -16
-; RV32ZDINX-NEXT:    sw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a1, 12(sp)
-; RV32ZDINX-NEXT:    lw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a3, 12(sp)
-; RV32ZDINX-NEXT:    lw a2, 8(sp)
 ; RV32ZDINX-NEXT:    fle.d a0, a2, a0
 ; RV32ZDINX-NEXT:    xori a0, a0, 1
-; RV32ZDINX-NEXT:    addi sp, sp, 16
 ; RV32ZDINX-NEXT:    ret
 ;
 ; RV64ZDINX-LABEL: fcmp_ult:
@@ -757,16 +669,8 @@
 ;
 ; RV32ZDINX-LABEL: fcmp_ule:
 ; RV32ZDINX:       # %bb.0:
-; RV32ZDINX-NEXT:    addi sp, sp, -16
-; RV32ZDINX-NEXT:    sw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a1, 12(sp)
-; RV32ZDINX-NEXT:    lw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a3, 12(sp)
-; RV32ZDINX-NEXT:    lw a2, 8(sp)
 ; RV32ZDINX-NEXT:    flt.d a0, a2, a0
 ; RV32ZDINX-NEXT:    xori a0, a0, 1
-; RV32ZDINX-NEXT:    addi sp, sp, 16
 ; RV32ZDINX-NEXT:    ret
 ;
 ; RV64ZDINX-LABEL: fcmp_ule:
@@ -814,16 +718,8 @@
 ;
 ; RV32ZDINX-LABEL: fcmp_une:
 ; RV32ZDINX:       # %bb.0:
-; RV32ZDINX-NEXT:    addi sp, sp, -16
-; RV32ZDINX-NEXT:    sw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a3, 12(sp)
-; RV32ZDINX-NEXT:    lw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a1, 12(sp)
-; RV32ZDINX-NEXT:    lw a0, 8(sp)
 ; RV32ZDINX-NEXT:    feq.d a0, a0, a2
 ; RV32ZDINX-NEXT:    xori a0, a0, 1
-; RV32ZDINX-NEXT:    addi sp, sp, 16
 ; RV32ZDINX-NEXT:    ret
 ;
 ; RV64ZDINX-LABEL: fcmp_une:
@@ -875,18 +771,10 @@
 ;
 ; RV32ZDINX-LABEL: fcmp_uno:
 ; RV32ZDINX:       # %bb.0:
-; RV32ZDINX-NEXT:    addi sp, sp, -16
-; RV32ZDINX-NEXT:    sw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a1, 12(sp)
-; RV32ZDINX-NEXT:    lw a0, 8(sp)
-; RV32ZDINX-NEXT:    sw a2, 8(sp)
-; RV32ZDINX-NEXT:    sw a3, 12(sp)
-; RV32ZDINX-NEXT:    lw a2, 8(sp)
 ; RV32ZDINX-NEXT:    feq.d a2, a2, a2
 ; RV32ZDINX-NEXT:    feq.d a0, a0, a0
 ; RV32ZDINX-NEXT:    and a0, a0, a2
 ; RV32ZDINX-NEXT:    xori a0, a0, 1
-; RV32ZDINX-NEXT:    addi sp, sp, 16
 ; RV32ZDINX-NEXT:    ret
 ;
 ; RV64ZDINX-LABEL: fcmp_uno: