diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td --- a/llvm/include/llvm/Target/Target.td +++ b/llvm/include/llvm/Target/Target.td @@ -1620,7 +1620,7 @@ // SubtargetFeature - A characteristic of the chip set. // class SubtargetFeature i = []> { + list i = [], bit m = 1> { // Name - Feature name. Used by command line (-mattr=) to determine the // appropriate target chip. // @@ -1643,6 +1643,10 @@ // features isn't set, then this one shouldn't be set either. // list Implies = i; + + // TrivalInterface - Auto-generate a trival interface for this feature. + // + bit TrivalInterface = m; } /// Specifies a Subtarget feature that this instruction is deprecated on. diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -19,11 +19,11 @@ // X86 Subtarget state // -def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true", +def Mode64Bit : SubtargetFeature<"64bit-mode", "Is64Bit", "true", "64-bit mode (x86_64)">; -def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true", +def Mode32Bit : SubtargetFeature<"32bit-mode", "Is32Bit", "true", "32-bit mode (80386)">; -def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true", +def Mode16Bit : SubtargetFeature<"16bit-mode", "Is16Bit", "true", "16-bit mode (i8086)">; //===----------------------------------------------------------------------===// @@ -37,7 +37,7 @@ "Enable NOPL instruction">; def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true", - "Enable conditional move instructions">; + "Enable conditional move instructions", [], 0>; def FeatureCMPXCHG8B : SubtargetFeature<"cx8", "HasCmpxchg8b", "true", "Support CMPXCHG8B instructions">; @@ -102,7 +102,7 @@ "Support 64-bit instructions">; def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true", "64-bit with cmpxchg16b", - [FeatureCMPXCHG8B]>; + [FeatureCMPXCHG8B], 0>; def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true", "Support SSE 4a instructions", [FeatureSSE3]>; @@ -119,7 +119,7 @@ def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true", "Support 16-bit floating point conversion instructions", [FeatureAVX]>; -def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F", +def FeatureAVX512 : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512", "Enable AVX-512 instructions", [FeatureAVX2, FeatureFMA, FeatureF16C]>; def FeatureERI : SubtargetFeature<"avx512er", "HasERI", "true", @@ -396,11 +396,11 @@ // FIXME: This should not apply to CPUs that do not have SSE. def TuningSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16", - "IsUAMem16Slow", "true", + "IsUnalignedMem16Slow", "true", "Slow unaligned 16-byte memory access">; def TuningSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32", - "IsUAMem32Slow", "true", + "IsUnalignedMem32Slow", "true", "Slow unaligned 32-byte memory access">; def TuningLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true", @@ -425,7 +425,7 @@ "SlowTwoMemOps", "true", "Two memory operand instructions are slow">; -def TuningLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true", +def TuningLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LeaUsesAG", "true", "LEA instruction needs inputs at AG stage">; def TuningSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true", @@ -584,7 +584,7 @@ // Enable use of alias analysis during code generation. def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true", - "Use alias analysis during codegen">; + "Use alias analysis during codegen", [], 0>; //===----------------------------------------------------------------------===// // X86 CPU Families @@ -592,7 +592,7 @@ //===----------------------------------------------------------------------===// // Bonnell -def ProcIntelAtom : SubtargetFeature<"", "X86ProcFamily", "IntelAtom", "">; +def ProcIntelAtom : SubtargetFeature<"", "IsAtom", "true", "Is Intel Atom processor">; //===----------------------------------------------------------------------===// // Register File Description diff --git a/llvm/lib/Target/X86/X86FixupLEAs.cpp b/llvm/lib/Target/X86/X86FixupLEAs.cpp --- a/llvm/lib/Target/X86/X86FixupLEAs.cpp +++ b/llvm/lib/Target/X86/X86FixupLEAs.cpp @@ -229,7 +229,7 @@ const X86Subtarget &ST = MF.getSubtarget(); bool IsSlowLEA = ST.slowLEA(); bool IsSlow3OpsLEA = ST.slow3OpsLEA(); - bool LEAUsesAG = ST.LEAusesAG(); + bool LEAUsesAG = ST.leaUsesAG(); bool OptIncDec = !ST.slowIncDec() || MF.getFunction().hasOptSize(); bool UseLEAForSP = ST.useLeaForSP(); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -497,7 +497,7 @@ setOperationAction(ISD::SRL_PARTS, VT, Custom); } - if (Subtarget.hasSSEPrefetch() || Subtarget.has3DNow()) + if (Subtarget.hasSSEPrefetch() || Subtarget.hasThreeDNow()) setOperationAction(ISD::PREFETCH , MVT::Other, Legal); setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -879,8 +879,8 @@ def NoCMov : Predicate<"!Subtarget->hasCMov()">; def HasMMX : Predicate<"Subtarget->hasMMX()">; -def Has3DNow : Predicate<"Subtarget->has3DNow()">; -def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; +def Has3DNow : Predicate<"Subtarget->hasThreeDNow()">; +def Has3DNowA : Predicate<"Subtarget->hasThreeNowA()">; def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h --- a/llvm/lib/Target/X86/X86Subtarget.h +++ b/llvm/lib/Target/X86/X86Subtarget.h @@ -50,445 +50,21 @@ } // end namespace PICStyles class X86Subtarget final : public X86GenSubtargetInfo { - // NOTE: Do not add anything new to this list. Coarse, CPU name based flags - // are not a good idea. We should be migrating away from these. - enum X86ProcFamilyEnum { - Others, - IntelAtom - }; - enum X86SSEEnum { - NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F + NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512 }; enum X863DNowEnum { NoThreeDNow, MMX, ThreeDNow, ThreeDNowA }; - /// X86 processor family: Intel Atom, and others - X86ProcFamilyEnum X86ProcFamily = Others; - /// Which PIC style to use PICStyles::Style PICStyle; const TargetMachine &TM; - /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported. - X86SSEEnum X86SSELevel = NoSSE; - - /// MMX, 3DNow, 3DNow Athlon, or none supported. - X863DNowEnum X863DNowLevel = NoThreeDNow; - - /// True if the processor supports X87 instructions. - bool HasX87 = false; - - /// True if the processor supports CMPXCHG8B. - bool HasCmpxchg8b = false; - - /// True if this processor has NOPL instruction - /// (generally pentium pro+). - bool HasNOPL = false; - - /// True if this processor has conditional move instructions - /// (generally pentium pro+). - bool HasCMov = false; - - /// True if the processor supports X86-64 instructions. - bool HasX86_64 = false; - - /// True if the processor supports POPCNT. - bool HasPOPCNT = false; - - /// True if the processor supports SSE4A instructions. - bool HasSSE4A = false; - - /// Target has AES instructions - bool HasAES = false; - bool HasVAES = false; - - /// Target has FXSAVE/FXRESTOR instructions - bool HasFXSR = false; - - /// Target has XSAVE instructions - bool HasXSAVE = false; - - /// Target has XSAVEOPT instructions - bool HasXSAVEOPT = false; - - /// Target has XSAVEC instructions - bool HasXSAVEC = false; - - /// Target has XSAVES instructions - bool HasXSAVES = false; - - /// Target has carry-less multiplication - bool HasPCLMUL = false; - bool HasVPCLMULQDQ = false; - - /// Target has Galois Field Arithmetic instructions - bool HasGFNI = false; - - /// Target has 3-operand fused multiply-add - bool HasFMA = false; - - /// Target has 4-operand fused multiply-add - bool HasFMA4 = false; - - /// Target has XOP instructions - bool HasXOP = false; - - /// Target has TBM instructions. - bool HasTBM = false; - - /// Target has LWP instructions - bool HasLWP = false; - - /// True if the processor has the MOVBE instruction. - bool HasMOVBE = false; - - /// True if the processor has the RDRAND instruction. - bool HasRDRAND = false; - - /// Processor has 16-bit floating point conversion instructions. - bool HasF16C = false; - - /// Processor has FS/GS base insturctions. - bool HasFSGSBase = false; - - /// Processor has LZCNT instruction. - bool HasLZCNT = false; - - /// Processor has BMI1 instructions. - bool HasBMI = false; - - /// Processor has BMI2 instructions. - bool HasBMI2 = false; - - /// Processor has VBMI instructions. - bool HasVBMI = false; - - /// Processor has VBMI2 instructions. - bool HasVBMI2 = false; - - /// Processor has Integer Fused Multiply Add - bool HasIFMA = false; - - /// Processor has RTM instructions. - bool HasRTM = false; - - /// Processor has ADX instructions. - bool HasADX = false; - - /// Processor has SHA instructions. - bool HasSHA = false; - - /// Processor has PRFCHW instructions. - bool HasPRFCHW = false; - - /// Processor has RDSEED instructions. - bool HasRDSEED = false; - - /// Processor has LAHF/SAHF instructions in 64-bit mode. - bool HasLAHFSAHF64 = false; - - /// Processor has MONITORX/MWAITX instructions. - bool HasMWAITX = false; - - /// Processor has Cache Line Zero instruction - bool HasCLZERO = false; - - /// Processor has Cache Line Demote instruction - bool HasCLDEMOTE = false; - - /// Processor has MOVDIRI instruction (direct store integer). - bool HasMOVDIRI = false; - - /// Processor has MOVDIR64B instruction (direct store 64 bytes). - bool HasMOVDIR64B = false; - - /// Processor has ptwrite instruction. - bool HasPTWRITE = false; - - /// Processor has Prefetch with intent to Write instruction - bool HasPREFETCHWT1 = false; - - /// True if SHLD instructions are slow. - bool IsSHLDSlow = false; - - /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and - // PMULUDQ. - bool IsPMULLDSlow = false; - - /// True if the PMADDWD instruction is slow compared to PMULLD. - bool IsPMADDWDSlow = false; - - /// True if unaligned memory accesses of 16-bytes are slow. - bool IsUAMem16Slow = false; - - /// True if unaligned memory accesses of 32-bytes are slow. - bool IsUAMem32Slow = false; - - /// True if SSE operations can have unaligned memory operands. - /// This may require setting a configuration bit in the processor. - bool HasSSEUnalignedMem = false; - - /// True if this processor has the CMPXCHG16B instruction; - /// this is true for most x86-64 chips, but not the first AMD chips. - bool HasCmpxchg16b = false; - - /// True if the LEA instruction should be used for adjusting - /// the stack pointer. This is an optimization for Intel Atom processors. - bool UseLeaForSP = false; - - /// True if POPCNT instruction has a false dependency on the destination register. - bool HasPOPCNTFalseDeps = false; - - /// True if LZCNT/TZCNT instructions have a false dependency on the destination register. - bool HasLZCNTFalseDeps = false; - - /// True if an SBB instruction with same source register is recognized as - /// having no dependency on that register. - bool HasSBBDepBreaking = false; - - /// True if its preferable to combine to a single cross-lane shuffle - /// using a variable mask over multiple fixed shuffles. - bool HasFastVariableCrossLaneShuffle = false; - - /// True if its preferable to combine to a single per-lane shuffle - /// using a variable mask over multiple fixed shuffles. - bool HasFastVariablePerLaneShuffle = false; - - /// True if vzeroupper instructions should be inserted after code that uses - /// ymm or zmm registers. - bool InsertVZEROUPPER = false; - - /// True if there is no performance penalty for writing NOPs with up to - /// 7 bytes. - bool HasFast7ByteNOP = false; - - /// True if there is no performance penalty for writing NOPs with up to - /// 11 bytes. - bool HasFast11ByteNOP = false; - - /// True if there is no performance penalty for writing NOPs with up to - /// 15 bytes. - bool HasFast15ByteNOP = false; - - /// True if gather is reasonably fast. This is true for Skylake client and - /// all AVX-512 CPUs. - bool HasFastGather = false; - - /// True if hardware SQRTSS instruction is at least as fast (latency) as - /// RSQRTSS followed by a Newton-Raphson iteration. - bool HasFastScalarFSQRT = false; - - /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast - /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration. - bool HasFastVectorFSQRT = false; - - /// True if 8-bit divisions are significantly faster than - /// 32-bit divisions and should be used when possible. - bool HasSlowDivide32 = false; - - /// True if 32-bit divides are significantly faster than - /// 64-bit divisions and should be used when possible. - bool HasSlowDivide64 = false; - - /// True if LZCNT instruction is fast. - bool HasFastLZCNT = false; - - /// True if SHLD based rotate is fast. - bool HasFastSHLDRotate = false; - - /// True if the processor supports macrofusion. - bool HasMacroFusion = false; - - /// True if the processor supports branch fusion. - bool HasBranchFusion = false; - - /// True if the processor has enhanced REP MOVSB/STOSB. - bool HasERMSB = false; - - /// True if the processor has fast short REP MOV. - bool HasFSRM = false; - - /// True if the short functions should be padded to prevent - /// a stall when returning too early. - bool PadShortFunctions = false; - - /// True if two memory operand instructions should use a temporary register - /// instead. - bool SlowTwoMemOps = false; - - /// True if the LEA instruction inputs have to be ready at address generation - /// (AG) time. - bool LEAUsesAG = false; - - /// True if the LEA instruction with certain arguments is slow - bool SlowLEA = false; - - /// True if the LEA instruction has all three source operands: base, index, - /// and offset or if the LEA instruction uses base and index registers where - /// the base is EBP, RBP,or R13 - bool Slow3OpsLEA = false; - - /// True if INC and DEC instructions are slow when writing to flags - bool SlowIncDec = false; - - /// Processor has AVX-512 PreFetch Instructions - bool HasPFI = false; - - /// Processor has AVX-512 Exponential and Reciprocal Instructions - bool HasERI = false; - - /// Processor has AVX-512 Conflict Detection Instructions - bool HasCDI = false; - - /// Processor has AVX-512 population count Instructions - bool HasVPOPCNTDQ = false; - - /// Processor has AVX-512 Doubleword and Quadword instructions - bool HasDQI = false; - - /// Processor has AVX-512 Byte and Word instructions - bool HasBWI = false; - - /// Processor has AVX-512 Vector Length eXtenstions - bool HasVLX = false; - - /// Processor has AVX-512 16 bit floating-point extenstions - bool HasFP16 = false; - - /// Processor has PKU extenstions - bool HasPKU = false; - - /// Processor has AVX-512 Vector Neural Network Instructions - bool HasVNNI = false; - - /// Processor has AVX Vector Neural Network Instructions - bool HasAVXVNNI = false; - - /// Processor has AVX-512 bfloat16 floating-point extensions - bool HasBF16 = false; - - /// Processor supports ENQCMD instructions - bool HasENQCMD = false; - - /// Processor has AVX-512 Bit Algorithms instructions - bool HasBITALG = false; - - /// Processor has AVX-512 vp2intersect instructions - bool HasVP2INTERSECT = false; - - /// Processor supports CET SHSTK - Control-Flow Enforcement Technology - /// using Shadow Stack - bool HasSHSTK = false; - - /// Processor supports Invalidate Process-Context Identifier - bool HasINVPCID = false; - - /// Processor has Software Guard Extensions - bool HasSGX = false; - - /// Processor supports Flush Cache Line instruction - bool HasCLFLUSHOPT = false; - - /// Processor supports Cache Line Write Back instruction - bool HasCLWB = false; - - /// Processor supports Write Back No Invalidate instruction - bool HasWBNOINVD = false; - - /// Processor support RDPID instruction - bool HasRDPID = false; - - /// Processor supports WaitPKG instructions - bool HasWAITPKG = false; - - /// Processor supports PCONFIG instruction - bool HasPCONFIG = false; - - /// Processor support key locker instructions - bool HasKL = false; - - /// Processor support key locker wide instructions - bool HasWIDEKL = false; - - /// Processor supports HRESET instruction - bool HasHRESET = false; - - /// Processor supports SERIALIZE instruction - bool HasSERIALIZE = false; - - /// Processor supports TSXLDTRK instruction - bool HasTSXLDTRK = false; - - /// Processor has AMX support - bool HasAMXTILE = false; - bool HasAMXBF16 = false; - bool HasAMXINT8 = false; - - /// Processor supports User Level Interrupt instructions - bool HasUINTR = false; - - /// Enable SSE4.2 CRC32 instruction (Used when SSE4.2 is supported but - /// function is GPR only) - bool HasCRC32 = false; - - /// Processor has a single uop BEXTR implementation. - bool HasFastBEXTR = false; - - /// Try harder to combine to horizontal vector ops if they are fast. - bool HasFastHorizontalOps = false; - - /// Prefer a left/right scalar logical shifts pair over a shift+and pair. - bool HasFastScalarShiftMasks = false; - - /// Prefer a left/right vector logical shifts pair over a shift+and pair. - bool HasFastVectorShiftMasks = false; - - /// Prefer a movbe over a single-use load + bswap / single-use bswap + store. - bool HasFastMOVBE = false; - - /// Use a retpoline thunk rather than indirect calls to block speculative - /// execution. - bool UseRetpolineIndirectCalls = false; - - /// Use a retpoline thunk or remove any indirect branch to block speculative - /// execution. - bool UseRetpolineIndirectBranches = false; - - /// Deprecated flag, query `UseRetpolineIndirectCalls` and - /// `UseRetpolineIndirectBranches` instead. - bool DeprecatedUseRetpoline = false; - - /// When using a retpoline thunk, call an externally provided thunk rather - /// than emitting one inside the compiler. - bool UseRetpolineExternalThunk = false; - - /// Prevent generation of indirect call/branch instructions from memory, - /// and force all indirect call/branch instructions from a register to be - /// preceded by an LFENCE. Also decompose RET instructions into a - /// POP+LFENCE+JMP sequence. - bool UseLVIControlFlowIntegrity = false; - - /// Enable Speculative Execution Side Effect Suppression - bool UseSpeculativeExecutionSideEffectSuppression = false; - - /// Insert LFENCE instructions to prevent data speculatively injected into - /// loads from being used maliciously. - bool UseLVILoadHardening = false; - - /// Use an instruction sequence for taking the address of a global that allows - /// a memory tag in the upper address bits. - bool AllowTaggedGlobals = false; - - /// Use software floating point for code generation. - bool UseSoftFloat = false; - - /// Use alias analysis during code generation. - bool UseAA = false; - +#define GET_SUBTARGETINFO_FEATURE_MEMBER +#include "X86GenSubtargetInfo.inc" /// The minimum alignment known to hold of the stack frame on /// entry to the function and which must be maintained by every function. Align stackAlignment = Align(4); @@ -500,21 +76,6 @@ // FIXME: this is a known good value for Yonah. How about others? unsigned MaxInlineSizeThreshold = 128; - /// Indicates target prefers 128 bit instructions. - bool Prefer128Bit = false; - - /// Indicates target prefers 256 bit instructions. - bool Prefer256Bit = false; - - /// Indicates target prefers AVX512 mask registers. - bool PreferMaskRegisters = false; - - /// Use Silvermont specific arithmetic costs. - bool UseSLMArithCosts = false; - - /// Use Goldmont specific floating point div/sqrt costs. - bool UseGLMDivSqrtCosts = false; - /// What processor and OS we're targeting. Triple TargetTriple; @@ -538,15 +99,6 @@ /// Required vector width from function attribute. unsigned RequiredVectorWidth; - /// True if compiling for 64-bit, false for 16-bit or 32-bit. - bool In64BitMode = false; - - /// True if compiling for 32-bit, false for 16-bit or 64-bit. - bool In32BitMode = false; - - /// True if compiling for 16-bit, false for 32-bit or 64-bit. - bool In16BitMode = false; - X86SelectionDAGInfo TSInfo; // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which // X86TargetLowering needs. @@ -612,187 +164,44 @@ void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); public: - /// Is this x86_64? (disregarding specific ABI / programming model) - bool is64Bit() const { - return In64BitMode; - } - - bool is32Bit() const { - return In32BitMode; - } - - bool is16Bit() const { - return In16BitMode; - } - /// Is this x86_64 with the ILP32 programming model (x32 ABI)? bool isTarget64BitILP32() const { - return In64BitMode && (TargetTriple.isX32() || TargetTriple.isOSNaCl()); + return Is64Bit && (TargetTriple.isX32() || TargetTriple.isOSNaCl()); } /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)? bool isTarget64BitLP64() const { - return In64BitMode && (!TargetTriple.isX32() && !TargetTriple.isOSNaCl()); + return Is64Bit && (!TargetTriple.isX32() && !TargetTriple.isOSNaCl()); } PICStyles::Style getPICStyle() const { return PICStyle; } void setPICStyle(PICStyles::Style Style) { PICStyle = Style; } - bool hasX87() const { return HasX87; } - bool hasCmpxchg8b() const { return HasCmpxchg8b; } - bool hasNOPL() const { return HasNOPL; } +#define GET_SUBTARGETINFO_FEATURE_INTERFACE +#include "X86GenSubtargetInfo.inc" + // SSE codegen depends on cmovs, and all SSE1+ processors support them. // All 64-bit processors support cmov. bool hasCMov() const { return HasCMov || X86SSELevel >= SSE1 || is64Bit(); } - bool hasSSE1() const { return X86SSELevel >= SSE1; } - bool hasSSE2() const { return X86SSELevel >= SSE2; } - bool hasSSE3() const { return X86SSELevel >= SSE3; } - bool hasSSSE3() const { return X86SSELevel >= SSSE3; } - bool hasSSE41() const { return X86SSELevel >= SSE41; } - bool hasSSE42() const { return X86SSELevel >= SSE42; } - bool hasAVX() const { return X86SSELevel >= AVX; } - bool hasAVX2() const { return X86SSELevel >= AVX2; } - bool hasAVX512() const { return X86SSELevel >= AVX512F; } + + bool useAA() const override { return UseAA; } bool hasInt256() const { return hasAVX2(); } - bool hasSSE4A() const { return HasSSE4A; } - bool hasMMX() const { return X863DNowLevel >= MMX; } - bool has3DNow() const { return X863DNowLevel >= ThreeDNow; } - bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; } - bool hasPOPCNT() const { return HasPOPCNT; } - bool hasAES() const { return HasAES; } - bool hasVAES() const { return HasVAES; } - bool hasFXSR() const { return HasFXSR; } - bool hasXSAVE() const { return HasXSAVE; } - bool hasXSAVEOPT() const { return HasXSAVEOPT; } - bool hasXSAVEC() const { return HasXSAVEC; } - bool hasXSAVES() const { return HasXSAVES; } - bool hasPCLMUL() const { return HasPCLMUL; } - bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; } - bool hasGFNI() const { return HasGFNI; } - // Prefer FMA4 to FMA - its better for commutation/memory folding and - // has equal or better performance on all supported targets. - bool hasFMA() const { return HasFMA; } - bool hasFMA4() const { return HasFMA4; } bool hasAnyFMA() const { return hasFMA() || hasFMA4(); } - bool hasXOP() const { return HasXOP; } - bool hasTBM() const { return HasTBM; } - bool hasLWP() const { return HasLWP; } - bool hasMOVBE() const { return HasMOVBE; } - bool hasRDRAND() const { return HasRDRAND; } - bool hasF16C() const { return HasF16C; } - bool hasFSGSBase() const { return HasFSGSBase; } - bool hasLZCNT() const { return HasLZCNT; } - bool hasBMI() const { return HasBMI; } - bool hasBMI2() const { return HasBMI2; } - bool hasVBMI() const { return HasVBMI; } - bool hasVBMI2() const { return HasVBMI2; } - bool hasIFMA() const { return HasIFMA; } - bool hasRTM() const { return HasRTM; } - bool hasADX() const { return HasADX; } - bool hasSHA() const { return HasSHA; } - bool hasPRFCHW() const { return HasPRFCHW; } - bool hasPREFETCHWT1() const { return HasPREFETCHWT1; } bool hasPrefetchW() const { // The PREFETCHW instruction was added with 3DNow but later CPUs gave it // its own CPUID bit as part of deprecating 3DNow. Intel eventually added // it and KNL has another that prefetches to L2 cache. We assume the // L1 version exists if the L2 version does. - return has3DNow() || hasPRFCHW() || hasPREFETCHWT1(); + return hasThreeDNow() || hasPRFCHW() || hasPREFETCHWT1(); } bool hasSSEPrefetch() const { // We implicitly enable these when we have a write prefix supporting cache // level OR if we have prfchw, but don't already have a read prefetch from // 3dnow. - return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1(); + return hasSSE1() || (hasPRFCHW() && !hasThreeDNow()) || hasPREFETCHWT1(); } - bool hasRDSEED() const { return HasRDSEED; } bool hasLAHFSAHF() const { return HasLAHFSAHF64 || !is64Bit(); } - bool hasMWAITX() const { return HasMWAITX; } - bool hasCLZERO() const { return HasCLZERO; } - bool hasCLDEMOTE() const { return HasCLDEMOTE; } - bool hasMOVDIRI() const { return HasMOVDIRI; } - bool hasMOVDIR64B() const { return HasMOVDIR64B; } - bool hasPTWRITE() const { return HasPTWRITE; } - bool isSHLDSlow() const { return IsSHLDSlow; } - bool isPMULLDSlow() const { return IsPMULLDSlow; } - bool isPMADDWDSlow() const { return IsPMADDWDSlow; } - bool isUnalignedMem16Slow() const { return IsUAMem16Slow; } - bool isUnalignedMem32Slow() const { return IsUAMem32Slow; } - bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; } bool hasCmpxchg16b() const { return HasCmpxchg16b && is64Bit(); } - bool useLeaForSP() const { return UseLeaForSP; } - bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; } - bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; } - bool hasSBBDepBreaking() const { return HasSBBDepBreaking; } - bool hasFastVariableCrossLaneShuffle() const { - return HasFastVariableCrossLaneShuffle; - } - bool hasFastVariablePerLaneShuffle() const { - return HasFastVariablePerLaneShuffle; - } - bool insertVZEROUPPER() const { return InsertVZEROUPPER; } - bool hasFastGather() const { return HasFastGather; } - bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; } - bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; } - bool hasFastLZCNT() const { return HasFastLZCNT; } - bool hasFastSHLDRotate() const { return HasFastSHLDRotate; } - bool hasFastBEXTR() const { return HasFastBEXTR; } - bool hasFastHorizontalOps() const { return HasFastHorizontalOps; } - bool hasFastScalarShiftMasks() const { return HasFastScalarShiftMasks; } - bool hasFastVectorShiftMasks() const { return HasFastVectorShiftMasks; } - bool hasFastMOVBE() const { return HasFastMOVBE; } - bool hasMacroFusion() const { return HasMacroFusion; } - bool hasBranchFusion() const { return HasBranchFusion; } - bool hasERMSB() const { return HasERMSB; } - bool hasFSRM() const { return HasFSRM; } - bool hasSlowDivide32() const { return HasSlowDivide32; } - bool hasSlowDivide64() const { return HasSlowDivide64; } - bool padShortFunctions() const { return PadShortFunctions; } - bool slowTwoMemOps() const { return SlowTwoMemOps; } - bool LEAusesAG() const { return LEAUsesAG; } - bool slowLEA() const { return SlowLEA; } - bool slow3OpsLEA() const { return Slow3OpsLEA; } - bool slowIncDec() const { return SlowIncDec; } - bool hasCDI() const { return HasCDI; } - bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; } - bool hasPFI() const { return HasPFI; } - bool hasERI() const { return HasERI; } - bool hasDQI() const { return HasDQI; } - bool hasBWI() const { return HasBWI; } - bool hasVLX() const { return HasVLX; } - bool hasFP16() const { return HasFP16; } - bool hasPKU() const { return HasPKU; } - bool hasVNNI() const { return HasVNNI; } - bool hasBF16() const { return HasBF16; } - bool hasVP2INTERSECT() const { return HasVP2INTERSECT; } - bool hasBITALG() const { return HasBITALG; } - bool hasSHSTK() const { return HasSHSTK; } - bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; } - bool hasCLWB() const { return HasCLWB; } - bool hasWBNOINVD() const { return HasWBNOINVD; } - bool hasRDPID() const { return HasRDPID; } - bool hasWAITPKG() const { return HasWAITPKG; } - bool hasPCONFIG() const { return HasPCONFIG; } - bool hasSGX() const { return HasSGX; } - bool hasINVPCID() const { return HasINVPCID; } - bool hasENQCMD() const { return HasENQCMD; } - bool hasKL() const { return HasKL; } - bool hasWIDEKL() const { return HasWIDEKL; } - bool hasHRESET() const { return HasHRESET; } - bool hasSERIALIZE() const { return HasSERIALIZE; } - bool hasTSXLDTRK() const { return HasTSXLDTRK; } - bool hasUINTR() const { return HasUINTR; } - bool hasCRC32() const { return HasCRC32; } - bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; } - bool useRetpolineIndirectBranches() const { - return UseRetpolineIndirectBranches; - } - bool hasAVXVNNI() const { return HasAVXVNNI; } - bool hasAMXTILE() const { return HasAMXTILE; } - bool hasAMXBF16() const { return HasAMXBF16; } - bool hasAMXINT8() const { return HasAMXINT8; } - bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; } - // These are generic getters that OR together all of the thunk types // supported by the subtarget. Therefore useIndirectThunk*() will return true // if any respective thunk feature is enabled. @@ -803,16 +212,6 @@ return useRetpolineIndirectBranches() || useLVIControlFlowIntegrity(); } - bool preferMaskRegisters() const { return PreferMaskRegisters; } - bool useSLMArithCosts() const { return UseSLMArithCosts; } - bool useGLMDivSqrtCosts() const { return UseGLMDivSqrtCosts; } - bool useLVIControlFlowIntegrity() const { return UseLVIControlFlowIntegrity; } - bool allowTaggedGlobals() const { return AllowTaggedGlobals; } - bool useLVILoadHardening() const { return UseLVILoadHardening; } - bool useSpeculativeExecutionSideEffectSuppression() const { - return UseSpeculativeExecutionSideEffectSuppression; - } - unsigned getPreferVectorWidth() const { return PreferVectorWidth; } unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; } @@ -839,11 +238,6 @@ bool isXRaySupported() const override { return is64Bit(); } - /// TODO: to be removed later and replaced with suitable properties - bool isAtom() const { return X86ProcFamily == IntelAtom; } - bool useSoftFloat() const { return UseSoftFloat; } - bool useAA() const override { return UseAA; } - /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for /// no-sse2). There isn't any reason to disable it if the target processor /// supports it. @@ -895,9 +289,9 @@ bool isOSWindows() const { return TargetTriple.isOSWindows(); } - bool isTargetWin64() const { return In64BitMode && isOSWindows(); } + bool isTargetWin64() const { return Is64Bit && isOSWindows(); } - bool isTargetWin32() const { return !In64BitMode && isOSWindows(); } + bool isTargetWin32() const { return !Is64Bit && isOSWindows(); } bool isPICStyleGOT() const { return PICStyle == PICStyles::Style::GOT; } bool isPICStyleRIPRel() const { return PICStyle == PICStyles::Style::RIPRel; } diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp --- a/llvm/lib/Target/X86/X86Subtarget.cpp +++ b/llvm/lib/Target/X86/X86Subtarget.cpp @@ -53,7 +53,6 @@ X86EarlyIfConv("x86-early-ifcvt", cl::Hidden, cl::desc("Enable early if-conversion on X86")); - /// Classify a blockaddress reference for the current subtarget according to how /// we should reference it in a non-pcrel context. unsigned char X86Subtarget::classifyBlockAddressReference() const { @@ -249,7 +248,7 @@ // FIXME: I386 PE/COFF supports PC relative calls using IMAGE_REL_I386_REL32 // but WinCOFFObjectWriter::RecordRelocation cannot emit them. Once it does, // the following check for Win32 should be removed. - if (In64BitMode || isTargetWin32()) + if (Is64Bit || isTargetWin32()) return false; return isTargetELF() || TM.getRelocationModel() == Reloc::Static; } @@ -276,12 +275,12 @@ // introduced with Intel's Nehalem/Silvermont and AMD's Family10h // micro-architectures respectively. if (hasSSE42() || hasSSE4A()) - IsUAMem16Slow = false; + IsUnalignedMem16Slow = false; LLVM_DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel << ", 3DNowLevel " << X863DNowLevel << ", 64bit " << HasX86_64 << "\n"); - if (In64BitMode && !HasX86_64) + if (Is64Bit && !HasX86_64) report_fatal_error("64-bit code requested on a subtarget that doesn't " "support it!"); @@ -291,7 +290,7 @@ if (StackAlignOverride) stackAlignment = *StackAlignOverride; else if (isTargetDarwin() || isTargetLinux() || isTargetKFreeBSD() || - isTargetNaCl() || In64BitMode) + isTargetNaCl() || Is64Bit) stackAlignment = Align(16); // Consume the vector width attribute or apply any target specific limit. diff --git a/llvm/utils/TableGen/SubtargetEmitter.cpp b/llvm/utils/TableGen/SubtargetEmitter.cpp --- a/llvm/utils/TableGen/SubtargetEmitter.cpp +++ b/llvm/utils/TableGen/SubtargetEmitter.cpp @@ -122,8 +122,7 @@ void EmitSchedModel(raw_ostream &OS); void EmitHwModeCheck(const std::string &ClassName, raw_ostream &OS); - void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures, - unsigned NumProcs); + void ParseFeaturesFunction(raw_ostream &OS); public: SubtargetEmitter(RecordKeeper &R, CodeGenTarget &TGT) @@ -1685,9 +1684,13 @@ // ParseFeaturesFunction - Produces a subtarget specific function for parsing // the subtarget features string. // -void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS, - unsigned NumFeatures, - unsigned NumProcs) { +void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) { + OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n"; + OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n\n"; + + OS << "#include \"llvm/Support/Debug.h\"\n"; + OS << "#include \"llvm/Support/raw_ostream.h\"\n\n"; + std::vector Features = Records.getAllDerivedDefinitions("SubtargetFeature"); llvm::sort(Features, LessRecord()); @@ -1702,13 +1705,10 @@ << " LLVM_DEBUG(dbgs() << \"\\nCPU:\" << CPU);\n" << " LLVM_DEBUG(dbgs() << \"\\nTuneCPU:\" << TuneCPU << \"\\n\\n\");\n"; - if (Features.empty()) { - OS << "}\n"; - return; - } + OS << " InitMCProcessorInfo(CPU, TuneCPU, FS);\n"; - OS << " InitMCProcessorInfo(CPU, TuneCPU, FS);\n" - << " const FeatureBitset &Bits = getFeatureBits();\n"; + if (!Features.empty()) + OS << " const FeatureBitset &Bits = getFeatureBits();\n"; for (Record *R : Features) { // Next record @@ -1728,6 +1728,47 @@ } OS << "}\n"; + OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n"; + + OS << "\n#ifdef GET_SUBTARGETINFO_FEATURE_MEMBER\n"; + OS << "#undef GET_SUBTARGETINFO_FEATURE_MEMBER\n\n"; + std::set> AttrVals; + std::set Attrs; + for (Record *R : Features) { + StringRef Attribute = R->getValueAsString("Attribute"); + StringRef Value = R->getValueAsString("Value"); + bool HasTrivalInterface = R->getValueAsBit("TrivalInterface"); + if (HasTrivalInterface) + AttrVals.insert({Attribute, Value}); + if (Attrs.find(Attribute) != Attrs.end()) + continue; + Attrs.insert(Attribute); + StringRef Desc = R->getValueAsString("Desc"); + if (!Desc.empty()) + OS << "/// " << Desc << "\n"; + if (Value == "true" || Value == "false") + OS << "bool "; + else + OS << "unsigned "; + OS << Attribute << " = {};\n"; + } + OS << "#endif // GET_SUBTARGETINFO_FEATURE_MEMBER\n\n"; + + OS << "\n#ifdef GET_SUBTARGETINFO_FEATURE_INTERFACE\n"; + for (auto AttrVal : AttrVals) { + StringRef Attribute = AttrVal.first; + StringRef Value = AttrVal.second; + OS << "bool "; + if (Value == "true" || Value == "false") + OS << toLower(Attribute[0]) << Attribute.substr(1) << "() const { return " + << Attribute; + else + OS << "has" << Value << "() const { return " << Attribute + << " >= " << Value; + OS << "; }\n"; + } + OS << "#undef GET_SUBTARGETINFO_FEATURE_INTERFACE\n\n"; + OS << "#endif // GET_SUBTARGETINFO_FEATURE_INTERFACE\n\n"; } void SubtargetEmitter::emitGenMCSubtargetInfo(raw_ostream &OS) { @@ -1853,14 +1894,7 @@ OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n"; - OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n"; - OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n\n"; - - OS << "#include \"llvm/Support/Debug.h\"\n"; - OS << "#include \"llvm/Support/raw_ostream.h\"\n\n"; - ParseFeaturesFunction(OS, NumFeatures, NumProcs); - - OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n"; + ParseFeaturesFunction(OS); // Create a TargetSubtargetInfo subclass to hide the MC layer initialization. OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n";