diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3753,7 +3753,14 @@
     // Use PC-relative addressing to access the GOT for this symbol, then load
     // the address from the GOT. This generates the pattern (PseudoLA sym),
     // which expands to (ld (addi (auipc %got_pcrel_hi(sym)) %pcrel_lo(auipc))).
-    return SDValue(DAG.getMachineNode(RISCV::PseudoLA, DL, Ty, Addr), 0);
+    MachineSDNode *LoadAddr = DAG.getMachineNode(RISCV::PseudoLA, DL, Ty, Addr);
+    MachinePointerInfo MPI =
+        MachinePointerInfo::getGOT(DAG.getMachineFunction());
+    DAG.setNodeMemRefs(LoadAddr, {DAG.getMachineFunction().getMachineMemOperand(
+                                 MPI, MachineMemOperand::MOLoad,
+                                 Subtarget.getXLenVT().getSizeInBits() / 8, Align(8))});
+
+    return SDValue(LoadAddr, 0);
   }
 
   switch (getTargetMachine().getCodeModel()) {
diff --git a/llvm/test/CodeGen/RISCV/pseudola-add-memop.ll b/llvm/test/CodeGen/RISCV/pseudola-add-memop.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pseudola-add-memop.ll
@@ -0,0 +1,35 @@
+; RUN: llc -mtriple=riscv64 -stop-after=finalize-isel -relocation-model=pic -o - %s | FileCheck --check-prefix=MIR-RV64 %s
+; RUN: llc -mtriple=riscv32 -stop-after=finalize-isel -relocation-model=pic -o - %s | FileCheck --check-prefix=MIR-RV32 %s
+
+@global = global i32 0, align 4
+
+
+; MIR-RV64:  %7:gpr = PseudoLA @global :: (load (s64) from got)
+; MIR-RV32:  %6:gpr = PseudoLA @global :: (load (s32) from got, align 8)
+define void @test(i32 noundef signext %n) local_unnamed_addr #0 {
+entry:
+  %cmp3 = icmp sgt i32 %n, 0
+  br i1 %cmp3, label %for.body, label %for.cond.cleanup
+
+for.cond.cleanup:                                 ; preds = %for.body, %entry
+  ret void
+
+for.body:                                         ; preds = %entry, %for.body
+  %i.04 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
+  %0 = load volatile i32, i32* @global, align 4, !tbaa !5
+  %add = add nsw i32 %0, 1
+  store volatile i32 %add, i32* @global, align 4, !tbaa !5
+  %inc = add nuw nsw i32 %i.04, 1
+  %cmp = icmp slt i32 %inc, %n
+  br i1 %cmp, label %for.body, label %for.cond.cleanup, !llvm.loop !9
+}
+
+
+
+!0 = !{i32 1, !"wchar_size", i32 4}
+!5 = !{!6, !6, i64 0}
+!6 = !{!"int", !7, i64 0}
+!7 = !{!"omnipotent char", !8, i64 0}
+!8 = !{!"Simple C/C++ TBAA"}
+!9 = distinct !{!9, !10}
+!10 = !{!"llvm.loop.mustprogress"}