diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -98,6 +98,8 @@ }; static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { + {"zihintntl", RISCVExtensionVersion{0, 2}}, + {"zbe", RISCVExtensionVersion{0, 93}}, {"zbf", RISCVExtensionVersion{0, 93}}, {"zbm", RISCVExtensionVersion{0, 93}}, diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -48,6 +48,13 @@ AssemblerPredicate<(all_of FeatureStdExtZihintpause), "'Zihintpause' (Pause Hint)">; +def FeatureStdExtZihintntl + : SubtargetFeature<"experimental-zihintntl", "HasStdExtZihintntl", "true", + "'zihintntl' (Non-Temporal Locality Hints)">; +def HasStdExtZihintntl : Predicate<"Subtarget->hasStdExtZihintntl()">, + AssemblerPredicate<(all_of FeatureStdExtZihintntl), + "'Zihintntl' (Non-Temporal Locality Hints)">; + def FeatureStdExtZfhmin : SubtargetFeature<"zfhmin", "HasStdExtZfhmin", "true", "'Zfhmin' (Half-Precision Floating-Point Minimal)", diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -904,6 +904,13 @@ def : InstAlias<"hfence.vvma", (HFENCE_VVMA X0, X0)>; def : InstAlias<"hfence.vvma $rs", (HFENCE_VVMA GPR:$rs, X0)>; +let Predicates = [HasStdExtZihintntl] in { + def : InstAlias<"ntl.p1", (ADD X0, X0, X2)>; + def : InstAlias<"ntl.pall", (ADD X0, X0, X3)>; + def : InstAlias<"ntl.s1", (ADD X0, X0, X4)>; + def : InstAlias<"ntl.all", (ADD X0, X0, X5)>; +} // Predicates = [HasStdExtZihintntl] + let EmitPriority = 0 in { def : InstAlias<"lb $rd, (${rs1})", (LB GPR:$rd, GPR:$rs1, 0)>; diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -66,6 +66,7 @@ bool HasStdExtD = false; bool HasStdExtC = false; bool HasStdExtZihintpause = false; + bool HasStdExtZihintntl = false; bool HasStdExtZba = false; bool HasStdExtZbb = false; bool HasStdExtZbc = false; @@ -163,6 +164,7 @@ bool hasStdExtC() const { return HasStdExtC; } bool hasStdExtV() const { return HasStdExtV; } bool hasStdExtZihintpause() const { return HasStdExtZihintpause; } + bool hasStdExtZihintntl() const { return HasStdExtZihintntl; } bool hasStdExtZba() const { return HasStdExtZba; } bool hasStdExtZbb() const { return HasStdExtZbb; } bool hasStdExtZbc() const { return HasStdExtZbc; } diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -6,6 +6,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+d %s -o - | FileCheck --check-prefix=RV32D %s ; RUN: llc -mtriple=riscv32 -mattr=+c %s -o - | FileCheck --check-prefix=RV32C %s ; RUN: llc -mtriple=riscv32 -mattr=+zihintpause %s -o - | FileCheck --check-prefix=RV32ZIHINTPAUSE %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-zihintntl %s -o - | FileCheck --check-prefix=RV32ZIHINTNTL %s ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin %s -o - | FileCheck --check-prefix=RV32ZFHMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+zfh %s -o - | FileCheck --check-prefix=RV32ZFH %s ; RUN: llc -mtriple=riscv32 -mattr=+zba %s -o - | FileCheck --check-prefix=RV32ZBA %s @@ -42,6 +43,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefix=RV64D %s ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefix=RV64C %s ; RUN: llc -mtriple=riscv64 -mattr=+zihintpause %s -o - | FileCheck --check-prefix=RV64ZIHINTPAUSE %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-zihintntl %s -o - | FileCheck --check-prefix=RV64ZIHINTNTL %s ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin %s -o - | FileCheck --check-prefix=RV64ZFHMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+zfh %s -o - | FileCheck --check-prefix=RV64ZFH %s ; RUN: llc -mtriple=riscv64 -mattr=+zba %s -o - | FileCheck --check-prefix=RV64ZBA %s @@ -79,6 +81,7 @@ ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0" ; RV32C: .attribute 5, "rv32i2p0_c2p0" ; RV32ZIHINTPAUSE: .attribute 5, "rv32i2p0_zihintpause2p0" +; RV32ZIHINTNTL: .attribute 5, "rv32i2p0_zihintntl0p2" ; RV32ZFHMIN: .attribute 5, "rv32i2p0_f2p0_zfhmin1p0" ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh1p0" ; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0" @@ -116,6 +119,7 @@ ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0" ; RV64C: .attribute 5, "rv64i2p0_c2p0" ; RV64ZIHINTPAUSE: .attribute 5, "rv64i2p0_zihintpause2p0" +; RV64ZIHINTNTL: .attribute 5, "rv64i2p0_zihintntl0p2" ; RV64ZFHMIN: .attribute 5, "rv64i2p0_f2p0_zfhmin1p0" ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh1p0" ; RV64ZBA: .attribute 5, "rv64i2p0_zba1p0" diff --git a/llvm/test/MC/RISCV/rv32zihintntl-valid.s b/llvm/test/MC/RISCV/rv32zihintntl-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32zihintntl-valid.s @@ -0,0 +1,26 @@ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zihintntl -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zihintntl < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zihintntl < %s \ +# RUN: | llvm-objdump --mattr=+experimental-zihintntl -M no-aliases -d -r - \ +# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s + +# CHECK-ASM-AND-OBJ: add zero, zero, sp +# CHECK-ASM: encoding: [0x33,0x00,0x20,0x00] +ntl.p1 + +# CHECK-ASM-AND-OBJ: add zero, zero, gp +# CHECK-ASM: encoding: [0x33,0x00,0x30,0x00] +ntl.pall + +# CHECK-ASM-AND-OBJ: add zero, zero, tp +# CHECK-ASM: encoding: [0x33,0x00,0x40,0x00] +ntl.s1 + +# CHECK-ASM-AND-OBJ: add zero, zero, t0 +# CHECK-ASM: encoding: [0x33,0x00,0x50,0x00] +ntl.all