diff --git a/llvm/test/CodeGen/X86/dag-test-mov64ri.ll b/llvm/test/CodeGen/X86/dag-test-mov64ri.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/X86/dag-test-mov64ri.ll
@@ -0,0 +1,103 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
+
+define i1 @f_shr_testb(i64 %a) {
+; CHECK-LABEL: f_shr_testb:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movabsq $287104476244869120, %rax # imm = 0x3FC000000000000
+; CHECK-NEXT:    testq %rax, %rdi
+; CHECK-NEXT:    setne %al
+; CHECK-NEXT:    retq
+  %v0 = and i64 %a, 287104476244869120  ; 0xff << 50
+  %v1 = icmp ne i64 %v0, 0
+  ret i1 %v1
+}
+
+define i1 @f_shr_testw(i64 %a) {
+; CHECK-LABEL: f_shr_testw:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movabsq $562941363486720, %rax # imm = 0x1FFFE00000000
+; CHECK-NEXT:    testq %rax, %rdi
+; CHECK-NEXT:    setne %al
+; CHECK-NEXT:    retq
+  %v0 = and i64 %a, 562941363486720  ; 0xffff << 33
+  %v1 = icmp ne i64 %v0, 0
+  ret i1 %v1
+}
+
+define i1 @f_shr_testl(i64 %a) {
+; CHECK-LABEL: f_shr_testl:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movabsq $549755813760, %rax # imm = 0x7FFFFFFF80
+; CHECK-NEXT:    testq %rax, %rdi
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    retq
+  %v0 = and i64 %a, 549755813760  ; 0xffffffff << 7
+  %v1 = icmp eq i64 %v0, 0
+  ret i1 %v1
+}
+
+define i1 @f_shr(i64 %a) {
+; CHECK-LABEL: f_shr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    shrq $56, %rdi
+; CHECK-NEXT:    setne %al
+; CHECK-NEXT:    retq
+  %v0 = and i64 %a, 18374686479671623680  ; 0xff << 56
+  %v1 = icmp ne i64 %v0, 0
+  ret i1 %v1
+}
+
+define i1 @f_no_opt0(i64 %a) {
+; CHECK-LABEL: f_no_opt0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movabsq $529956014653440, %rax # imm = 0x1E1FE00000000
+; CHECK-NEXT:    testq %rax, %rdi
+; CHECK-NEXT:    setne %al
+; CHECK-NEXT:    retq
+  %v0 = and i64 %a, 529956014653440 ; 0xf0ff << 33
+  %v1 = icmp ne i64 %v0, 0
+  ret i1 %v1
+}
+
+define i1 @f_no_opt1(i64 %a) {
+; CHECK-LABEL: f_no_opt1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movabsq $529956014653440, %rax # imm = 0x1E1FE00000000
+; CHECK-NEXT:    testq %rax, %rdi
+; CHECK-NEXT:    setne %al
+; CHECK-NEXT:    retq
+  %v0 = and i64 %a, 529956014653440 ; 0xff << 7
+  %v1 = icmp ne i64 %v0, 0
+  ret i1 %v1
+}
+
+@g = global i64 0
+
+define i1 @f_no_opt2(i64 %a) {
+; CHECK-LABEL: f_no_opt2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq g@GOTPCREL(%rip), %rax
+; CHECK-NEXT:    movabsq $287104476244869120, %rcx # imm = 0x3FC000000000000
+; CHECK-NEXT:    movq %rcx, (%rax)
+; CHECK-NEXT:    testq %rcx, %rdi
+; CHECK-NEXT:    setne %al
+; CHECK-NEXT:    retq
+  store i64 287104476244869120, i64* @g
+  %v0 = and i64 %a, 287104476244869120  ; 0xff << 50
+  %v1 = icmp ne i64 %v0, 0
+  ret i1 %v1
+}
+
+define i1 @f_no_opt3(i64 %a) {
+; CHECK-LABEL: f_no_opt3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movabsq $-72057594037927936, %rax # imm = 0xFF00000000000000
+; CHECK-NEXT:    andq %rdi, %rax
+; CHECK-NEXT:    cmpq $12345, %rax # imm = 0x3039
+; CHECK-NEXT:    setl %al
+; CHECK-NEXT:    retq
+  %v0 = and i64 %a, 18374686479671623680  ; 0xff << 56
+  %v1 = icmp slt i64 %v0, 12345
+  ret i1 %v1
+}