diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp @@ -77,11 +77,8 @@ static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { - if (CPU.empty()) + if (CPU.empty() || CPU == "generic") CPU = TT.isArch64Bit() ? "generic-rv64" : "generic-rv32"; - if (CPU == "generic") - report_fatal_error(Twine("CPU 'generic' is not supported. Use ") + - (TT.isArch64Bit() ? "generic-rv64" : "generic-rv32")); return createRISCVMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS); } diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -452,6 +452,9 @@ def : ProcessorModel<"generic-rv32", NoSchedModel, []>; def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>; +// Support generic for compatibility with other targets. The triple will be used +// to change to the appropriate rv32/rv64 version. +def : ProcessorModel<"generic", NoSchedModel, []>; def : ProcessorModel<"rocket-rv32", RocketModel, []>; def : ProcessorModel<"rocket-rv64", RocketModel, [Feature64Bit]>; diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp --- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp @@ -69,11 +69,8 @@ StringRef ABIName) { // Determine default and user-specified characteristics bool Is64Bit = TT.isArch64Bit(); - if (CPU.empty()) + if (CPU.empty() || CPU == "generic") CPU = Is64Bit ? "generic-rv64" : "generic-rv32"; - if (CPU == "generic") - report_fatal_error(Twine("CPU 'generic' is not supported. Use ") + - (Is64Bit ? "generic-rv64" : "generic-rv32")); if (TuneCPU.empty()) TuneCPU = CPU;