diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -4722,18 +4722,19 @@
 Register
 MipsTargetLowering::getRegisterByName(const char *RegName, LLT VT,
                                       const MachineFunction &MF) const {
-  // Named registers is expected to be fairly rare. For now, just support $28
-  // since the linux kernel uses it.
+  // The Linux kernel uses $28 and sp.
   if (Subtarget.isGP64bit()) {
     Register Reg = StringSwitch<Register>(RegName)
-                         .Case("$28", Mips::GP_64)
-                         .Default(Register());
+                       .Case("$28", Mips::GP_64)
+                       .Case("sp", Mips::SP_64)
+                       .Default(Register());
     if (Reg)
       return Reg;
   } else {
     Register Reg = StringSwitch<Register>(RegName)
-                         .Case("$28", Mips::GP)
-                         .Default(Register());
+                       .Case("$28", Mips::GP)
+                       .Case("sp", Mips::SP)
+                       .Default(Register());
     if (Reg)
       return Reg;
   }
diff --git a/llvm/test/CodeGen/Mips/named-register-n32.ll b/llvm/test/CodeGen/Mips/named-register-n32.ll
--- a/llvm/test/CodeGen/Mips/named-register-n32.ll
+++ b/llvm/test/CodeGen/Mips/named-register-n32.ll
@@ -1,18 +1,29 @@
-; RUN: llc -mtriple=mips64 -relocation-model=static -mattr=+noabicalls -target-abi n32 < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips64 -relocation-model=static -mattr=+noabicalls \
+; RUN:   -target-abi n32 < %s | FileCheck %s
 
-define i32* @get_gp() {
-entry:
-  %0 = call i64 @llvm.read_register.i64(metadata !0)
-  %1 = trunc i64 %0 to i32
-  %2 = inttoptr i32 %1 to i32*
-  ret i32* %2
-}
+declare i64 @llvm.read_register.i64(metadata)
 
+define i64 @get_gp() {
 ; CHECK-LABEL: get_gp:
-; CHECK:           sll $2, $gp, 0
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    move $2, $gp
+  %1 = call i64 @llvm.read_register.i64(metadata !0)
+  ret i64 %1
+}
 
-declare i64 @llvm.read_register.i64(metadata)
+define i64 @get_sp() {
+; CHECK-LABEL: get_sp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    move $2, $sp
+  %1 = call i64 @llvm.read_register.i64(metadata !1)
+  ret i64 %1
+}
 
 !llvm.named.register.$28 = !{!0}
+!llvm.named.register.sp = !{!1}
 
 !0 = !{!"$28"}
+!1 = !{!"sp"}
diff --git a/llvm/test/CodeGen/Mips/named-register-n64.ll b/llvm/test/CodeGen/Mips/named-register-n64.ll
--- a/llvm/test/CodeGen/Mips/named-register-n64.ll
+++ b/llvm/test/CodeGen/Mips/named-register-n64.ll
@@ -1,17 +1,29 @@
-; RUN: llc -mtriple=mips64 -relocation-model=static -mattr=+noabicalls < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips64 -relocation-model=static -mattr=+noabicalls \
+; RUN:   < %s | FileCheck %s
 
-define i32* @get_gp() {
-entry:
-  %0 = call i64 @llvm.read_register.i64(metadata !0)
-  %1 = inttoptr i64 %0 to i32*
-  ret i32* %1
-}
+declare i64 @llvm.read_register.i64(metadata)
 
+define i64 @get_gp() {
 ; CHECK-LABEL: get_gp:
-; CHECK:           move $2, $gp
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    move $2, $gp
+  %1 = call i64 @llvm.read_register.i64(metadata !0)
+  ret i64 %1
+}
 
-declare i64 @llvm.read_register.i64(metadata)
+define i64 @get_sp() {
+; CHECK-LABEL: get_sp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    move $2, $sp
+  %1 = call i64 @llvm.read_register.i64(metadata !1)
+  ret i64 %1
+}
 
 !llvm.named.register.$28 = !{!0}
+!llvm.named.register.sp = !{!1}
 
 !0 = !{!"$28"}
+!1 = !{!"sp"}
diff --git a/llvm/test/CodeGen/Mips/named-register-o32.ll b/llvm/test/CodeGen/Mips/named-register-o32.ll
--- a/llvm/test/CodeGen/Mips/named-register-o32.ll
+++ b/llvm/test/CodeGen/Mips/named-register-o32.ll
@@ -1,17 +1,29 @@
-; RUN: llc -mtriple=mips -relocation-model=static -mattr=+noabicalls < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=mips -relocation-model=static -mattr=+noabicalls \
+; RUN:   < %s | FileCheck %s
 
-define i32* @get_gp() {
-entry:
-  %0 = call i32 @llvm.read_register.i32(metadata !0)
-  %1 = inttoptr i32 %0 to i32*
-  ret i32* %1
-}
+declare i32 @llvm.read_register.i32(metadata)
 
+define i32 @get_gp() {
 ; CHECK-LABEL: get_gp:
-; CHECK:           move $2, $gp
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    move $2, $gp
+  %1 = call i32 @llvm.read_register.i32(metadata !0)
+  ret i32 %1
+}
 
-declare i32 @llvm.read_register.i32(metadata)
+define i32 @get_sp() {
+; CHECK-LABEL: get_sp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    jr $ra
+; CHECK-NEXT:    move $2, $sp
+  %1 = call i32 @llvm.read_register.i32(metadata !1)
+  ret i32 %1
+}
 
 !llvm.named.register.$28 = !{!0}
+!llvm.named.register.sp = !{!1}
 
 !0 = !{!"$28"}
+!1 = !{!"sp"}