Index: lib/builtins/arm/aeabi_cdcmp.S =================================================================== --- /dev/null +++ lib/builtins/arm/aeabi_cdcmp.S @@ -0,0 +1,109 @@ +//===-- aeabi_cdcmp.S - EABI cdcmp* implementation ------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is dual licensed under the MIT and the University of Illinois Open +// Source Licenses. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "../assembly.h" + +#ifndef __LITTLE_ENDIAN__ +#error FIXME +#endif + +#define APSR_Z (1 << 30) +#define APSR_C (1 << 29) + +// void __aeabi_cdcmpeq(double a, double b) { +// // __aeabi_cdcmpeq_helper takes the most significant words of a, b +// if (__aeabi_cdcmpeq(a, b)) { Z = 0, C = 1 } +// else { __aeabi_cdcmple(a, b); } +// } + + .syntax unified + .p2align 2 +DEFINE_COMPILERRT_FUNCTION(__aeabi_cdcmpeq) + push {r0, r1, r2, r3, lr} + mov r0, r1 + mov r1, r3 + bl __aeabi_cdcmpeq_helper + cmp r0, #1 + bne 1f + msr CPSR_f, #APSR_C + pop {r0, r1, r2, r3, pc} +1: + // __aeabi_cdcmple restores registers + pop {r0, r1, r2, r3} + bl __aeabi_cdcmple + pop {pc} +END_COMPILERRT_FUNCTION(__aeabi_cdcmpeq) + + +// void __aeabi_cdcmple(double a, double b) { +// if (__aeabi_dcmplt(a, b)) { +// Z = 1; C = 0; +// } else if (__aeabi_dcmpeq(a, b)) { +// Z = 0; C = 1; +// } else { +// Z = 0; C = 0; +// } +// } + + .syntax unified + .p2align 2 +DEFINE_COMPILERRT_FUNCTION(__aeabi_cdcmple) + push {r0, r1, r2, r3, lr} + bl __aeabi_dcmplt + cmp r0, #1 + bne 2f + msr CPSR_f, #0 + pop {r0, r1, r2, r3, pc} + +2: + ldm sp, {r0, r1, r2, r3} + bl __aeabi_dcmpeq + cmp r0, #1 + bne 3f + msr CPSR_f, #(APSR_Z | APSR_C) + pop {r0, r1, r2, r3, pc} + +3: + msr CPSR_f, #APSR_C + pop {r0, r1, r2, r3, pc} +END_COMPILERRT_FUNCTION(__aeabi_cdcmple) + +// int __aeabi_cdrcmple(double a, double b) { +// return __aeabi_cdcmple(b, a); +// } + + .syntax unified + .p2align 2 +DEFINE_COMPILERRT_FUNCTION(__aeabi_cdrcmple) + push {lr} + + // Swap r0 and r2 + mov ip, r0 + mov r0, r2 + mov r2, ip + + // Swap r1 and r3 + mov ip, r1 + mov r1, r3 + mov r3, ip + + bl __aeabi_cdcmple + + // Swap them back + mov ip, r0 + mov r0, r2 + mov r2, ip + + mov ip, r1 + mov r1, r3 + mov r3, ip + + pop {pc} +END_COMPILERRT_FUNCTION(__aeabi_cdrcmple) + Index: lib/builtins/arm/aeabi_cdcmpeq_helper.c =================================================================== --- /dev/null +++ lib/builtins/arm/aeabi_cdcmpeq_helper.c @@ -0,0 +1,20 @@ +//===-- lib/arm/aeabi_cdcmpeq_helper.c - Helper for cdcmpeq ---------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is dual licensed under the MIT and the University of Illinois Open +// Source Licenses. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include + +static int isnan_d(int32_t a) { + return (a & 0x7ff << 20) == 0x7ff << 20; +} + +__attribute__((pcs("aapcs"))) +__attribute__((visibility("hidden"))) +int __aeabi_cdcmpeq_helper(int32_t a, int32_t b) { + return isnan_d(a) || isnan_d(b); +} Index: lib/builtins/arm/aeabi_cfcmp.S =================================================================== --- /dev/null +++ lib/builtins/arm/aeabi_cfcmp.S @@ -0,0 +1,90 @@ +//===-- aeabi_cfcmp.S - EABI cfcmp* implementation ------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is dual licensed under the MIT and the University of Illinois Open +// Source Licenses. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "../assembly.h" + +// void __aeabi_cfcmpeq(float a, float b) { +// Z = fcmpeq(a, b); +// } + +#define APSR_Z (1 << 30) +#define APSR_C (1 << 29) + + .syntax unified + .p2align 2 +DEFINE_COMPILERRT_FUNCTION(__aeabi_cfcmpeq) + push {r0, r1, r2, r3, lr} + bl __aeabi_cfcmpeq_helper + cmp r0, #1 + bne 1f + msr CPSR_f, #APSR_C + pop {r0, r1, r2, r3, pc} +1: + pop {r0, r1, r2, r3} + bl __aeabi_cfcmple + pop {pc} +END_COMPILERRT_FUNCTION(__aeabi_cfcmpeq) + + +// void __aeabi_cfcmple(float a, float b) { +// if (__aeabi_fcmplt(a, b)) { +// Z = 0; C = 0; +// } else if (__aeabi_fcmpeq(a, b)) { +// Z = 1; C = 1; +// } else { +// Z = 0; C = 1; +// } +// } + + .syntax unified + .p2align 2 +DEFINE_COMPILERRT_FUNCTION(__aeabi_cfcmple) + push {r0, r1, r2, r3, lr} + bl __aeabi_fcmplt + cmp r0, #1 + bne 2f + msr CPSR_f, #0 + pop {r0, r1, r2, r3, pc} + +2: + ldm sp, {r0, r1} + bl __aeabi_fcmpeq + cmp r0, #1 + bne 3f + msr CPSR_f, #(APSR_Z | APSR_C) + pop {r0, r1, r2, r3, pc} + +3: + msr CPSR_f, #APSR_C + pop {r0, r1, r2, r3, pc} +END_COMPILERRT_FUNCTION(__aeabi_cfcmple) + +// int __aeabi_cfrcmple(float a, float b) { +// return __aeabi_cfcmple(b, a); +// } + + .syntax unified + .p2align 2 +DEFINE_COMPILERRT_FUNCTION(__aeabi_cfrcmple) + push {lr} + + // Swap r0 and r1 + mov ip, r0 + mov r0, r1 + mov r1, ip + + bl __aeabi_cfcmple + + // Swap them back + mov ip, r0 + mov r0, r1 + mov r1, ip + pop {pc} +END_COMPILERRT_FUNCTION(__aeabi_cfrcmple) + Index: lib/builtins/arm/aeabi_cfcmpeq_helper.c =================================================================== --- /dev/null +++ lib/builtins/arm/aeabi_cfcmpeq_helper.c @@ -0,0 +1,20 @@ +//===-- lib/arm/aeabi_cfcmpeq_helper.c - Helper for cfcmpeq ---------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is dual licensed under the MIT and the University of Illinois Open +// Source Licenses. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include + +static int isnan_f(int32_t a) { + return (a & 0xff << 23) == 0xff << 23; +} + +__attribute__((pcs("aapcs"))) +__attribute__((visibility("hidden"))) +int __aeabi_cfcmpeq_helper(int32_t a, int32_t b) { + return isnan_f(a) || isnan_f(b); +} Index: test/builtins/Unit/arm/aeabi_cdcmpeq_test.c =================================================================== --- /dev/null +++ test/builtins/Unit/arm/aeabi_cdcmpeq_test.c @@ -0,0 +1,74 @@ +//===-- aeabi_cdcmpeq.c - Test __aeabi_cdcmpeq ----------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is dual licensed under the MIT and the University of Illinois Open +// Source Licenses. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file tests __aeabi_cdcmpeq for the compiler_rt library. +// +//===----------------------------------------------------------------------===// + +#include +#include +#include +#include + +#if __arm__ +#include "call_apsr.h" + +extern __attribute__((pcs("aapcs"))) void __aeabi_cdcmpeq(double a, double b); + +union double_bits { + double d; + struct b { + uint64_t m: 52; + uint64_t e: 11; + uint64_t s: 1; + } b; +}; + +int test__aeabi_cdcmpeq(double a, double b, int expected) +{ + uint32_t cpsr_value = call_apsr_d(a, b, __aeabi_cdcmpeq); + union cpsr cpsr = { .value = cpsr_value }; + if (expected != cpsr.flags.z) { + printf("error in __aeabi_cdcmpeq(%f, %f) => Z = %d, expected %d\n", + a, b, cpsr.flags.z, expected); + return 1; + } + return 0; +} +#endif + +int main() +{ + double SNAN; + union double_bits fb; + fb.b.s = 0; + fb.b.e = 0xff; + fb.b.m = (1 << 22) + 1; + SNAN = fb.d; + +#if __arm__ + if (test__aeabi_cdcmpeq(1.0, 1.0, 1)) + return 1; + if (test__aeabi_cdcmpeq(1234.567, 765.4321, 0)) + return 1; + if (test__aeabi_cdcmpeq(-123.0, -678.0, 0)) + return 1; + if (test__aeabi_cdcmpeq(0.0, -0.0, 1)) + return 1; + if (test__aeabi_cdcmpeq(1.0, NAN, 0)) + return 1; + if (test__aeabi_cdcmpeq(NAN, 1.0, 0)) + return 1; + if (test__aeabi_cdcmpeq(SNAN, 1.0, 0)) + return 1; +#else + printf("skipped\n"); +#endif + return 0; +} Index: test/builtins/Unit/arm/aeabi_cdcmple_test.c =================================================================== --- /dev/null +++ test/builtins/Unit/arm/aeabi_cdcmple_test.c @@ -0,0 +1,83 @@ +//===-- aeabi_cdcmple.c - Test __aeabi_cdcmple and __aeabi_cdrcmple--------===// +// +// The LLVM Compiler Infrastructure +// +// This file is dual licensed under the MIT and the University of Illinois Open +// Source Licenses. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file tests __aeabi_cdcmple and __aeabi_cdrcmple for the compiler_rt +// library. +// +//===----------------------------------------------------------------------===// + +#include +#include +#include +#include + +#include "call_apsr.h" + +#if __arm__ + +extern __attribute__((pcs("aapcs"))) void __aeabi_cdcmple(double a, double b); +extern __attribute__((pcs("aapcs"))) void __aeabi_cdrcmple(double a, double b); + +int test__aeabi_cdcmple(double a, double b) +{ + int32_t cpsr_value = call_apsr_d(a, b, __aeabi_cdcmple); + int32_t r_cpsr_value = call_apsr_d(b, a, __aeabi_cdrcmple); + + if (cpsr_value != r_cpsr_value) { + printf("error: __aeabi_cdcmple(%f, %f) != __aeabi_cdrcmple(%f, %f)\n", a, b, b, a); + return 1; + } + + int expected_z, expected_c; + if (a < b) { + expected_z = 0; + expected_c = 0; + } else if (a == b) { + expected_z = 1; + expected_c = 1; + } else { + // a or b is NaN, or a > b + expected_z = 0; + expected_c = 1; + } + + union cpsr cpsr = { .value = cpsr_value }; + if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) { + printf("error in __aeabi_cdcmple(%f, %f) => (Z = %d, C = %d), expected (Z = %d, C = %d)\n", + a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c); + return 1; + } + return 0; +} +#endif + +int main() +{ +#if __arm__ + if (test__aeabi_cdcmple(1.0, 1.0)) + return 1; + if (test__aeabi_cdcmple(1234.567, 765.4321)) + return 1; + if (test__aeabi_cdcmple(765.4321, 1234.567)) + return 1; + if (test__aeabi_cdcmple(-123.0, -678.0)) + return 1; + if (test__aeabi_cdcmple(-678.0, -123.0)) + return 1; + if (test__aeabi_cdcmple(0.0, -0.0)) + return 1; + if (test__aeabi_cdcmple(1.0, NAN)) + return 1; + if (test__aeabi_cdcmple(NAN, 1.0)) + return 1; +#else + printf("skipped\n"); +#endif + return 0; +} Index: test/builtins/Unit/arm/aeabi_cfcmpeq_test.c =================================================================== --- /dev/null +++ test/builtins/Unit/arm/aeabi_cfcmpeq_test.c @@ -0,0 +1,74 @@ +//===-- aeabi_cfcmpeq.c - Test __aeabi_cfcmpeq ----------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is dual licensed under the MIT and the University of Illinois Open +// Source Licenses. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file tests __aeabi_cfcmpeq for the compiler_rt library. +// +//===----------------------------------------------------------------------===// + +#include +#include +#include +#include + +#if __arm__ +#include "call_apsr.h" + +extern __attribute__((pcs("aapcs"))) void __aeabi_cfcmpeq(float a, float b); + +union float_bits { + float f; + struct b { + uint32_t m: 23; + uint32_t e: 8; + uint32_t s: 1; + } b; +}; + +int test__aeabi_cfcmpeq(float a, float b, int expected) +{ + uint32_t cpsr_value = call_apsr_f(a, b, __aeabi_cfcmpeq); + union cpsr cpsr = { .value = cpsr_value }; + if (expected != cpsr.flags.z) { + printf("error in __aeabi_cfcmpeq(%f, %f) => Z = %d, expected %d\n", + a, b, cpsr.flags.z, expected); + return 0; + } + return 0; +} +#endif + +int main() +{ + float SNAN; + union float_bits fb; + fb.b.s = 0; + fb.b.e = 0xff; + fb.b.m = (1 << 22) + 1; + SNAN = fb.f; + +#if __arm__ + if (test__aeabi_cfcmpeq(1.0, 1.0, 1)) + return 1; + if (test__aeabi_cfcmpeq(1234.567, 765.4321, 0)) + return 1; + if (test__aeabi_cfcmpeq(-123.0, -678.0, 0)) + return 1; + if (test__aeabi_cfcmpeq(0.0, -0.0, 1)) + return 1; + if (test__aeabi_cfcmpeq(1.0, NAN, 0)) + return 1; + if (test__aeabi_cfcmpeq(NAN, 1.0, 0)) + return 1; + if (test__aeabi_cfcmpeq(SNAN, 1.0, 0)) + return 1; +#else + printf("skipped\n"); +#endif + return 0; +} Index: test/builtins/Unit/arm/aeabi_cfcmple_test.c =================================================================== --- /dev/null +++ test/builtins/Unit/arm/aeabi_cfcmple_test.c @@ -0,0 +1,83 @@ +//===-- aeabi_cfcmple.c - Test __aeabi_cfcmple and __aeabi_cfrcmple -------===// +// +// The LLVM Compiler Infrastructure +// +// This file is dual licensed under the MIT and the University of Illinois Open +// Source Licenses. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file tests __aeabi_cfcmple and __aeabi_cfrcmple for the compiler_rt +// library. +// +//===----------------------------------------------------------------------===// + +#include +#include +#include +#include + +#include "call_apsr.h" + +#if __arm__ + +extern __attribute__((pcs("aapcs"))) void __aeabi_cfcmple(float a, float b); +extern __attribute__((pcs("aapcs"))) void __aeabi_cfrcmple(float a, float b); + +int test__aeabi_cfcmple(float a, float b) +{ + int32_t cpsr_value = call_apsr_f(a, b, __aeabi_cfcmple); + int32_t r_cpsr_value = call_apsr_f(b, a, __aeabi_cfrcmple); + + if (cpsr_value != r_cpsr_value) { + printf("error: __aeabi_cfcmple(%f, %f) != __aeabi_cfrcmple(%f, %f)\n", a, b, b, a); + return 1; + } + + int expected_z, expected_c; + if (a < b) { + expected_z = 0; + expected_c = 0; + } else if (a == b) { + expected_z = 1; + expected_c = 1; + } else { + // a or b is NaN, or a > b + expected_z = 0; + expected_c = 1; + } + + union cpsr cpsr = { .value = cpsr_value }; + if (expected_z != cpsr.flags.z || expected_c != cpsr.flags.c) { + printf("error in __aeabi_cfcmple(%f, %f) => (Z = %d, C = %d), expected (Z = %d, C = %d)\n", + a, b, cpsr.flags.z, cpsr.flags.c, expected_z, expected_c); + return 1; + } + return 0; +} +#endif + +int main() +{ +#if __arm__ + if (test__aeabi_cfcmple(1.0, 1.0)) + return 1; + if (test__aeabi_cfcmple(1234.567, 765.4321)) + return 1; + if (test__aeabi_cfcmple(765.4321, 1234.567)) + return 1; + if (test__aeabi_cfcmple(-123.0, -678.0)) + return 1; + if (test__aeabi_cfcmple(-678.0, -123.0)) + return 1; + if (test__aeabi_cfcmple(0.0, -0.0)) + return 1; + if (test__aeabi_cfcmple(1.0, NAN)) + return 1; + if (test__aeabi_cfcmple(NAN, 1.0)) + return 1; +#else + printf("skipped\n"); +#endif + return 0; +} Index: test/builtins/Unit/arm/call_apsr.h =================================================================== --- /dev/null +++ test/builtins/Unit/arm/call_apsr.h @@ -0,0 +1,25 @@ +#ifndef CALL_APSR_H +#define CALL_APSR_H + +#ifndef __LITTLE_ENDIAN__ +#error FIXME +#endif + +union cpsr { + struct { + uint32_t filler: 28; + uint32_t v: 1; + uint32_t c: 1; + uint32_t z: 1; + uint32_t n: 1; + } flags; + uint32_t value; +}; + +extern __attribute__((pcs("aapcs"))) +uint32_t call_apsr_f(float a, float b, __attribute__((pcs("aapcs"))) void (*fn)(float, float)); + +extern __attribute__((pcs("aapcs"))) +uint32_t call_apsr_d(double a, double b, __attribute__((pcs("aapcs"))) void (*fn)(double, double)); + +#endif // CALL_APSR_H Index: test/builtins/Unit/arm/call_apsr.S =================================================================== --- /dev/null +++ test/builtins/Unit/arm/call_apsr.S @@ -0,0 +1,27 @@ +.syntax unified +// __attribute__((pcs("aapcs"))) int32_t call_apsr_d(double a, double b, void(*fn)(double, double)) { +// fn(a, b); +// return apsr; +// } + +.globl call_apsr_d +.type call_apsr_d,%function +call_apsr_d: + push {lr} + ldr ip, [sp, #4] + blx ip + mrs r0, apsr + pop {pc} + +// __attribute__((pcs("aapcs"))) int32_t call_apsr_f(float a, float b, void(*fn)(float, float)) { +// fn(a, b); +// return apsr; +// } + +.globl call_apsr_f +.type call_apsr_f,%function +call_apsr_f: + push {lr} + blx r2 + mrs r0, apsr + pop {pc}