Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -94,6 +94,8 @@
     // (We look for a CopyFromReg reading a virtual register that is used
     //  for the function live-in value of register Reg)
     SDValue Value = OutVals[I];
+    if (Value->getOpcode() == ISD::AssertZext)
+      Value = Value.getOperand(0);
     if (Value->getOpcode() != ISD::CopyFromReg)
       return false;
     Register ArgReg = cast<RegisterSDNode>(Value->getOperand(1))->getReg();
Index: llvm/test/CodeGen/AArch64/swiftself.ll
===================================================================
--- llvm/test/CodeGen/AArch64/swiftself.ll
+++ llvm/test/CodeGen/AArch64/swiftself.ll
@@ -51,10 +51,10 @@
 ; CHECK-LABEL: swiftself_tail:
 ; OPTAARCH64: b {{_?}}swiftself_param
 ; OPTAARCH64-NOT: ret
-; OPTARM64_32: bl {{_?}}swiftself_param
+; OPTARM64_32: b {{_?}}swiftself_param
 define i8* @swiftself_tail(i8* swiftself %addr0) {
   call void asm sideeffect "", "~{x20}"()
-  %res = tail call i8* @swiftself_param(i8* swiftself %addr0)
+  %res = musttail call i8* @swiftself_param(i8* swiftself %addr0)
   ret i8* %res
 }