Index: llvm/trunk/include/llvm/Target/TargetLowering.h =================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h +++ llvm/trunk/include/llvm/Target/TargetLowering.h @@ -226,7 +226,11 @@ /// Return true if integer divide is usually cheaper than a sequence of /// several shifts, adds, and multiplies for this target. - bool isIntDivCheap() const { return IntDivIsCheap; } + /// The definition of "cheaper" may depend on whether we're optimizing + /// for speed or for size. + virtual bool isIntDivCheap(EVT VT, bool OptSize) const { + return false; + } /// Return true if sqrt(x) is as cheap or cheaper than 1 / rsqrt(x) bool isFsqrtCheap() const { @@ -242,9 +246,6 @@ return BypassSlowDivWidths; } - /// Return true if pow2 sdiv is cheaper than a chain of sra/srl/add/sra. - bool isPow2SDivCheap() const { return Pow2SDivIsCheap; } - /// Return true if Flow Control is an expensive operation that should be /// avoided. bool isJumpExpensive() const { return JumpIsExpensive; } @@ -1252,11 +1253,6 @@ /// control. void setJumpIsExpensive(bool isExpensive = true); - /// Tells the code generator that integer divide is expensive, and if - /// possible, should be replaced by an alternate sequence of instructions not - /// containing an integer divide. - void setIntDivIsCheap(bool isCheap = true) { IntDivIsCheap = isCheap; } - /// Tells the code generator that fsqrt is cheap, and should not be replaced /// with an alternative sequence of instructions. void setFsqrtIsCheap(bool isCheap = true) { FsqrtIsCheap = isCheap; } @@ -1272,10 +1268,6 @@ BypassSlowDivWidths[SlowBitWidth] = FastBitWidth; } - /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a - /// signed divide by power of two; let the target handle it. - void setPow2SDivIsCheap(bool isCheap = true) { Pow2SDivIsCheap = isCheap; } - /// Add the specified register class as an available regclass for the /// specified value type. This indicates the selector can handle values of /// that class natively. @@ -1766,12 +1758,6 @@ /// combined with "shift" to BitExtract instructions. bool HasExtractBitsInsn; - /// Tells the code generator not to expand integer divides by constants into a - /// sequence of muls, adds, and shifts. This is a hack until a real cost - /// model is in place. If we ever optimize for size, this will be set to true - /// unconditionally. - bool IntDivIsCheap; - // Don't expand fsqrt with an approximation based on the inverse sqrt. bool FsqrtIsCheap; @@ -1781,10 +1767,6 @@ /// div/rem when the operands are positive and less than 256. DenseMap BypassSlowDivWidths; - /// Tells the code generator that it shouldn't generate sra/srl/add/sra for a - /// signed divide by power of two; let the target handle it. - bool Pow2SDivIsCheap; - /// Tells the code generator that it shouldn't generate extra flow control /// instructions and should attempt to combine flow control instructions via /// predication. Index: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp =================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -2176,6 +2176,7 @@ N0, N1); } + bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize(); // fold (sdiv X, pow2) -> simple ops after legalize // FIXME: We check for the exact bit here because the generic lowering gives // better results in that case. The target-specific lowering should learn how @@ -2184,9 +2185,8 @@ !cast(N)->Flags.hasExact() && (N1C->getAPIntValue().isPowerOf2() || (-N1C->getAPIntValue()).isPowerOf2())) { - // If dividing by powers of two is cheap, then don't perform the following - // fold. - if (TLI.isPow2SDivCheap()) + // If integer division is cheap, then don't perform the following fold. + if (TLI.isIntDivCheap(N->getValueType(0), MinSize)) return SDValue(); // Target-specific implementation of sdiv x, pow2. @@ -2226,7 +2226,7 @@ // If integer divide is expensive and we satisfy the requirements, emit an // alternate sequence. - if (N1C && !TLI.isIntDivCheap()) + if (N1C && !TLI.isIntDivCheap(N->getValueType(0), MinSize)) if (SDValue Op = BuildSDIV(N)) return Op; @@ -2280,8 +2280,10 @@ } } } + // fold (udiv x, c) -> alternate - if (N1C && !TLI.isIntDivCheap()) + bool MinSize = DAG.getMachineFunction().getFunction()->optForMinSize(); + if (N1C && !TLI.isIntDivCheap(N->getValueType(0), MinSize)) if (SDValue Op = BuildUDIV(N)) return Op; Index: llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp =================================================================== --- llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp +++ llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp @@ -758,9 +758,7 @@ SelectIsExpensive = false; HasMultipleConditionRegisters = false; HasExtractBitsInsn = false; - IntDivIsCheap = false; FsqrtIsCheap = false; - Pow2SDivIsCheap = false; JumpIsExpensive = JumpIsExpensiveOverride; PredictableSelectIsExpensive = false; MaskAndBranchFoldingIsLegal = false; Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ llvm/trunk/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -429,10 +429,6 @@ setSelectIsExpensive(false); PredictableSelectIsExpensive = false; - // There are no integer divide instructions, and these expand to a pretty - // large sequence of instructions. - setIntDivIsCheap(false); - setPow2SDivIsCheap(false); setFsqrtIsCheap(true); // FIXME: Need to really handle these. Index: llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp =================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp +++ llvm/trunk/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -69,10 +69,6 @@ computeRegisterProperties(STI.getRegisterInfo()); // Provide all sorts of operation actions - - // Division is expensive - setIntDivIsCheap(false); - setStackPointerRegisterToSaveRestore(MSP430::SP); setBooleanContents(ZeroOrOneBooleanContent); setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? Index: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp =================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp @@ -79,9 +79,6 @@ // Compute derived properties from the register classes computeRegisterProperties(Subtarget.getRegisterInfo()); - // Division is expensive - setIntDivIsCheap(false); - setStackPointerRegisterToSaveRestore(XCore::SP); setSchedulingPreference(Sched::Source);