diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -1602,8 +1602,9 @@
 
   unsigned OpIdx = Op - &UseMI->getOperand(0);
   const MCInstrDesc &InstDesc = UseMI->getDesc();
-  if (!TRI->isVectorSuperClass(
-          TRI->getRegClass(InstDesc.OpInfo[OpIdx].RegClass)))
+  const TargetRegisterClass *OpRC =
+      TII->getRegClass(InstDesc, OpIdx, TRI, *MI.getMF());
+  if (!OpRC || !TRI->isVectorSuperClass(OpRC))
     return false;
 
   const auto *NewDstRC = TRI->getEquivalentAGPRClass(MRI->getRegClass(Reg));
diff --git a/llvm/test/CodeGen/AMDGPU/skip-fold-regsequence.mir b/llvm/test/CodeGen/AMDGPU/skip-fold-regsequence.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/skip-fold-regsequence.mir
@@ -0,0 +1,51 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-machineinstrs -run-pass si-fold-operands -o - %s | FileCheck -check-prefix=GCN %s
+
+# Skip folding a REG_SEQUENCE to its user when the regclasses for the user operands can't be
+# fully determined from the instruction description.
+---
+name:            regsequence_with_regsequence_use_op
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $agpr0, $agpr1
+
+    ; GCN-LABEL: name: regsequence_with_regsequence_use_op
+    ; GCN: liveins: $agpr0, $agpr1
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $agpr0
+    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $agpr1
+    ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+    ; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
+    ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE killed [[REG_SEQUENCE]], %subreg.sub0_sub1, killed [[DEF]], %subreg.sub2
+    ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE1]]
+    %0:vgpr_32 = COPY $agpr0
+    %1:vgpr_32 = COPY $agpr1
+    %2:vreg_64_align2 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, %1:vgpr_32, %subreg.sub1
+    %3:vgpr_32 = IMPLICIT_DEF
+    %4:vreg_96_align2 = REG_SEQUENCE killed %2:vreg_64_align2, %subreg.sub0_sub1, killed %3:vgpr_32, %subreg.sub2
+    S_ENDPGM 0, implicit %4
+...
+---
+name:            insert_subreg_with_regsequence_use_op
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $agpr0, $agpr1
+
+    ; GCN-LABEL: name: insert_subreg_with_regsequence_use_op
+    ; GCN: liveins: $agpr0, $agpr1
+    ; GCN-NEXT: {{  $}}
+    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $agpr0
+    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $agpr1
+    ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
+    ; GCN-NEXT: S_NOP 0, implicit-def %3
+    ; GCN-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vreg_64_align2 = INSERT_SUBREG %3, [[REG_SEQUENCE]], %subreg.sub0_sub1
+    ; GCN-NEXT: S_ENDPGM 0, implicit [[INSERT_SUBREG]]
+    %0:vgpr_32 = COPY $agpr0
+    %1:vgpr_32 = COPY $agpr1
+    %2:vreg_64_align2 = REG_SEQUENCE %0:vgpr_32, %subreg.sub0, %1:vgpr_32, %subreg.sub1
+    S_NOP 0, implicit-def %3:vreg_64_align2
+    %4:vreg_64_align2 = INSERT_SUBREG %3, %2, %subreg.sub0_sub1
+    S_ENDPGM 0, implicit %4
+...