Index: llvm/include/llvm/CodeGen/SelectionDAG.h =================================================================== --- llvm/include/llvm/CodeGen/SelectionDAG.h +++ llvm/include/llvm/CodeGen/SelectionDAG.h @@ -280,7 +280,9 @@ DenseMap SDCallSiteDbgInfo; +#if LLVM_ENABLE_ABI_BREAKING_CHECKS uint16_t NextPersistentId = 0; +#endif public: /// Clients of various APIs that cause global effects on Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h =================================================================== --- llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -617,7 +617,9 @@ public: /// Unique and persistent id per SDNode in the DAG. /// Used for debug printing. +#if LLVM_ENABLE_ABI_BREAKING_CHECKS uint16_t PersistentId; +#endif //===--------------------------------------------------------------------===// // Accessors @@ -1220,7 +1222,9 @@ : SDNode(ISD::HANDLENODE, 0, DebugLoc(), getSDVTList(MVT::Other)) { // HandleSDNodes are never inserted into the DAG, so they won't be // auto-numbered. Use ID 65535 as a sentinel. +#if LLVM_ENABLE_ABI_BREAKING_CHECKS PersistentId = 0xffff; +#endif // Manually set up the operand list. This node type is special in that it's // always stack allocated and SelectionDAG does not manage its operands. Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp =================================================================== --- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1066,8 +1066,10 @@ /// verification and other common operations when a new node is allocated. void SelectionDAG::InsertNode(SDNode *N) { AllNodes.push_back(N); -#ifndef NDEBUG +#if LLVM_ENABLE_ABI_BREAKING_CHECKS N->PersistentId = NextPersistentId++; +#endif +#ifndef NDEBUG VerifySDNode(N); #endif for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next) @@ -1271,7 +1273,7 @@ AllNodes.remove(AllNodes.begin()); while (!AllNodes.empty()) DeallocateNode(&AllNodes.front()); -#ifndef NDEBUG +#if LLVM_ENABLE_ABI_BREAKING_CHECKS NextPersistentId = 0; #endif } Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp =================================================================== --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp @@ -504,10 +504,10 @@ static Printable PrintNodeId(const SDNode &Node) { return Printable([&Node](raw_ostream &OS) { -#ifndef NDEBUG +#if LLVM_ENABLE_ABI_BREAKING_CHECKS OS << 't' << Node.PersistentId; #else - OS << (const void*)&Node; + OS << (const void *)&Node; #endif }); } Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp =================================================================== --- llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp +++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp @@ -77,7 +77,7 @@ const SelectionDAG *Graph) { std::string R; raw_string_ostream OS(R); -#ifndef NDEBUG +#if LLVM_ENABLE_ABI_BREAKING_CHECKS OS << 't' << Node->PersistentId; #else OS << static_cast(Node); Index: llvm/test/CodeGen/AArch64/pow.75.ll =================================================================== --- llvm/test/CodeGen/AArch64/pow.75.ll +++ llvm/test/CodeGen/AArch64/pow.75.ll @@ -7,40 +7,38 @@ declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>) define float @pow_f32_three_fourth_fmf(float %x) nounwind { -; CHECK: Combining: {{.*}}: f32 = fpow ninf nsz afn [[X:t[0-9]+]], ConstantFP:f32<7.500000e-01> -; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f32 = fsqrt ninf nsz afn [[X]] -; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: f32 = fsqrt ninf nsz afn [[SQRT]] -; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: f32 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]] -; CHECK-NEXT: ... into: [[R]]: f32 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]] +; CHECK: Combining: {{.*}}: f32 = fpow ninf nsz afn [[X:(t[0-9]+)|(0x[0-9a-f]+)]], ConstantFP:f32<7.500000e-01> +; CHECK-NEXT: Creating new node: [[SQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fsqrt ninf nsz afn [[X]] +; CHECK-NEXT: Creating new node: [[SQRTSQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fsqrt ninf nsz afn [[SQRT]] +; CHECK-NEXT: Creating new node: [[R:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]] %r = call nsz ninf afn float @llvm.pow.f32(float %x, float 7.5e-01) ret float %r } define double @pow_f64_three_fourth_fmf(double %x) nounwind { ; CHECK: Combining: {{.*}}: f64 = fpow ninf nsz afn [[X:t[0-9]+]], ConstantFP:f64<7.500000e-01> -; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f64 = fsqrt ninf nsz afn [[X]] -; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: f64 = fsqrt ninf nsz afn [[SQRT]] -; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: f64 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]] -; CHECK-NEXT: ... into: [[R]]: f64 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]] +; CHECK: Combining: {{.*}}: f64 = fpow ninf nsz afn [[X:(t[0-9]+)|(0x[0-9a-f]+)]], ConstantFP:f64<7.500000e-01> +; CHECK-NEXT: Creating new node: [[SQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f64 = fsqrt ninf nsz afn [[X]] +; CHECK-NEXT: Creating new node: [[SQRTSQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f64 = fsqrt ninf nsz afn [[SQRT]] +; CHECK-NEXT: Creating new node: [[R:(t[0-9]+)|(0x[0-9a-f]+)]]: f64 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]] %r = call nsz ninf afn double @llvm.pow.f64(double %x, double 7.5e-01) ret double %r } define <4 x float> @pow_v4f32_three_fourth_fmf(<4 x float> %x) nounwind { -; CHECK: Combining: {{.*}}: v4f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], {{.*}} -; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: v4f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] -; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: v4f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] -; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: v4f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] -; CHECK-NEXT: ... into: [[R]]: v4f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] +; CHECK: Combining: {{.*}}: v4f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:(t[0-9]+)|(0x[0-9a-f]+)]], {{.*}} +; CHECK-NEXT: Creating new node: [[SQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: v4f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] +; CHECK-NEXT: Creating new node: [[SQRTSQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: v4f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] +; CHECK-NEXT: Creating new node: [[R:(t[0-9]+)|(0x[0-9a-f]+)]]: v4f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] %r = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> ) ret <4 x float> %r } define <2 x double> @pow_v2f64_three_fourth_fmf(<2 x double> %x) nounwind { -; CHECK: Combining: {{.*}}: v2f64 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], {{.*}} -; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: v2f64 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] -; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: v2f64 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] -; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: v2f64 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] +; CHECK: Combining: {{.*}}: v2f64 = fpow nnan ninf nsz arcp contract afn reassoc [[X:(t[0-9]+)|(0x[0-9a-f]+)]], {{.*}} +; CHECK-NEXT: Creating new node: [[SQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: v2f64 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] +; CHECK-NEXT: Creating new node: [[SQRTSQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: v2f64 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] +; CHECK-NEXT: Creating new node: [[R:(t[0-9]+)|(0x[0-9a-f]+)]]: v2f64 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] ; CHECK-NEXT: ... into: [[R]]: v2f64 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] %r = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> ) ret <2 x double> %r Index: llvm/test/CodeGen/AArch64/split-vector-insert.ll =================================================================== --- llvm/test/CodeGen/AArch64/split-vector-insert.ll +++ llvm/test/CodeGen/AArch64/split-vector-insert.ll @@ -9,10 +9,10 @@ declare @llvm.experimental.vector.insert.nxv2f64.v8f64(, <8 x double>, i64) define @test_nxv2i64_v8i64( %a, <8 x i64> %b) #0 { -; CHECK-LEGALIZATION: Legally typed node: [[T1:t[0-9]+]]: nxv2i64 = insert_subvector {{t[0-9]+}}, {{t[0-9]+}}, Constant:i64<0> -; CHECK-LEGALIZATION: Legally typed node: [[T2:t[0-9]+]]: nxv2i64 = insert_subvector [[T1]], {{t[0-9]+}}, Constant:i64<2> -; CHECK-LEGALIZATION: Legally typed node: [[T3:t[0-9]+]]: nxv2i64 = insert_subvector [[T2]], {{t[0-9]+}}, Constant:i64<4> -; CHECK-LEGALIZATION: Legally typed node: [[T4:t[0-9]+]]: nxv2i64 = insert_subvector [[T3]], {{t[0-9]+}}, Constant:i64<6> +; CHECK-LEGALIZATION: Legally typed node: [[T1:(t[0-9]+)|(0x[0-9a-f]+)]]: nxv2i64 = insert_subvector {{(t[0-9]+)|(0x[0-9a-f]+)}}, {{(t[0-9]+)|(0x[0-9a-f]+)}}, Constant:i64<0> +; CHECK-LEGALIZATION: Legally typed node: [[T2:(t[0-9]+)|(0x[0-9a-f]+)]]: nxv2i64 = insert_subvector [[T1]], {{(t[0-9]+)|(0x[0-9a-f]+)}}, Constant:i64<2> +; CHECK-LEGALIZATION: Legally typed node: [[T3:(t[0-9]+)|(0x[0-9a-f]+)]]: nxv2i64 = insert_subvector [[T2]], {{(t[0-9]+)|(0x[0-9a-f]+)}}, Constant:i64<4> +; CHECK-LEGALIZATION: Legally typed node: [[T4:(t[0-9]+)|(0x[0-9a-f]+)]]: nxv2i64 = insert_subvector [[T3]], {{(t[0-9]+)|(0x[0-9a-f]+)}}, Constant:i64<6> ; CHECK-LABEL: test_nxv2i64_v8i64: ; CHECK: // %bb.0: @@ -63,10 +63,10 @@ } define @test_nxv2f64_v8f64( %a, <8 x double> %b) #0 { -; CHECK-LEGALIZATION: Legally typed node: [[T1:t[0-9]+]]: nxv2f64 = insert_subvector {{t[0-9]+}}, {{t[0-9]+}}, Constant:i64<0> -; CHECK-LEGALIZATION: Legally typed node: [[T2:t[0-9]+]]: nxv2f64 = insert_subvector [[T1]], {{t[0-9]+}}, Constant:i64<2> -; CHECK-LEGALIZATION: Legally typed node: [[T3:t[0-9]+]]: nxv2f64 = insert_subvector [[T2]], {{t[0-9]+}}, Constant:i64<4> -; CHECK-LEGALIZATION: Legally typed node: [[T4:t[0-9]+]]: nxv2f64 = insert_subvector [[T3]], {{t[0-9]+}}, Constant:i64<6> +; CHECK-LEGALIZATION: Legally typed node: [[T1:(t[0-9]+)|(0x[0-9a-f]+)]]: nxv2f64 = insert_subvector {{(t[0-9]+)|(0x[0-9a-f]+)}}, {{(t[0-9]+)|(0x[0-9a-f]+)}}, Constant:i64<0> +; CHECK-LEGALIZATION: Legally typed node: [[T2:(t[0-9]+)|(0x[0-9a-f]+)]]: nxv2f64 = insert_subvector [[T1]], {{(t[0-9]+)|(0x[0-9a-f]+)}}, Constant:i64<2> +; CHECK-LEGALIZATION: Legally typed node: [[T3:(t[0-9]+)|(0x[0-9a-f]+)]]: nxv2f64 = insert_subvector [[T2]], {{(t[0-9]+)|(0x[0-9a-f]+)}}, Constant:i64<4> +; CHECK-LEGALIZATION: Legally typed node: [[T4:(t[0-9]+)|(0x[0-9a-f]+)]]: nxv2f64 = insert_subvector [[T3]], {{(t[0-9]+)|(0x[0-9a-f]+)}}, Constant:i64<6> ; CHECK-LABEL: test_nxv2f64_v8f64: ; CHECK: // %bb.0: Index: llvm/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll =================================================================== --- llvm/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll +++ llvm/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll @@ -5,15 +5,15 @@ ; This test check that when v4f64 gets broken down to two v2f64 it maintains ; the "nnan" flags. -; CHECK: Legalizing node: [[VFOUR:t.*]]: v4f64 = BUILD_VECTOR +; CHECK: Legalizing node: [[VFOUR:(t[0-9]+)|(0x[0-9a-f]+)]]: v4f64 = BUILD_VECTOR ; CHECK-NEXT: Analyzing result type: v4f64 ; CHECK-NEXT: Split node result: [[VFOUR]]: v4f64 = BUILD_VECTOR -; CHECK: Legalizing node: [[VTWOA:t.*]]: v2f64 = BUILD_VECTOR +; CHECK: Legalizing node: [[VTWOA:(t[0-9]+)|(0x[0-9a-f]+)]]: v2f64 = BUILD_VECTOR ; CHECK: Legally typed node: [[VTWOA]]: v2f64 = BUILD_VECTOR -; CHECK: Legalizing node: [[VTWOB:t.*]]: v2f64 = BUILD_VECTOR +; CHECK: Legalizing node: [[VTWOB:(t[0-9]+)|(0x[0-9a-f]+)]]: v2f64 = BUILD_VECTOR ; CHECK: Legally typed node: [[VTWOB]]: v2f64 = BUILD_VECTOR -; CHECK: Legalizing node: t34: v2f64 = fmaxnum nnan reassoc [[VTWOB]], [[VTWOA]] +; CHECK: Legalizing node: {{(t[0-9]+)|(0x[0-9a-f]+)}}: v2f64 = fmaxnum nnan reassoc [[VTWOB]], [[VTWOA]] target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-gnu" Index: llvm/test/CodeGen/ARM/pow.75.ll =================================================================== --- llvm/test/CodeGen/ARM/pow.75.ll +++ llvm/test/CodeGen/ARM/pow.75.ll @@ -8,63 +8,63 @@ declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>) define float @pow_f32_three_fourth_fmf(float %x) nounwind { -; CHECK: Combining: {{.*}}: f32 = fpow ninf nsz afn [[X:t[0-9]+]], ConstantFP:f32<7.500000e-01> -; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f32 = fsqrt ninf nsz afn [[X]] -; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: f32 = fsqrt ninf nsz afn [[SQRT]] -; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: f32 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]] +; CHECK: Combining: {{.*}}: f32 = fpow ninf nsz afn [[X:(t[0-9]+)|(0x[0-9a-f]+)]], ConstantFP:f32<7.500000e-01> +; CHECK-NEXT: Creating new node: [[SQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fsqrt ninf nsz afn [[X]] +; CHECK-NEXT: Creating new node: [[SQRTSQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fsqrt ninf nsz afn [[SQRT]] +; CHECK-NEXT: Creating new node: [[R:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]] ; CHECK-NEXT: ... into: [[R]]: f32 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]] %r = call nsz ninf afn float @llvm.pow.f32(float %x, float 7.5e-01) ret float %r } define double @pow_f64_three_fourth_fmf(double %x) nounwind { -; CHECK: Combining: {{.*}}: f64 = fpow ninf nsz afn t2, ConstantFP:f64<7.500000e-01> -; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f64 = fsqrt ninf nsz afn [[X]] -; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: f64 = fsqrt ninf nsz afn [[SQRT]] -; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: f64 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]] +; CHECK: Combining: {{.*}}: f64 = fpow ninf nsz afn {{(t[0-9]+)|(0x[0-9a-f]+)}}, ConstantFP:f64<7.500000e-01> +; CHECK-NEXT: Creating new node: [[SQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f64 = fsqrt ninf nsz afn [[X:(t[0-9]+)|(0x[0-9a-f]+)]] +; CHECK-NEXT: Creating new node: [[SQRTSQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f64 = fsqrt ninf nsz afn [[SQRT]] +; CHECK-NEXT: Creating new node: [[R:(t[0-9]+)|(0x[0-9a-f]+)]]: f64 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]] ; CHECK-NEXT: ... into: [[R]]: f64 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]] %r = call nsz ninf afn double @llvm.pow.f64(double %x, double 7.5e-01) ret double %r } define <4 x float> @pow_v4f32_three_fourth_fmf(<4 x float> %x) nounwind { -; CHECK: Combining: {{.*}}: v4f32 = BUILD_VECTOR [[FORTH:t[0-9]+]], [[THIRD:t[0-9]+]], [[SECOND:t[0-9]+]], [[FIRST:t[0-9]+]] -; CHECK: Combining: [[FIRST]]: f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], ConstantFP:f32<7.500000e-01> -; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] -; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] -; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] +; CHECK: Combining: {{.*}}: v4f32 = BUILD_VECTOR [[FORTH:(t[0-9]+)|(0x[0-9a-f]+)]], [[THIRD:(t[0-9]+)|(0x[0-9a-f]+)]], [[SECOND:(t[0-9]+)|(0x[0-9a-f]+)]], [[FIRST:(t[0-9]+)|(0x[0-9a-f]+)]] +; CHECK: Combining: [[FIRST]]: f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:(t[0-9]+)|(0x[0-9a-f]+)]], ConstantFP:f32<7.500000e-01> +; CHECK-NEXT: Creating new node: [[SQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] +; CHECK-NEXT: Creating new node: [[SQRTSQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] +; CHECK-NEXT: Creating new node: [[R:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] ; CHECK-NEXT: ... into: [[R]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] -; CHECK: Combining: [[SECOND]]: f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], ConstantFP:f32<7.500000e-01> -; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] -; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] -; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] +; CHECK: Combining: [[SECOND]]: f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:(t[0-9]+)|(0x[0-9a-f]+)]], ConstantFP:f32<7.500000e-01> +; CHECK-NEXT: Creating new node: [[SQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] +; CHECK-NEXT: Creating new node: [[SQRTSQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] +; CHECK-NEXT: Creating new node: [[R:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] ; CHECK-NEXT: ... into: [[R]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] -; CHECK: Combining: [[THIRD]]: f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], ConstantFP:f32<7.500000e-01> -; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] -; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] -; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] +; CHECK: Combining: [[THIRD]]: f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:(t[0-9]+)|(0x[0-9a-f]+)]], ConstantFP:f32<7.500000e-01> +; CHECK-NEXT: Creating new node: [[SQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] +; CHECK-NEXT: Creating new node: [[SQRTSQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] +; CHECK-NEXT: Creating new node: [[R:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] ; CHECK-NEXT: ... into: [[R]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] -; CHECK: Combining: [[FORTH]]: f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], ConstantFP:f32<7.500000e-01> -; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] -; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] -; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] +; CHECK: Combining: [[FORTH]]: f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:(t[0-9]+)|(0x[0-9a-f]+)]], ConstantFP:f32<7.500000e-01> +; CHECK-NEXT: Creating new node: [[SQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] +; CHECK-NEXT: Creating new node: [[SQRTSQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] +; CHECK-NEXT: Creating new node: [[R:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] ; CHECK-NEXT: ... into: [[R]]: f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] %r = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> ) ret <4 x float> %r } define <2 x double> @pow_v2f64_three_fourth_fmf(<2 x double> %x) nounwind { -; CHECK: Combining: {{.*}}: v2f64 = BUILD_VECTOR [[SECOND:t[0-9]+]], [[FIRST:t[0-9]+]] -; CHECK: Combining: [[FIRST]]: f64 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], ConstantFP:f64<7.500000e-01> -; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f64 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] -; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: f64 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] -; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: f64 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] -; CHECK-NEXT: ... into: [[R]]: f64 = fmul nnan ninf nsz arcp contract afn reassoc t16, t17 -; CHECK: Combining: [[SECOND]]: f64 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], ConstantFP:f64<7.500000e-01> -; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f64 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] -; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: f64 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] -; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: f64 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] -; CHECK-NEXT: ... into: [[R]]: f64 = fmul nnan ninf nsz arcp contract afn reassoc t19, t20 +; CHECK: Combining: {{.*}}: v2f64 = BUILD_VECTOR [[SECOND:(t[0-9]+)|(0x[0-9a-f]+)]], [[FIRST:(t[0-9]+)|(0x[0-9a-f]+)]] +; CHECK: Combining: [[FIRST]]: f64 = fpow nnan ninf nsz arcp contract afn reassoc [[X:(t[0-9]+)|(0x[0-9a-f]+)]], ConstantFP:f64<7.500000e-01> +; CHECK-NEXT: Creating new node: [[SQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f64 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] +; CHECK-NEXT: Creating new node: [[SQRTSQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f64 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] +; CHECK-NEXT: Creating new node: [[R:(t[0-9]+)|(0x[0-9a-f]+)]]: f64 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] +; CHECK-NEXT: ... into: [[R]]: f64 = fmul nnan ninf nsz arcp contract afn reassoc [[T16:(t[0-9]+)|(0x[0-9a-f]+)]], [[T17:(t[0-9]+)|(0x[0-9a-f]+)]] +; CHECK: Combining: [[SECOND]]: f64 = fpow nnan ninf nsz arcp contract afn reassoc [[X:(t[0-9]+)|(0x[0-9a-f]+)]], ConstantFP:f64<7.500000e-01> +; CHECK-NEXT: Creating new node: [[SQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f64 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] +; CHECK-NEXT: Creating new node: [[SQRTSQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f64 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] +; CHECK-NEXT: Creating new node: [[R:(t[0-9]+)|(0x[0-9a-f]+)]]: f64 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] +; CHECK-NEXT: ... into: [[R]]: f64 = fmul nnan ninf nsz arcp contract afn reassoc [[T19:(t[0-9]+)|(0x[0-9a-f]+)]], [[T20:(t[0-9]+)|(0x[0-9a-f]+)]] %r = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> ) ret <2 x double> %r } Index: llvm/test/CodeGen/X86/callbr-asm-bb-exports.ll =================================================================== --- llvm/test/CodeGen/X86/callbr-asm-bb-exports.ll +++ llvm/test/CodeGen/X86/callbr-asm-bb-exports.ll @@ -5,19 +5,21 @@ ; inlineasm_br. Not sure how to get a MachineIR change so this reads the debug ; output from SelectionDAG. -; CHECK: t0: ch = EntryToken -; CHECK-NEXT: t16: i64 = BlockAddress<@test, %fail> 0 -; CHECK-NEXT: t4: i32,ch = CopyFromReg t0, Register:i32 %3 -; CHECK-NEXT: t10: i32 = add t4, Constant:i32<1> -; CHECK-NEXT: t12: ch = CopyToReg t0, Register:i32 %0, t10 -; CHECK-NEXT: t6: i32,ch = CopyFromReg t0, Register:i32 %4 -; CHECK-NEXT: t13: i32 = add t6, Constant:i32<1> -; CHECK-NEXT: t15: ch = CopyToReg t0, Register:i32 %1, t13 -; CHECK-NEXT: t17: ch = TokenFactor t12, t15 -; CHECK-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %2 -; CHECK-NEXT: t8: i32 = add t2, Constant:i32<4> -; CHECK-NEXT: t22: ch,glue = CopyToReg t17, Register:i32 %5, t8 -; CHECK-NEXT: t30: ch,glue = inlineasm_br t22, TargetExternalSymbol:i64'xorl $0, $0; jmp ${1:l}', MDNode:ch, TargetConstant:i64<8>, TargetConstant:i32<2293769>, Register:i32 %5, TargetConstant:i64<13>, TargetBlockAddress:i64<@test, %fail> 0, TargetConstant:i32<12>, Register:i32 $df, TargetConstant:i32<12>, Register:i16 $fpsw, TargetConstant:i32<12>, Register:i32 $eflags, t22:1 +; CHECK: Initial selection DAG: %bb.0 'test:entry' +; CHECK-NEXT: SelectionDAG has 33 nodes: +; CHECK-NEXT: [[T00:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = EntryToken +; CHECK-NEXT: [[T16:(t[0-9]+)|(0x[0-9a-f]+)]]: i64 = BlockAddress<@test, %fail> 0 +; CHECK-NEXT: [[T04:(t[0-9]+)|(0x[0-9a-f]+)]]: i32,ch = CopyFromReg [[T00]], Register:i32 %3 +; CHECK-NEXT: [[T10:(t[0-9]+)|(0x[0-9a-f]+)]]: i32 = add [[T04]], Constant:i32<1> +; CHECK-NEXT: [[T12:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = CopyToReg [[T00]], Register:i32 %0, [[T10]] +; CHECK-NEXT: [[T06:(t[0-9]+)|(0x[0-9a-f]+)]]: i32,ch = CopyFromReg [[T00]], Register:i32 %4 +; CHECK-NEXT: [[T13:(t[0-9]+)|(0x[0-9a-f]+)]]: i32 = add [[T06]], Constant:i32<1> +; CHECK-NEXT: [[T15:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = CopyToReg [[T00]], Register:i32 %1, [[T13]] +; CHECK-NEXT: [[T17:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = TokenFactor [[T12]], [[T15]] +; CHECK-NEXT: [[T02:(t[0-9]+)|(0x[0-9a-f]+)]]: i32,ch = CopyFromReg [[T00]], Register:i32 %2 +; CHECK-NEXT: [[T08:(t[0-9]+)|(0x[0-9a-f]+)]]: i32 = add [[T02]], Constant:i32<4> +; CHECK-NEXT: [[T22:(t[0-9]+)|(0x[0-9a-f]+)]]: ch,glue = CopyToReg [[T17]], Register:i32 %5, [[T08]] +; CHECK-NEXT: [[T30:(t[0-9]+)|(0x[0-9a-f]+)]]: ch,glue = inlineasm_br [[T22]], TargetExternalSymbol:i64'xorl $0, $0; jmp ${1:l}', MDNode:ch, TargetConstant:i64<8>, TargetConstant:i32<2293769>, Register:i32 %5, TargetConstant:i64<13>, TargetBlockAddress:i64<@test, %fail> 0, TargetConstant:i32<12>, Register:i32 $df, TargetConstant:i32<12>, Register:i16 $fpsw, TargetConstant:i32<12>, Register:i32 $eflags, [[T22]]:1 define i32 @test(i32 %a, i32 %b, i32 %c) { entry: Index: llvm/test/CodeGen/X86/fmf-propagation.ll =================================================================== --- llvm/test/CodeGen/X86/fmf-propagation.ll +++ llvm/test/CodeGen/X86/fmf-propagation.ll @@ -5,14 +5,14 @@ ; CHECK-LABEL: Initial selection DAG: %bb.0 'fmf_transfer:' -; CHECK: t5: f32 = fadd nsz t2, t4 -; CHECK-NEXT: t6: f32 = fadd arcp t5, t4 -; CHECK-NEXT: t7: f32 = fadd nnan t6, t4 -; CHECK-NEXT: t8: f32 = fadd ninf t7, t4 -; CHECK-NEXT: t9: f32 = fadd contract t8, t4 -; CHECK-NEXT: t10: f32 = fadd afn t9, t4 -; CHECK-NEXT: t11: f32 = fadd reassoc t10, t4 -; CHECK-NEXT: t12: f32 = fadd nnan ninf nsz arcp contract afn reassoc t11, t4 +; CHECK: [[T05:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fadd nsz [[T02:(t[0-9]+)|(0x[0-9a-f]+)]], [[T04:(t[0-9]+)|(0x[0-9a-f]+)]] +; CHECK-NEXT: [[T06:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fadd arcp [[T05]], [[T04]] +; CHECK-NEXT: [[T07:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fadd nnan [[T06]], [[T04]] +; CHECK-NEXT: [[T08:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fadd ninf [[T07]], [[T04]] +; CHECK-NEXT: [[T09:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fadd contract [[T08]], [[T04]] +; CHECK-NEXT: [[T10:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fadd afn [[T09]], [[T04]] +; CHECK-NEXT: [[T11:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fadd reassoc [[T10]], [[T04]] +; CHECK-NEXT: [[T12:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fadd nnan ninf nsz arcp contract afn reassoc [[T11]], [[T04]] ; CHECK: Optimized lowered selection DAG: %bb.0 'fmf_transfer:' @@ -29,7 +29,7 @@ } ; CHECK-LABEL: Optimized type-legalized selection DAG: %bb.0 'fmf_setcc:' -; CHECK: t13: i8 = setcc nnan ninf nsz arcp contract afn reassoc t2, ConstantFP:f32<0.000000e+00>, setlt:ch +; CHECK: [[T13:(t[0-9]+)|(0x[0-9a-f]+)]]: i8 = setcc nnan ninf nsz arcp contract afn reassoc [[T02:(t[0-9]+)|(0x[0-9a-f]+)]], ConstantFP:f32<0.000000e+00>, setlt:ch define float @fmf_setcc(float %x, float %y) { %cmp = fcmp fast ult float %x, 0.0 @@ -38,7 +38,7 @@ } ; CHECK-LABEL: Initial selection DAG: %bb.0 'fmf_setcc_canon:' -; CHECK: t14: i8 = setcc nnan ninf nsz arcp contract afn reassoc t2, ConstantFP:f32<0.000000e+00>, setgt:ch +; CHECK: [[T14:(t[0-9]+)|(0x[0-9a-f]+)]]: i8 = setcc nnan ninf nsz arcp contract afn reassoc [[T02:(t[0-9]+)|(0x[0-9a-f]+)]], ConstantFP:f32<0.000000e+00>, setgt:ch define float @fmf_setcc_canon(float %x, float %y) { %cmp = fcmp fast ult float 0.0, %x %ret = select i1 %cmp, float %x, float %y @@ -54,8 +54,8 @@ ; CHECK: v16f32 = llvm.x86.avx512.vfmadd.ps.512 nsz TargetConstant:i64<{{.*}}> ; CHECK-LABEL: Legalized selection DAG: %bb.0 'fmf_target_intrinsic:' -; CHECK: v16f32 = fma ninf nsz t{{.*}} -; CHECK: v16f32 = fma nsz t{{.*}} +; CHECK: v16f32 = fma ninf nsz {{(t[0-9]+)|(0x[0-9a-f]+)}} +; CHECK: v16f32 = fma nsz {{(t[0-9]+)|(0x[0-9a-f]+)}} define <16 x float> @fmf_target_intrinsic(<16 x float> %a, <16 x float> %b, <16 x float> %c) nounwind { %t0 = tail call ninf nsz <16 x float> @llvm.x86.avx512.vfmadd.ps.512(<16 x float> %a, <16 x float> %b, <16 x float> %c, i32 4) Index: llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll =================================================================== --- llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll +++ llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll @@ -14,18 +14,18 @@ ; X86-NEXT: retq ; DBGDAG-LABEL: Optimized legalized selection DAG: %bb.0 'merge_store_partial_overlap_load:' -; DBGDAG: [[ENTRYTOKEN:t[0-9]+]]: ch = EntryToken -; DBGDAG-DAG: [[BASEPTR:t[0-9]+]]: i64,ch = CopyFromReg [[ENTRYTOKEN]], -; DBGDAG-DAG: [[ADDPTR:t[0-9]+]]: i64 = add {{(nuw )?}}[[BASEPTR]], Constant:i64<2> +; DBGDAG: [[ENTRYTOKEN:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = EntryToken +; DBGDAG-DAG: [[BASEPTR:(t[0-9]+)|(0x[0-9a-f]+)]]: i64,ch = CopyFromReg [[ENTRYTOKEN]], +; DBGDAG-DAG: [[ADDPTR:(t[0-9]+)|(0x[0-9a-f]+)]]: i64 = add {{(nuw )?}}[[BASEPTR]], Constant:i64<2> -; DBGDAG-DAG: [[LD2:t[0-9]+]]: i16,ch = load<(load (s16) from %ir.tmp81, align 1)> [[ENTRYTOKEN]], [[BASEPTR]], undef:i64 -; DBGDAG-DAG: [[LD1:t[0-9]+]]: i8,ch = load<(load (s8) from %ir.tmp12)> [[ENTRYTOKEN]], [[ADDPTR]], undef:i64 +; DBGDAG-DAG: [[LD2:(t[0-9]+)|(0x[0-9a-f]+)]]: i16,ch = load<(load (s16) from %ir.tmp81, align 1)> [[ENTRYTOKEN]], [[BASEPTR]], undef:i64 +; DBGDAG-DAG: [[LD1:(t[0-9]+)|(0x[0-9a-f]+)]]: i8,ch = load<(load (s8) from %ir.tmp12)> [[ENTRYTOKEN]], [[ADDPTR]], undef:i64 -; DBGDAG-DAG: [[ST1:t[0-9]+]]: ch = store<(store (s8) into %ir.tmp14)> [[ENTRYTOKEN]], [[LD1]], t{{[0-9]+}}, undef:i64 -; DBGDAG-DAG: [[LOADTOKEN:t[0-9]+]]: ch = TokenFactor [[LD2]]:1, [[LD1]]:1 -; DBGDAG-DAG: [[ST2:t[0-9]+]]: ch = store<(store (s16) into %ir.tmp10, align 1)> [[LOADTOKEN]], [[LD2]], t{{[0-9]+}}, undef:i64 +; DBGDAG-DAG: [[ST1:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = store<(store (s8) into %ir.tmp14)> [[ENTRYTOKEN]], [[LD1]], {{(t[0-9]+)|(0x[0-9a-f]+)}}, undef:i64 +; DBGDAG-DAG: [[LOADTOKEN:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = TokenFactor [[LD2]]:1, [[LD1]]:1 +; DBGDAG-DAG: [[ST2:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = store<(store (s16) into %ir.tmp10, align 1)> [[LOADTOKEN]], [[LD2]], {{(t[0-9]+)|(0x[0-9a-f]+)}}, undef:i64 -; DBGDAG: X86ISD::RET_FLAG t{{[0-9]+}}, +; DBGDAG: X86ISD::RET_FLAG {{(t[0-9]+)|(0x[0-9a-f]+)}}, ; DBGDAG-LABEL: Instruction selection begins define void @merge_store_partial_overlap_load([4 x i8]* %tmp) { Index: llvm/test/CodeGen/X86/pow.75.ll =================================================================== --- llvm/test/CodeGen/X86/pow.75.ll +++ llvm/test/CodeGen/X86/pow.75.ll @@ -7,40 +7,40 @@ declare <2 x double> @llvm.pow.v2f64(<2 x double>, <2 x double>) define float @pow_f32_three_fourth_fmf(float %x) nounwind { -; CHECK: Combining: {{.*}}: f32 = fpow ninf nsz afn [[X:t[0-9]+]], ConstantFP:f32<7.500000e-01> -; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f32 = fsqrt ninf nsz afn [[X]] -; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: f32 = fsqrt ninf nsz afn [[SQRT]] -; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: f32 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]] +; CHECK: Combining: {{.*}}: f32 = fpow ninf nsz afn [[X:(t[0-9]+)|(0x[0-9a-f]+)]], ConstantFP:f32<7.500000e-01> +; CHECK-NEXT: Creating new node: [[SQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fsqrt ninf nsz afn [[X]] +; CHECK-NEXT: Creating new node: [[SQRTSQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fsqrt ninf nsz afn [[SQRT]] +; CHECK-NEXT: Creating new node: [[R:(t[0-9]+)|(0x[0-9a-f]+)]]: f32 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]] ; CHECK-NEXT: ... into: [[R]]: f32 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]] %r = call nsz ninf afn float @llvm.pow.f32(float %x, float 7.5e-01) ret float %r } define double @pow_f64_three_fourth_fmf(double %x) nounwind { -; CHECK: Combining: {{.*}}: f64 = fpow ninf nsz afn [[X:t[0-9]+]], ConstantFP:f64<7.500000e-01> -; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: f64 = fsqrt ninf nsz afn [[X]] -; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: f64 = fsqrt ninf nsz afn [[SQRT]] -; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: f64 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]] +; CHECK: Combining: {{.*}}: f64 = fpow ninf nsz afn [[X:(t[0-9]+)|(0x[0-9a-f]+)]], ConstantFP:f64<7.500000e-01> +; CHECK-NEXT: Creating new node: [[SQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f64 = fsqrt ninf nsz afn [[X]] +; CHECK-NEXT: Creating new node: [[SQRTSQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: f64 = fsqrt ninf nsz afn [[SQRT]] +; CHECK-NEXT: Creating new node: [[R:(t[0-9]+)|(0x[0-9a-f]+)]]: f64 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]] ; CHECK-NEXT: ... into: [[R]]: f64 = fmul ninf nsz afn [[SQRT]], [[SQRTSQRT]] %r = call nsz ninf afn double @llvm.pow.f64(double %x, double 7.5e-01) ret double %r } define <4 x float> @pow_v4f32_three_fourth_fmf(<4 x float> %x) nounwind { -; CHECK: Combining: {{.*}}: v4f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], {{.*}} -; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: v4f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] -; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: v4f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] -; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: v4f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] +; CHECK: Combining: {{.*}}: v4f32 = fpow nnan ninf nsz arcp contract afn reassoc [[X:(t[0-9]+)|(0x[0-9a-f]+)]], {{.*}} +; CHECK-NEXT: Creating new node: [[SQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: v4f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] +; CHECK-NEXT: Creating new node: [[SQRTSQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: v4f32 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] +; CHECK-NEXT: Creating new node: [[R:(t[0-9]+)|(0x[0-9a-f]+)]]: v4f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] ; CHECK-NEXT: ... into: [[R]]: v4f32 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] %r = call fast <4 x float> @llvm.pow.v4f32(<4 x float> %x, <4 x float> ) ret <4 x float> %r } define <2 x double> @pow_v2f64_three_fourth_fmf(<2 x double> %x) nounwind { -; CHECK: Combining: {{.*}}: v2f64 = fpow nnan ninf nsz arcp contract afn reassoc [[X:t[0-9]+]], {{.*}} -; CHECK-NEXT: Creating new node: [[SQRT:t[0-9]+]]: v2f64 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] -; CHECK-NEXT: Creating new node: [[SQRTSQRT:t[0-9]+]]: v2f64 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] -; CHECK-NEXT: Creating new node: [[R:t[0-9]+]]: v2f64 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] +; CHECK: Combining: {{.*}}: v2f64 = fpow nnan ninf nsz arcp contract afn reassoc [[X:(t[0-9]+)|(0x[0-9a-f]+)]], {{.*}} +; CHECK-NEXT: Creating new node: [[SQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: v2f64 = fsqrt nnan ninf nsz arcp contract afn reassoc [[X]] +; CHECK-NEXT: Creating new node: [[SQRTSQRT:(t[0-9]+)|(0x[0-9a-f]+)]]: v2f64 = fsqrt nnan ninf nsz arcp contract afn reassoc [[SQRT]] +; CHECK-NEXT: Creating new node: [[R:(t[0-9]+)|(0x[0-9a-f]+)]]: v2f64 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] ; CHECK-NEXT: ... into: [[R]]: v2f64 = fmul nnan ninf nsz arcp contract afn reassoc [[SQRT]], [[SQRTSQRT]] %r = call fast <2 x double> @llvm.pow.v2f64(<2 x double> %x, <2 x double> ) ret <2 x double> %r Index: llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_isel.ll.expected =================================================================== --- llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_isel.ll.expected +++ llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/x86_isel.ll.expected @@ -5,20 +5,20 @@ define i64 @i64_test(i64 %i) nounwind readnone { ; PIC-LABEL: i64_test: ; PIC: SelectionDAG has 12 nodes: -; PIC-NEXT: t0: ch = EntryToken -; PIC-NEXT: t2: i64,ch = CopyFromReg t0, Register:i64 %0 -; PIC-NEXT: t7: i64,i32,ch = ADD64rm t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; PIC-NEXT: t10: ch,glue = CopyToReg t0, Register:i64 $rax, t7 -; PIC-NEXT: t11: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t10, t10:1 +; PIC-NEXT: [[T0:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = EntryToken +; PIC-NEXT: [[T1:(t[0-9]+)|(0x[0-9a-f]+)]]: i64,ch = CopyFromReg [[T0]], Register:i64 %0 +; PIC-NEXT: [[T2:(t[0-9]+)|(0x[0-9a-f]+)]]: i64,i32,ch = ADD64rm [[T1]], TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, [[T0]] +; PIC-NEXT: [[T3:(t[0-9]+)|(0x[0-9a-f]+)]]: ch,glue = CopyToReg [[T0]], Register:i64 $rax, [[T2]] +; PIC-NEXT: [[T4:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = RET TargetConstant:i32<0>, Register:i64 $rax, [[T3]], [[T3]]:1 ; PIC-EMPTY: ; ; WIN-LABEL: i64_test: ; WIN: SelectionDAG has 12 nodes: -; WIN-NEXT: t0: ch = EntryToken -; WIN-NEXT: t2: i64,ch = CopyFromReg t0, Register:i64 %0 -; WIN-NEXT: t7: i64,i32,ch = ADD64rm t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; WIN-NEXT: t10: ch,glue = CopyToReg t0, Register:i64 $rax, t7 -; WIN-NEXT: t11: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t10, t10:1 +; WIN-NEXT: [[T0:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = EntryToken +; WIN-NEXT: [[T1:(t[0-9]+)|(0x[0-9a-f]+)]]: i64,ch = CopyFromReg [[T0]], Register:i64 %0 +; WIN-NEXT: [[T2:(t[0-9]+)|(0x[0-9a-f]+)]]: i64,i32,ch = ADD64rm [[T1]], TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, [[T0]] +; WIN-NEXT: [[T3:(t[0-9]+)|(0x[0-9a-f]+)]]: ch,glue = CopyToReg [[T0]], Register:i64 $rax, [[T2]] +; WIN-NEXT: [[T4:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = RET TargetConstant:i32<0>, Register:i64 $rax, [[T3]], [[T3]]:1 ; WIN-EMPTY: %loc = alloca i64 %j = load i64, i64 * %loc @@ -29,22 +29,22 @@ define i64 @i32_test(i32 %i) nounwind readnone { ; PIC-LABEL: i32_test: ; PIC: SelectionDAG has 15 nodes: -; PIC-NEXT: t0: ch = EntryToken -; PIC-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0 -; PIC-NEXT: t7: i32,i32,ch = ADD32rm t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; PIC-NEXT: t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t7, TargetConstant:i32<6> -; PIC-NEXT: t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8 -; PIC-NEXT: t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1 +; PIC-NEXT: [[T0:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = EntryToken +; PIC-NEXT: [[T1:(t[0-9]+)|(0x[0-9a-f]+)]]: i32,ch = CopyFromReg [[T0]], Register:i32 %0 +; PIC-NEXT: [[T2:(t[0-9]+)|(0x[0-9a-f]+)]]: i32,i32,ch = ADD32rm [[T1]], TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, [[T0]] +; PIC-NEXT: [[T3:(t[0-9]+)|(0x[0-9a-f]+)]]: i64 = SUBREG_TO_REG TargetConstant:i64<0>, [[T2]], TargetConstant:i32<6> +; PIC-NEXT: [[T4:(t[0-9]+)|(0x[0-9a-f]+)]]: ch,glue = CopyToReg [[T0]], Register:i64 $rax, [[T3]] +; PIC-NEXT: [[T5:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = RET TargetConstant:i32<0>, Register:i64 $rax, [[T4]], [[T4]]:1 ; PIC-EMPTY: ; ; WIN-LABEL: i32_test: ; WIN: SelectionDAG has 15 nodes: -; WIN-NEXT: t0: ch = EntryToken -; WIN-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0 -; WIN-NEXT: t7: i32,i32,ch = ADD32rm t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; WIN-NEXT: t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t7, TargetConstant:i32<6> -; WIN-NEXT: t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8 -; WIN-NEXT: t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1 +; WIN-NEXT: [[T0:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = EntryToken +; WIN-NEXT: [[T1:(t[0-9]+)|(0x[0-9a-f]+)]]: i32,ch = CopyFromReg [[T0]], Register:i32 %0 +; WIN-NEXT: [[T2:(t[0-9]+)|(0x[0-9a-f]+)]]: i32,i32,ch = ADD32rm [[T1]], TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, [[T0]] +; WIN-NEXT: [[T3:(t[0-9]+)|(0x[0-9a-f]+)]]: i64 = SUBREG_TO_REG TargetConstant:i64<0>, [[T2]], TargetConstant:i32<6> +; WIN-NEXT: [[T4:(t[0-9]+)|(0x[0-9a-f]+)]]: ch,glue = CopyToReg [[T0]], Register:i64 $rax, [[T3]] +; WIN-NEXT: [[T5:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = RET TargetConstant:i32<0>, Register:i64 $rax, [[T4]], [[T4]]:1 ; WIN-EMPTY: %loc = alloca i32 %j = load i32, i32 * %loc @@ -56,25 +56,25 @@ define i64 @i16_test(i16 %i) nounwind readnone { ; PIC-LABEL: i16_test: ; PIC: SelectionDAG has 18 nodes: -; PIC-NEXT: t0: ch = EntryToken -; PIC-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0 -; PIC-NEXT: t3: i16 = EXTRACT_SUBREG t2, TargetConstant:i32<4> -; PIC-NEXT: t8: i16,i32,ch = ADD16rm t3, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; PIC-NEXT: t15: i32 = MOVZX32rr16 t8 -; PIC-NEXT: t9: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t15, TargetConstant:i32<6> -; PIC-NEXT: t12: ch,glue = CopyToReg t0, Register:i64 $rax, t9 -; PIC-NEXT: t13: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t12, t12:1 +; PIC-NEXT: [[T0:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = EntryToken +; PIC-NEXT: [[T1:(t[0-9]+)|(0x[0-9a-f]+)]]: i32,ch = CopyFromReg [[T0]], Register:i32 %0 +; PIC-NEXT: [[T2:(t[0-9]+)|(0x[0-9a-f]+)]]: i16 = EXTRACT_SUBREG [[T1]], TargetConstant:i32<4> +; PIC-NEXT: [[T3:(t[0-9]+)|(0x[0-9a-f]+)]]: i16,i32,ch = ADD16rm [[T2]], TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, [[T0]] +; PIC-NEXT: [[T4:(t[0-9]+)|(0x[0-9a-f]+)]]: i32 = MOVZX32rr16 [[T3]] +; PIC-NEXT: [[T5:(t[0-9]+)|(0x[0-9a-f]+)]]: i64 = SUBREG_TO_REG TargetConstant:i64<0>, [[T4]], TargetConstant:i32<6> +; PIC-NEXT: [[T6:(t[0-9]+)|(0x[0-9a-f]+)]]: ch,glue = CopyToReg [[T0]], Register:i64 $rax, [[T5]] +; PIC-NEXT: [[T7:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = RET TargetConstant:i32<0>, Register:i64 $rax, [[T6]], [[T6]]:1 ; PIC-EMPTY: ; ; WIN-LABEL: i16_test: ; WIN: SelectionDAG has 16 nodes: -; WIN-NEXT: t0: ch = EntryToken -; WIN-NEXT: t2: i16,ch = CopyFromReg t0, Register:i16 %0 -; WIN-NEXT: t7: i16,i32,ch = ADD16rm t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; WIN-NEXT: t14: i32 = MOVZX32rr16 t7 -; WIN-NEXT: t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t14, TargetConstant:i32<6> -; WIN-NEXT: t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8 -; WIN-NEXT: t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1 +; WIN-NEXT: [[T0:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = EntryToken +; WIN-NEXT: [[T1:(t[0-9]+)|(0x[0-9a-f]+)]]: i16,ch = CopyFromReg [[T0]], Register:i16 %0 +; WIN-NEXT: [[T2:(t[0-9]+)|(0x[0-9a-f]+)]]: i16,i32,ch = ADD16rm [[T1]], TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, [[T0]] +; WIN-NEXT: [[T3:(t[0-9]+)|(0x[0-9a-f]+)]]: i32 = MOVZX32rr16 [[T2]] +; WIN-NEXT: [[T4:(t[0-9]+)|(0x[0-9a-f]+)]]: i64 = SUBREG_TO_REG TargetConstant:i64<0>, [[T3]], TargetConstant:i32<6> +; WIN-NEXT: [[T5:(t[0-9]+)|(0x[0-9a-f]+)]]: ch,glue = CopyToReg [[T0]], Register:i64 $rax, [[T4]] +; WIN-NEXT: [[T6:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = RET TargetConstant:i32<0>, Register:i64 $rax, [[T5]], [[T5]]:1 ; WIN-EMPTY: %loc = alloca i16 %j = load i16, i16 * %loc @@ -86,25 +86,25 @@ define i64 @i8_test(i8 %i) nounwind readnone { ; PIC-LABEL: i8_test: ; PIC: SelectionDAG has 18 nodes: -; PIC-NEXT: t0: ch = EntryToken -; PIC-NEXT: t2: i32,ch = CopyFromReg t0, Register:i32 %0 -; PIC-NEXT: t3: i8 = EXTRACT_SUBREG t2, TargetConstant:i32<1> -; PIC-NEXT: t8: i8,i32,ch = ADD8rm t3, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; PIC-NEXT: t15: i32 = MOVZX32rr8 t8 -; PIC-NEXT: t9: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t15, TargetConstant:i32<6> -; PIC-NEXT: t12: ch,glue = CopyToReg t0, Register:i64 $rax, t9 -; PIC-NEXT: t13: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t12, t12:1 +; PIC-NEXT: [[T0:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = EntryToken +; PIC-NEXT: [[T1:(t[0-9]+)|(0x[0-9a-f]+)]]: i32,ch = CopyFromReg [[T0]], Register:i32 %0 +; PIC-NEXT: [[T2:(t[0-9]+)|(0x[0-9a-f]+)]]: i8 = EXTRACT_SUBREG [[T1]], TargetConstant:i32<1> +; PIC-NEXT: [[T3:(t[0-9]+)|(0x[0-9a-f]+)]]: i8,i32,ch = ADD8rm [[T2]], TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, [[T0]] +; PIC-NEXT: [[T4:(t[0-9]+)|(0x[0-9a-f]+)]]: i32 = MOVZX32rr8 [[T3]] +; PIC-NEXT: [[T5:(t[0-9]+)|(0x[0-9a-f]+)]]: i64 = SUBREG_TO_REG TargetConstant:i64<0>, [[T4]], TargetConstant:i32<6> +; PIC-NEXT: [[T6:(t[0-9]+)|(0x[0-9a-f]+)]]: ch,glue = CopyToReg [[T0]], Register:i64 $rax, [[T5]] +; PIC-NEXT: [[T7:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = RET TargetConstant:i32<0>, Register:i64 $rax, [[T6]], [[T6]]:1 ; PIC-EMPTY: ; ; WIN-LABEL: i8_test: ; WIN: SelectionDAG has 16 nodes: -; WIN-NEXT: t0: ch = EntryToken -; WIN-NEXT: t2: i8,ch = CopyFromReg t0, Register:i8 %0 -; WIN-NEXT: t7: i8,i32,ch = ADD8rm t2, TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, t0 -; WIN-NEXT: t14: i32 = MOVZX32rr8 t7 -; WIN-NEXT: t8: i64 = SUBREG_TO_REG TargetConstant:i64<0>, t14, TargetConstant:i32<6> -; WIN-NEXT: t11: ch,glue = CopyToReg t0, Register:i64 $rax, t8 -; WIN-NEXT: t12: ch = RET TargetConstant:i32<0>, Register:i64 $rax, t11, t11:1 +; WIN-NEXT: [[T0:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = EntryToken +; WIN-NEXT: [[T1:(t[0-9]+)|(0x[0-9a-f]+)]]: i8,ch = CopyFromReg [[T0]], Register:i8 %0 +; WIN-NEXT: [[T2:(t[0-9]+)|(0x[0-9a-f]+)]]: i8,i32,ch = ADD8rm [[T1]], TargetFrameIndex:i64<0>, TargetConstant:i8<1>, Register:i64 $noreg, TargetConstant:i32<0>, Register:i16 $noreg, [[T0]] +; WIN-NEXT: [[T3:(t[0-9]+)|(0x[0-9a-f]+)]]: i32 = MOVZX32rr8 [[T2]] +; WIN-NEXT: [[T4:(t[0-9]+)|(0x[0-9a-f]+)]]: i64 = SUBREG_TO_REG TargetConstant:i64<0>, [[T3]], TargetConstant:i32<6> +; WIN-NEXT: [[T5:(t[0-9]+)|(0x[0-9a-f]+)]]: ch,glue = CopyToReg [[T0]], Register:i64 $rax, [[T4]] +; WIN-NEXT: [[T6:(t[0-9]+)|(0x[0-9a-f]+)]]: ch = RET TargetConstant:i32<0>, Register:i64 $rax, [[T5]], [[T5]]:1 ; WIN-EMPTY: %loc = alloca i8 %j = load i8, i8 * %loc Index: llvm/utils/UpdateTestChecks/isel.py =================================================================== --- llvm/utils/UpdateTestChecks/isel.py +++ llvm/utils/UpdateTestChecks/isel.py @@ -20,6 +20,8 @@ r'Total[\s]*amount[\s]*of[\s]*phi[\s]*nodes[\s]*to[\s]*update:[\s]*[0-9]+', flags=(re.M | re.S)) +ISEL_SDNODE_ID_RE = re.compile(r'(t[0-9]+)|(0x[0-9a-f]+)') + def scrub_isel_default(isel, args): # Scrub runs of whitespace out of the iSel debug output, but leave the leading # whitespace in place. @@ -28,6 +30,32 @@ isel = string.expandtabs(isel, 2) # Strip trailing whitespace. isel = common.SCRUB_TRAILING_WHITESPACE_RE.sub(r'', isel) + + # Replace SDNode debug IDs with regexes in order to make tests + # treat both t and 0x as SDNode debug IDs. + lines = isel.split('\n') + isel_sdnode_id_to_filecheck_var = dict() + + # This gets called for each match that occurs in + # a line. We transform SDNode IDs we haven't seen + # into defs, and SDNode IDs we have seen into uses. + def transform_line_vars(match, isel_sdnode_id_to_filecheck_var=isel_sdnode_id_to_filecheck_var): + elem = match.group(0) + if elem in isel_sdnode_id_to_filecheck_var: + return '[[{}]]'.format(isel_sdnode_id_to_filecheck_var[elem]) + isel_sdnode_id_to_filecheck_var[elem] = 'T{}'.format(len(isel_sdnode_id_to_filecheck_var)) + return '[[{}:(t[0-9]+)|(0x[0-9a-f]+)]]'.format(isel_sdnode_id_to_filecheck_var[elem]) + + for i in range(len(lines)): + # It can happen that two matches are back-to-back and for some reason sub + # will not replace both of them. For now we work around this by + # substituting until there is no more match. + changed = True + while changed: + (lines[i], changed) = ISEL_SDNODE_ID_RE.subn(transform_line_vars, lines[i], count=1) + + isel = '\n'.join(lines) + return isel def get_run_handler(triple):