Index: lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h
===================================================================
--- lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h
+++ lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h
@@ -51,6 +51,9 @@
   void printGLC(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printSLC(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printTFE(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+  void printExpCompr(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+  void printExpVM(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+
   void printRegOperand(unsigned RegNo, raw_ostream &O);
   void printVOPDst(const MCInst *MI, unsigned OpNo, raw_ostream &O);
   void printImmediate32(uint32_t I, raw_ostream &O);
Index: lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
===================================================================
--- lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
+++ lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
@@ -127,6 +127,18 @@
     O << " tfe";
 }
 
+void AMDGPUInstPrinter::printExpCompr(const MCInst *MI, unsigned OpNo,
+                                      raw_ostream &O) {
+  if (MI->getOperand(OpNo).getImm())
+    O << " compr";
+}
+
+void AMDGPUInstPrinter::printExpVM(const MCInst *MI, unsigned OpNo,
+                                   raw_ostream &O) {
+  if (MI->getOperand(OpNo).getImm())
+    O << " vm";
+}
+
 void AMDGPUInstPrinter::printRegOperand(unsigned reg, raw_ostream &O,
                                         const MCRegisterInfo &MRI) {
   switch (reg) {
Index: lib/Target/AMDGPU/SIInstrInfo.td
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.td
+++ lib/Target/AMDGPU/SIInstrInfo.td
@@ -534,6 +534,14 @@
   let ParserMatchClass = SMRDLiteralOffsetMatchClass;
 }
 
+def exp_compr : Operand <i1> {
+  let PrintMethod = "printExpCompr";
+}
+
+def exp_vm : Operand <i1> {
+  let PrintMethod = "printExpVM";
+}
+
 } // End OperandType = "OPERAND_IMMEDIATE"
 
 def VOPDstS64 : VOPDstOperand <SReg_64>;
@@ -1873,9 +1881,9 @@
 
 class EXP_Helper<bit done, SDPatternOperator node = null_frag> : EXPCommon<
   (outs),
-  (ins i32imm:$en, i32imm:$tgt, i1imm:$compr, i1imm:$vm,
+  (ins i32imm:$en, i32imm:$tgt, exp_compr:$compr, exp_vm:$vm,
        VGPR_32:$src0, VGPR_32:$src1, VGPR_32:$src2, VGPR_32:$src3),
-  "exp $en, $tgt, $compr, "#!if(done, "1", "0")#", $vm, $src0, $src1, $src2, $src3",
+  "exp en:$en tgt:$tgt$compr$vm $src0, $src1, $src2, $src3"#!if(done, " done", ""),
   [(node (i32 timm:$en), (i1 timm:$vm), (i32 timm:$tgt), (i1 timm:$compr),
          f32:$src0, f32:$src1, f32:$src2, f32:$src3)]
 >;
Index: test/CodeGen/AMDGPU/llvm.SI.export.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/llvm.SI.export.ll
@@ -0,0 +1,69 @@
+; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN %s
+
+; This test just checks that the compiler doesn't crash.
+
+declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
+
+; GCN-LABEL: {{^}}test_export_zeroes:
+; GCN: v_mov_b32_e32 [[VREG0:v[0-9]+]], 0{{$}}
+; GCN: exp en:0 tgt:0 [[VREG0]], [[VREG0]], [[VREG0]], [[VREG0]]{{$}}
+; GCN: exp en:0 tgt:0 [[VREG0]], [[VREG0]], [[VREG0]], [[VREG0]] done{{$}}
+define void @test_export_zeroes(<32 x i8> addrspace(2)* inreg) #0 {
+  call void @llvm.SI.export(i32 0, i32 0, i32 0, i32 0, i32 0, float 0.0, float 0.0, float 0.0, float 0.0)
+  call void @llvm.SI.export(i32 0, i32 0, i32 1, i32 0, i32 0, float 0.0, float 0.0, float 0.0, float 0.0)
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_export_en:
+; GCN: v_mov_b32_e32 [[VREG0:v[0-9]+]]
+; GCN: exp en:12 tgt:0 [[VREG0]], [[VREG0]], [[VREG0]], [[VREG0]]{{$}}
+; GCN: exp en:13 tgt:0 [[VREG0]], [[VREG0]], [[VREG0]], [[VREG0]] done{{$}}
+define void @test_export_en(<32 x i8> addrspace(2)* inreg) #0 {
+  call void @llvm.SI.export(i32 12, i32 0, i32 0, i32 0, i32 0, float 0.0, float 0.0, float 0.0, float 0.0)
+  call void @llvm.SI.export(i32 13, i32 0, i32 1, i32 0, i32 0, float 0.0, float 0.0, float 0.0, float 0.0)
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_export_tgt:
+; GCN: v_mov_b32_e32 [[VREG0:v[0-9]+]]
+; GCN: exp en:0 tgt:7 [[VREG0]], [[VREG0]], [[VREG0]], [[VREG0]]{{$}}
+; GCN: exp en:0 tgt:11 [[VREG0]], [[VREG0]], [[VREG0]], [[VREG0]] done{{$}}
+define void @test_export_tgt(<32 x i8> addrspace(2)* inreg) #0 {
+  call void @llvm.SI.export(i32 0, i32 0, i32 0, i32 7, i32 0, float 0.0, float 0.0, float 0.0, float 0.0)
+  call void @llvm.SI.export(i32 0, i32 0, i32 1, i32 11, i32 0, float 0.0, float 0.0, float 0.0, float 0.0)
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_export_vm:
+; GCN: v_mov_b32_e32 [[VREG0:v[0-9]+]]
+; GCN: exp en:12 tgt:7 vm [[VREG0]], [[VREG0]], [[VREG0]], [[VREG0]]{{$}}
+; GCN: exp en:13 tgt:3 vm [[VREG0]], [[VREG0]], [[VREG0]], [[VREG0]] done{{$}}
+define void @test_export_vm(<32 x i8> addrspace(2)* inreg) #0 {
+  call void @llvm.SI.export(i32 12, i32 1, i32 0, i32 7, i32 0, float 0.0, float 0.0, float 0.0, float 0.0)
+  call void @llvm.SI.export(i32 13, i32 1, i32 1, i32 3, i32 0, float 0.0, float 0.0, float 0.0, float 0.0)
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_export_compr:
+; GCN: v_mov_b32_e32 [[VREG0:v[0-9]+]]
+; GCN: exp en:12 tgt:7 compr [[VREG0]], [[VREG0]], [[VREG0]], [[VREG0]]{{$}}
+; GCN: exp en:13 tgt:3 compr [[VREG0]], [[VREG0]], [[VREG0]], [[VREG0]] done{{$}}
+define void @test_export_compr(<32 x i8> addrspace(2)* inreg) #0 {
+  call void @llvm.SI.export(i32 12, i32 0, i32 0, i32 7, i32 1, float 0.0, float 0.0, float 0.0, float 0.0)
+  call void @llvm.SI.export(i32 13, i32 0, i32 1, i32 3, i32 1, float 0.0, float 0.0, float 0.0, float 0.0)
+  ret void
+}
+
+; GCN-LABEL: {{^}}test_export_vm_compr:
+; GCN: v_mov_b32_e32 [[VREG0:v[0-9]+]]
+; GCN: exp en:12 tgt:7 compr vm [[VREG0]], [[VREG0]], [[VREG0]], [[VREG0]]{{$}}
+; GCN: exp en:13 tgt:3 compr vm [[VREG0]], [[VREG0]], [[VREG0]], [[VREG0]] done{{$}}
+define void @test_export_vm_compr(<32 x i8> addrspace(2)* inreg) #0 {
+  call void @llvm.SI.export(i32 12, i32 1, i32 0, i32 7, i32 1, float 0.0, float 0.0, float 0.0, float 0.0)
+  call void @llvm.SI.export(i32 13, i32 1, i32 1, i32 3, i32 1, float 0.0, float 0.0, float 0.0, float 0.0)
+  ret void
+}
+
+
+attributes #0 = { "ShaderType"="0" }