diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp --- a/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp @@ -46,7 +46,7 @@ if (CommentStream) HasCustomInstComment = EmitAnyX86InstComments(MI, *CommentStream, MII); - printInstFlags(MI, OS); + printInstFlags(MI, OS, STI); // Output CALLpcrel32 as "callq" in 64-bit mode. // In Intel annotation it's always emitted as "call". diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h b/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h --- a/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h +++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.h @@ -33,7 +33,8 @@ raw_ostream &O); protected: - void printInstFlags(const MCInst *MI, raw_ostream &O); + void printInstFlags(const MCInst *MI, raw_ostream &O, + const MCSubtargetInfo &STI); void printOptionalSegReg(const MCInst *MI, unsigned OpNo, raw_ostream &O); void printVKPair(const MCInst *MI, unsigned OpNo, raw_ostream &OS); }; diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp --- a/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp @@ -18,10 +18,11 @@ #include "llvm/MC/MCInst.h" #include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCInstrInfo.h" -#include "llvm/Support/raw_ostream.h" +#include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/Casting.h" -#include +#include "llvm/Support/raw_ostream.h" #include +#include using namespace llvm; @@ -349,7 +350,8 @@ } } -void X86InstPrinterCommon::printInstFlags(const MCInst *MI, raw_ostream &O) { +void X86InstPrinterCommon::printInstFlags(const MCInst *MI, raw_ostream &O, + const MCSubtargetInfo &STI) { const MCInstrDesc &Desc = MII.get(MI->getOpcode()); uint64_t TSFlags = Desc.TSFlags; unsigned Flags = MI->getFlags(); @@ -379,6 +381,14 @@ O << "\t{disp8}"; else if (Flags & X86::IP_USE_DISP32) O << "\t{disp32}"; + + // Address-Size override prefix + if (Flags & X86::IP_HAS_AD_SIZE) { + if (STI.hasFeature(X86::Mode16Bit) || STI.hasFeature(X86::Mode64Bit)) + O << "\taddr32\t"; + else if (STI.hasFeature(X86::Mode32Bit)) + O << "\taddr16\t"; + } } void X86InstPrinterCommon::printVKPair(const MCInst *MI, unsigned OpNo, diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp --- a/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp @@ -40,7 +40,7 @@ void X86IntelInstPrinter::printInst(const MCInst *MI, uint64_t Address, StringRef Annot, const MCSubtargetInfo &STI, raw_ostream &OS) { - printInstFlags(MI, OS); + printInstFlags(MI, OS, STI); // In 16-bit mode, print data16 as data32. if (MI->getOpcode() == X86::DATA16_PREFIX && diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp --- a/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp +++ b/llvm/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp @@ -678,6 +678,8 @@ (STI.hasFeature(X86::Mode32Bit) && AdSize == X86II::AdSize16) || (STI.hasFeature(X86::Mode64Bit) && AdSize == X86II::AdSize32)) { NeedAddressOverride = true; + } else if (Flags & X86::IP_HAS_AD_SIZE) { + NeedAddressOverride = true; } else if (MemoryOperand < 0) { NeedAddressOverride = false; } else if (STI.hasFeature(X86::Mode64Bit)) { diff --git a/llvm/test/MC/Disassembler/X86/addr32.s b/llvm/test/MC/Disassembler/X86/addr32.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/addr32.s @@ -0,0 +1,5 @@ +# Check that we don't accidentally strip addr32 prefix + +# RUN: llvm-mc -disassemble %s -triple=x86_64 | FileCheck %s +# CHECK: addr32 callq +0x67 0xe8 0x00 0x00 0x00 0x00 diff --git a/llvm/test/MC/Disassembler/X86/prefixes.txt b/llvm/test/MC/Disassembler/X86/prefixes.txt --- a/llvm/test/MC/Disassembler/X86/prefixes.txt +++ b/llvm/test/MC/Disassembler/X86/prefixes.txt @@ -51,7 +51,7 @@ # CHECK: rep stosq %rax, %es:(%rdi) 0xf3 0x48 0xab -# CHECK: rep stosq %rax, %es:(%edi) +# CHECK: rep addr32 stosq %rax, %es:(%edi) 0xf3 0x67 0x48 0xab # CHECK: movl 32(%rbp), %eax diff --git a/llvm/test/MC/X86/addr16-32.s b/llvm/test/MC/X86/addr16-32.s --- a/llvm/test/MC/X86/addr16-32.s +++ b/llvm/test/MC/X86/addr16-32.s @@ -17,7 +17,7 @@ # CHECK: : # CHECK-NEXT: 6d insl %dx, %es:(%rdi) # CHECK-NEXT: 65 6f outsl %gs:(%rsi), %dx -# CHECK-NEXT: 67 6d insl %dx, %es:(%edi) -# CHECK-NEXT: 67 65 6f outsl %gs:(%esi), %dx -# CHECK-NEXT: 67 6d insl %dx, %es:(%edi) -# CHECK-NEXT: 67 65 6f outsl %gs:(%esi), %dx +# CHECK-NEXT: 67 6d addr32 insl %dx, %es:(%edi) +# CHECK-NEXT: 67 65 6f addr32 outsl %gs:(%esi), %dx +# CHECK-NEXT: 67 6d addr32 insl %dx, %es:(%edi) +# CHECK-NEXT: 67 65 6f addr32 outsl %gs:(%esi), %dx diff --git a/llvm/test/MC/X86/align-branch-hardcode.s b/llvm/test/MC/X86/align-branch-hardcode.s --- a/llvm/test/MC/X86/align-branch-hardcode.s +++ b/llvm/test/MC/X86/align-branch-hardcode.s @@ -17,7 +17,7 @@ int3 # CHECK: 5d: int3 - # CHECK: 5e: call + # CHECK: 5e: addr32 call # CHECK: 66: int3 .p2align 5 .rept 30 diff --git a/llvm/test/MC/X86/align-branch-prefix.s b/llvm/test/MC/X86/align-branch-prefix.s --- a/llvm/test/MC/X86/align-branch-prefix.s +++ b/llvm/test/MC/X86/align-branch-prefix.s @@ -28,7 +28,7 @@ int3 # CHECK: 9d: int3 - # CHECK: 9e: call + # CHECK: 9e: addr32 call # CHECK: a6: int3 .p2align 5 .rept 30 diff --git a/llvm/test/MC/X86/align-branch-system.s b/llvm/test/MC/X86/align-branch-system.s --- a/llvm/test/MC/X86/align-branch-system.s +++ b/llvm/test/MC/X86/align-branch-system.s @@ -43,7 +43,7 @@ movw %si, %ss jmp baz - # CHECK: 11b: movw (%esi), %ss + # CHECK: 11b: addr32 movw (%esi), %ss # CHECK: 11e: jmp .p2align 5 .rept 27 diff --git a/llvm/test/MC/X86/align-branch-variant-symbol.s b/llvm/test/MC/X86/align-branch-variant-symbol.s --- a/llvm/test/MC/X86/align-branch-variant-symbol.s +++ b/llvm/test/MC/X86/align-branch-variant-symbol.s @@ -25,7 +25,7 @@ int3 .endr # CHECK: 5d: int3 - # 64BIT: 5e: callq *(%ecx) + # 64BIT: 5e: addr32 callq *(%ecx) # 64BIT: 65: int3 # 32BIT: 5e: calll *(%ecx) # 32BIT: 64: int3 @@ -37,7 +37,7 @@ int3 .endr # CHECK: 9d: int3 - # 64BIT: 9e: callq *(%eax) + # 64BIT: 9e: addr32 callq *(%eax) # 64BIT: a1: int3 # 32BIT: 9e: calll *(%eax) # 32BIT: a0: int3 @@ -49,7 +49,7 @@ int3 .endr # CHECK: dd: int3 - # 64BIT: de: jmpq *(%eax) + # 64BIT: de: addr32 jmpq *(%eax) # 64BIT: e1: int3 # 32BIT: de: jmpl *(%eax) # 32BIT: e0: int3 diff --git a/llvm/test/MC/X86/code16-32-64.s b/llvm/test/MC/X86/code16-32-64.s --- a/llvm/test/MC/X86/code16-32-64.s +++ b/llvm/test/MC/X86/code16-32-64.s @@ -15,7 +15,7 @@ retq # CHECK: : -# CHECK-NEXT: 67 8b 00 movl (%eax), %eax +# CHECK-NEXT: 67 8b 00 addr32 movl (%eax), %eax # CHECK-NEXT: 8b 00 movl (%rax), %eax -# CHECK-NEXT: 67 66 8b 00 movw (%eax), %ax +# CHECK-NEXT: 67 66 8b 00 addr32 movw (%eax), %ax # CHECK-NEXT: c3 retq diff --git a/llvm/test/MC/X86/code16gcc-align.s b/llvm/test/MC/X86/code16gcc-align.s --- a/llvm/test/MC/X86/code16gcc-align.s +++ b/llvm/test/MC/X86/code16gcc-align.s @@ -10,7 +10,7 @@ # CHECK-NEXT: 25: 66 31 db xorl %ebx, %ebx # CHECK-NEXT: 28: 8d b4 00 00 leaw (%si), %si # CHECK-NEXT: 2c: 8d b4 00 00 leaw (%si), %si -# CHECK-NEXT: 30: 67 66 0f b6 0c 1e movzbl (%esi,%ebx), %ecx +# CHECK-NEXT: 30: 67 66 0f b6 0c 1e addr32 movzbl (%esi,%ebx), %ecx # CHECK-NEXT: 36: 66 e8 14 00 00 00 calll 0x50 # CHECK-NEXT: 3c: 8d 74 00 leaw (%si), %si diff --git a/llvm/test/MC/X86/tlsdesc-x32.s b/llvm/test/MC/X86/tlsdesc-x32.s --- a/llvm/test/MC/X86/tlsdesc-x32.s +++ b/llvm/test/MC/X86/tlsdesc-x32.s @@ -11,7 +11,7 @@ # CHECK: 0: 40 8d 05 00 00 00 00 leal (%rip), %eax # 0x7 <{{.*}}> # CHECK-NEXT: 00000003: R_X86_64_GOTPC32_TLSDESC a-0x4 -# CHECK-NEXT: 7: 67 ff 10 callq *(%eax) +# CHECK-NEXT: 7: 67 ff 10 addr32 callq *(%eax) # CHECK-NEXT: 00000007: R_X86_64_TLSDESC_CALL a # CHECK-NEXT: a: 8d 05 34 12 00 00 leal 4660(%rip), %eax # {{.*}}