[X86] Replace __m[128|256|512]bh with __m[128|256|512]i and mark the former deprecated

[pengfei]

Summary

As discussed on D120395, we should prohibit arithmetic operations for
m[128|256|512]bh as well. But them may be used for ABI type in future,
so replace them with m[128|256|512]i.

[andrew.w.kaylor]

Replacing __m128bh with __m128i does not prevent arithmetic operations on the type.

clang/lib/Headers/avx512bf16intrin.h

 /*===------------ avx512bf16intrin.h - AVX512_BF16 intrinsics --------------===
  *
  * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
  * See https://llvm.org/LICENSE.txt for license information.
  * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
  *
  *===-----------------------------------------------------------------------===
  */
 #ifndef __IMMINTRIN_H
 #error "Never use <avx512bf16intrin.h> directly; include <immintrin.h> instead."
 #endif
 
 #ifndef __AVX512BF16INTRIN_H
 #define __AVX512BF16INTRIN_H
 
-typedef short __m512bh __attribute__((__vector_size__(64), __aligned__(64)));
-typedef short __m256bh __attribute__((__vector_size__(32), __aligned__(32)));
+typedef short __m512bh __attribute__((__vector_size__(64), __aligned__(64),
+                                      deprecated("use __m512i instead")));
+typedef short __m256bh __attribute__((__vector_size__(32), __aligned__(32),
+                                      deprecated("use __m256i instead")));
 
 /// \typedef __bfloat16
 ///    A target specific type to represent the storage only brain floating-point
 ///    format type. Define through structure to explicitly prohibit any
 ///    arithmatic operations.
 typedef struct __bfloat16_s {
   short _Value;
 } __bfloat16;

 /// This intrinsic corresponds to the <c> VCVTNE2PS2BF16 </c> instructions.
 ///
 /// \param __A
 ///    A 512-bit vector of [16 x float].
 /// \param __B
 ///    A 512-bit vector of [16 x float].
 /// \returns A 512-bit vector of [32 x bfloat] whose lower 256 bits come from
 ///    conversion of __B, and higher 256 bits come from conversion of __A.
-static __inline__ __m512bh __DEFAULT_FN_ATTRS512
+static __inline__ __m512i __DEFAULT_FN_ATTRS512
 _mm512_cvtne2ps_pbh(__m512 __A, __m512 __B) {
-  return (__m512bh)__builtin_ia32_cvtne2ps2bf16_512((__v16sf) __A,
-                                                    (__v16sf) __B);
+  return (__m512i)__builtin_ia32_cvtne2ps2bf16_512((__v16sf) __A,
 }
 
 /// Convert Two Packed Single Data to One Packed BF16 Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VCVTNE2PS2BF16 </c> instructions.
 ///
 /// \param __A
 ///    A 512-bit vector of [16 x float].
 /// \param __B
 ///    A 512-bit vector of [16 x float].
 /// \param __W
 ///    A 512-bit vector of [32 x bfloat].
 /// \param __U
 ///    A 32-bit mask value specifying what is chosen for each element.
 ///    A 1 means conversion of __A or __B. A 0 means element from __W.
 /// \returns A 512-bit vector of [32 x bfloat] whose lower 256 bits come from
 ///    conversion of __B, and higher 256 bits come from conversion of __A.
-static __inline__ __m512bh __DEFAULT_FN_ATTRS512
-_mm512_mask_cvtne2ps_pbh(__m512bh __W, __mmask32 __U, __m512 __A, __m512 __B) {
-  return (__m512bh)__builtin_ia32_selectw_512((__mmask32)__U,
+static __inline__ __m512i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvtne2ps_pbh(__m512i __W, __mmask32 __U, __m512 __A, __m512 __B) {
+  return (__m512i)__builtin_ia32_selectw_512((__mmask32)__U,
                                         (__v32hi)_mm512_cvtne2ps_pbh(__A, __B),
                                         (__v32hi)__W);
 }
 
 /// Convert Two Packed Single Data to One Packed BF16 Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VCVTNE2PS2BF16 </c> instructions.
 ///
 /// \param __A
 ///    A 512-bit vector of [16 x float].
 /// \param __B
 ///    A 512-bit vector of [16 x float].
 /// \param __U
 ///    A 32-bit mask value specifying what is chosen for each element.
 ///    A 1 means conversion of __A or __B. A 0 means element is zero.
 /// \returns A 512-bit vector of [32 x bfloat] whose lower 256 bits come from
 ///    conversion of __B, and higher 256 bits come from conversion of __A.
-static __inline__ __m512bh __DEFAULT_FN_ATTRS512
+static __inline__ __m512i __DEFAULT_FN_ATTRS512
 _mm512_maskz_cvtne2ps_pbh(__mmask32 __U, __m512 __A, __m512 __B) {
-  return (__m512bh)__builtin_ia32_selectw_512((__mmask32)__U,
+  return (__m512i)__builtin_ia32_selectw_512((__mmask32)__U,
                                         (__v32hi)_mm512_cvtne2ps_pbh(__A, __B),
                                         (__v32hi)_mm512_setzero_si512());
 }
 
 /// Convert Packed Single Data to Packed BF16 Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
 ///
 /// \param __A
 ///    A 512-bit vector of [16 x float].
 /// \returns A 256-bit vector of [16 x bfloat] come from conversion of __A.
-static __inline__ __m256bh __DEFAULT_FN_ATTRS512
+static __inline__ __m256i __DEFAULT_FN_ATTRS512
 _mm512_cvtneps_pbh(__m512 __A) {
-  return (__m256bh)__builtin_ia32_cvtneps2bf16_512_mask((__v16sf)__A,
+  return (__m256i)__builtin_ia32_cvtneps2bf16_512_mask((__v16sf)__A,
                                               (__v16hi)_mm256_undefined_si256(),
                                               (__mmask16)-1);
 }
 
 /// Convert Packed Single Data to Packed BF16 Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
 ///
 /// \param __A
 ///    A 512-bit vector of [16 x float].
 /// \param __W
 ///    A 256-bit vector of [16 x bfloat].
 /// \param __U
 ///    A 16-bit mask value specifying what is chosen for each element.
 ///    A 1 means conversion of __A. A 0 means element from __W.
 /// \returns A 256-bit vector of [16 x bfloat] come from conversion of __A.
-static __inline__ __m256bh __DEFAULT_FN_ATTRS512
-_mm512_mask_cvtneps_pbh(__m256bh __W, __mmask16 __U, __m512 __A) {
-  return (__m256bh)__builtin_ia32_cvtneps2bf16_512_mask((__v16sf)__A,
-                                                        (__v16hi)__W,
-                                                        (__mmask16)__U);
+static __inline__ __m256i __DEFAULT_FN_ATTRS512
+_mm512_mask_cvtneps_pbh(__m256i __W, __mmask16 __U, __m512 __A) {
+  return (__m256i)__builtin_ia32_cvtneps2bf16_512_mask((__v16sf)__A,
 }
 
 /// Convert Packed Single Data to Packed BF16 Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
 ///
 /// \param __A
 ///    A 512-bit vector of [16 x float].
 /// \param __U
 ///    A 16-bit mask value specifying what is chosen for each element.
 ///    A 1 means conversion of __A. A 0 means element is zero.
 /// \returns A 256-bit vector of [16 x bfloat] come from conversion of __A.
-static __inline__ __m256bh __DEFAULT_FN_ATTRS512
+static __inline__ __m256i __DEFAULT_FN_ATTRS512
 _mm512_maskz_cvtneps_pbh(__mmask16 __U, __m512 __A) {
-  return (__m256bh)__builtin_ia32_cvtneps2bf16_512_mask((__v16sf)__A,
+  return (__m256i)__builtin_ia32_cvtneps2bf16_512_mask((__v16sf)__A,
                                                 (__v16hi)_mm256_setzero_si256(),
                                                 (__mmask16)__U);
 }
 
 /// Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VDPBF16PS </c> instructions.
 ///
 /// \param __A
 ///    A 512-bit vector of [32 x bfloat].
 /// \param __B
 ///    A 512-bit vector of [32 x bfloat].
 /// \param __D
 ///    A 512-bit vector of [16 x float].
 /// \returns A 512-bit vector of [16 x float] comes from  Dot Product of
 ///  __A, __B and __D
 static __inline__ __m512 __DEFAULT_FN_ATTRS512
-_mm512_dpbf16_ps(__m512 __D, __m512bh __A, __m512bh __B) {
+_mm512_dpbf16_ps(__m512 __D, __m512i __A, __m512i __B) {
   return (__m512)__builtin_ia32_dpbf16ps_512((__v16sf) __D,
                                              (__v16si) __A,
                                              (__v16si) __B);
 }
 
 /// Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VDPBF16PS </c> instructions.
 ///
 /// \param __A
 ///    A 512-bit vector of [32 x bfloat].
 /// \param __B
 ///    A 512-bit vector of [32 x bfloat].
 /// \param __D
 ///    A 512-bit vector of [16 x float].
 /// \param __U
 ///    A 16-bit mask value specifying what is chosen for each element.
 ///    A 1 means __A and __B's dot product accumulated with __D. A 0 means __D.
 /// \returns A 512-bit vector of [16 x float] comes from  Dot Product of
 ///  __A, __B and __D
 static __inline__ __m512 __DEFAULT_FN_ATTRS512
-_mm512_mask_dpbf16_ps(__m512 __D, __mmask16 __U, __m512bh __A, __m512bh __B) {
+_mm512_mask_dpbf16_ps(__m512 __D, __mmask16 __U, __m512i __A, __m512i __B) {
   return (__m512)__builtin_ia32_selectps_512((__mmask16)__U,
                                        (__v16sf)_mm512_dpbf16_ps(__D, __A, __B),
                                        (__v16sf)__D);
 }
 
 /// Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VDPBF16PS </c> instructions.
 ///
 /// \param __A
 ///    A 512-bit vector of [32 x bfloat].
 /// \param __B
 ///    A 512-bit vector of [32 x bfloat].
 /// \param __D
 ///    A 512-bit vector of [16 x float].
 /// \param __U
 ///    A 16-bit mask value specifying what is chosen for each element.
 ///    A 1 means __A and __B's dot product accumulated with __D. A 0 means 0.
 /// \returns A 512-bit vector of [16 x float] comes from  Dot Product of
 ///  __A, __B and __D
 static __inline__ __m512 __DEFAULT_FN_ATTRS512
-_mm512_maskz_dpbf16_ps(__mmask16 __U, __m512 __D, __m512bh __A, __m512bh __B) {
+_mm512_maskz_dpbf16_ps(__mmask16 __U, __m512 __D, __m512i __A, __m512i __B) {
   return (__m512)__builtin_ia32_selectps_512((__mmask16)__U,
                                        (__v16sf)_mm512_dpbf16_ps(__D, __A, __B),
                                        (__v16sf)_mm512_setzero_si512());
 }
 
 /// Convert Packed BF16 Data to Packed float Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// \param __A
 ///    A 256-bit vector of [16 x bfloat].
 /// \returns A 512-bit vector of [16 x float] come from conversion of __A
-static __inline__ __m512 __DEFAULT_FN_ATTRS512 _mm512_cvtpbh_ps(__m256bh __A) {
+static __inline__ __m512 __DEFAULT_FN_ATTRS512 _mm512_cvtpbh_ps(__m256i __A) {
   return _mm512_castsi512_ps((__m512i)_mm512_slli_epi32(
       (__m512i)_mm512_cvtepi16_epi32((__m256i)__A), 16));
 }
 
 /// Convert Packed BF16 Data to Packed float Data using zeroing mask.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// \param __U
 ///    A 16-bit mask. Elements are zeroed out when the corresponding mask
 ///    bit is not set.
 /// \param __A
 ///    A 256-bit vector of [16 x bfloat].
 /// \returns A 512-bit vector of [16 x float] come from conversion of __A
 static __inline__ __m512 __DEFAULT_FN_ATTRS512
-_mm512_maskz_cvtpbh_ps(__mmask16 __U, __m256bh __A) {
+_mm512_maskz_cvtpbh_ps(__mmask16 __U, __m256i __A) {
   return _mm512_castsi512_ps((__m512i)_mm512_slli_epi32(
       (__m512i)_mm512_maskz_cvtepi16_epi32((__mmask16)__U, (__m256i)__A), 16));
 }
 
 /// Convert Packed BF16 Data to Packed float Data using merging mask.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// \param __S
 ///    A 512-bit vector of [16 x float]. Elements are copied from __S when
 ///     the corresponding mask bit is not set.
 /// \param __U
 ///    A 16-bit mask.
 /// \param __A
 ///    A 256-bit vector of [16 x bfloat].
 /// \returns A 512-bit vector of [16 x float] come from conversion of __A
 static __inline__ __m512 __DEFAULT_FN_ATTRS512
-_mm512_mask_cvtpbh_ps(__m512 __S, __mmask16 __U, __m256bh __A) {
+_mm512_mask_cvtpbh_ps(__m512 __S, __mmask16 __U, __m256i __A) {
   return _mm512_castsi512_ps((__m512i)_mm512_mask_slli_epi32(
       (__m512i)__S, (__mmask16)__U,
       (__m512i)_mm512_cvtepi16_epi32((__m256i)__A), 16));
 }
 
 #undef __DEFAULT_FN_ATTRS
 #undef __DEFAULT_FN_ATTRS512
 
 #endif

clang/lib/Headers/avx512vlbf16intrin.h

 /*===--------- avx512vlbf16intrin.h - AVX512_BF16 intrinsics ---------------===
  *
  * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
  * See https://llvm.org/LICENSE.txt for license information.
  * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
  *
  *===-----------------------------------------------------------------------===
  */
 #ifndef __IMMINTRIN_H
 #error "Never use <avx512vlbf16intrin.h> directly; include <immintrin.h> instead."
 #endif
 
 #ifndef __AVX512VLBF16INTRIN_H
 #define __AVX512VLBF16INTRIN_H
 
-typedef short __m128bh __attribute__((__vector_size__(16), __aligned__(16)));
+typedef short __m128bh __attribute__((__vector_size__(16), __aligned__(16),
+                                      deprecated("use __m128i instead")));
 
 #define __DEFAULT_FN_ATTRS128 \
   __attribute__((__always_inline__, __nodebug__, \
                  __target__("avx512vl, avx512bf16"), __min_vector_width__(128)))
 #define __DEFAULT_FN_ATTRS256 \
   __attribute__((__always_inline__, __nodebug__, \
                  __target__("avx512vl, avx512bf16"), __min_vector_width__(256)))
 
 /// Convert Two Packed Single Data to One Packed BF16 Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VCVTNE2PS2BF16 </c> instructions.
 ///
 /// \param __A
 ///    A 128-bit vector of [4 x float].
 /// \param __B
 ///    A 128-bit vector of [4 x float].
 /// \returns A 128-bit vector of [8 x bfloat] whose lower 64 bits come from
 ///    conversion of __B, and higher 64 bits come from conversion of __A.
-static __inline__ __m128bh __DEFAULT_FN_ATTRS128
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
 _mm_cvtne2ps_pbh(__m128 __A, __m128 __B) {
-  return (__m128bh)__builtin_ia32_cvtne2ps2bf16_128((__v4sf) __A,
-                                                    (__v4sf) __B);
+  return (__m128i)__builtin_ia32_cvtne2ps2bf16_128((__v4sf) __A,
 }
 
 /// Convert Two Packed Single Data to One Packed BF16 Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VCVTNE2PS2BF16 </c> instructions.
 ///
 /// \param __A
 ///    A 128-bit vector of [4 x float].
 /// \param __B
 ///    A 128-bit vector of [4 x float].
 /// \param __W
 ///    A 128-bit vector of [8 x bfloat].
 /// \param __U
 ///    A 8-bit mask value specifying what is chosen for each element.
 ///    A 1 means conversion of __A or __B. A 0 means element from __W.
 /// \returns A 128-bit vector of [8 x bfloat] whose lower 64 bits come from
 ///    conversion of __B, and higher 64 bits come from conversion of __A.
-static __inline__ __m128bh __DEFAULT_FN_ATTRS128
-_mm_mask_cvtne2ps_pbh(__m128bh __W, __mmask8 __U, __m128 __A, __m128 __B) {
-  return (__m128bh)__builtin_ia32_selectw_128((__mmask8)__U,
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_mask_cvtne2ps_pbh(__m128i __W, __mmask8 __U, __m128 __A, __m128 __B) {
+  return (__m128i)__builtin_ia32_selectw_128((__mmask8)__U,
                                              (__v8hi)_mm_cvtne2ps_pbh(__A, __B),
                                              (__v8hi)__W);
 }
 
 /// Convert Two Packed Single Data to One Packed BF16 Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VCVTNE2PS2BF16 </c> instructions.
 ///
 /// \param __A
 ///    A 128-bit vector of [4 x float].
 /// \param __B
 ///    A 128-bit vector of [4 x float].
 /// \param __U
 ///    A 8-bit mask value specifying what is chosen for each element.
 ///    A 1 means conversion of __A or __B. A 0 means element is zero.
 /// \returns A 128-bit vector of [8 x bfloat] whose lower 64 bits come from
 ///    conversion of __B, and higher 64 bits come from conversion of __A.
-static __inline__ __m128bh __DEFAULT_FN_ATTRS128
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
 _mm_maskz_cvtne2ps_pbh(__mmask8 __U, __m128 __A, __m128 __B) {
-  return (__m128bh)__builtin_ia32_selectw_128((__mmask8)__U,
+  return (__m128i)__builtin_ia32_selectw_128((__mmask8)__U,
                                              (__v8hi)_mm_cvtne2ps_pbh(__A, __B),
                                              (__v8hi)_mm_setzero_si128());
 }
 
 /// Convert Two Packed Single Data to One Packed BF16 Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VCVTNE2PS2BF16 </c> instructions.
 ///
 /// \param __A
 ///    A 256-bit vector of [8 x float].
 /// \param __B
 ///    A 256-bit vector of [8 x float].
 /// \returns A 256-bit vector of [16 x bfloat] whose lower 128 bits come from
 ///    conversion of __B, and higher 128 bits come from conversion of __A.
-static __inline__ __m256bh __DEFAULT_FN_ATTRS256
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
 _mm256_cvtne2ps_pbh(__m256 __A, __m256 __B) {
-  return (__m256bh)__builtin_ia32_cvtne2ps2bf16_256((__v8sf) __A,
-                                                    (__v8sf) __B);
+  return (__m256i)__builtin_ia32_cvtne2ps2bf16_256((__v8sf) __A,
 }
 
 /// Convert Two Packed Single Data to One Packed BF16 Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VCVTNE2PS2BF16 </c> instructions.
 ///
 /// \param __A
 ///    A 256-bit vector of [8 x float].
 /// \param __B
 ///    A 256-bit vector of [8 x float].
 /// \param __W
 ///    A 256-bit vector of [16 x bfloat].
 /// \param __U
 ///    A 16-bit mask value specifying what is chosen for each element.
 ///    A 1 means conversion of __A or __B. A 0 means element from __W.
 /// \returns A 256-bit vector of [16 x bfloat] whose lower 128 bits come from
 ///    conversion of __B, and higher 128 bits come from conversion of __A.
-static __inline__ __m256bh __DEFAULT_FN_ATTRS256
-_mm256_mask_cvtne2ps_pbh(__m256bh __W, __mmask16 __U, __m256 __A, __m256 __B) {
-  return (__m256bh)__builtin_ia32_selectw_256((__mmask16)__U,
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
+_mm256_mask_cvtne2ps_pbh(__m256i __W, __mmask16 __U, __m256 __A, __m256 __B) {
+  return (__m256i)__builtin_ia32_selectw_256((__mmask16)__U,
                                          (__v16hi)_mm256_cvtne2ps_pbh(__A, __B),
                                          (__v16hi)__W);
 }
 
 /// Convert Two Packed Single Data to One Packed BF16 Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VCVTNE2PS2BF16 </c> instructions.
 ///
 /// \param __A
 ///    A 256-bit vector of [8 x float].
 /// \param __B
 ///    A 256-bit vector of [8 x float].
 /// \param __U
 ///    A 16-bit mask value specifying what is chosen for each element.
 ///    A 1 means conversion of __A or __B. A 0 means element is zero.
 /// \returns A 256-bit vector of [16 x bfloat] whose lower 128 bits come from
 ///    conversion of __B, and higher 128 bits come from conversion of __A.
-static __inline__ __m256bh __DEFAULT_FN_ATTRS256
+static __inline__ __m256i __DEFAULT_FN_ATTRS256
 _mm256_maskz_cvtne2ps_pbh(__mmask16 __U, __m256 __A, __m256 __B) {
-  return (__m256bh)__builtin_ia32_selectw_256((__mmask16)__U,
+  return (__m256i)__builtin_ia32_selectw_256((__mmask16)__U,
                                          (__v16hi)_mm256_cvtne2ps_pbh(__A, __B),
                                          (__v16hi)_mm256_setzero_si256());
 }
 
 /// Convert Packed Single Data to Packed BF16 Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
 ///
 /// \param __A
 ///    A 128-bit vector of [4 x float].
 /// \returns A 128-bit vector of [8 x bfloat] whose lower 64 bits come from
 ///    conversion of __A, and higher 64 bits are 0.
-static __inline__ __m128bh __DEFAULT_FN_ATTRS128
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
 _mm_cvtneps_pbh(__m128 __A) {
-  return (__m128bh)__builtin_ia32_cvtneps2bf16_128_mask((__v4sf) __A,
+  return (__m128i)__builtin_ia32_cvtneps2bf16_128_mask((__v4sf) __A,
                                                   (__v8hi)_mm_undefined_si128(),
                                                   (__mmask8)-1);
 }
 
 /// Convert Packed Single Data to Packed BF16 Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
 ///
 /// \param __A
 ///    A 128-bit vector of [4 x float].
 /// \param __W
 ///    A 128-bit vector of [8 x bfloat].
 /// \param __U
 ///    A 4-bit mask value specifying what is chosen for each element.
 ///    A 1 means conversion of __A. A 0 means element from __W.
 /// \returns A 128-bit vector of [8 x bfloat] whose lower 64 bits come from
 ///    conversion of __A, and higher 64 bits are 0.
-static __inline__ __m128bh __DEFAULT_FN_ATTRS128
-_mm_mask_cvtneps_pbh(__m128bh __W, __mmask8 __U, __m128 __A) {
-  return (__m128bh)__builtin_ia32_cvtneps2bf16_128_mask((__v4sf) __A,
-                                                        (__v8hi)__W,
-                                                        (__mmask8)__U);
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
+_mm_mask_cvtneps_pbh(__m128i __W, __mmask8 __U, __m128 __A) {
+  return (__m128i)__builtin_ia32_cvtneps2bf16_128_mask((__v4sf) __A,
 }
 
 /// Convert Packed Single Data to Packed BF16 Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
 ///
 /// \param __A
 ///    A 128-bit vector of [4 x float].
 /// \param __U
 ///    A 4-bit mask value specifying what is chosen for each element.
 ///    A 1 means conversion of __A. A 0 means element is zero.
 /// \returns A 128-bit vector of [8 x bfloat] whose lower 64 bits come from
 ///    conversion of __A, and higher 64 bits are 0.
-static __inline__ __m128bh __DEFAULT_FN_ATTRS128
+static __inline__ __m128i __DEFAULT_FN_ATTRS128
 _mm_maskz_cvtneps_pbh(__mmask8 __U, __m128 __A) {
-  return (__m128bh)__builtin_ia32_cvtneps2bf16_128_mask((__v4sf) __A,
+  return (__m128i)__builtin_ia32_cvtneps2bf16_128_mask((__v4sf) __A,
                                                     (__v8hi)_mm_setzero_si128(),
                                                     (__mmask8)__U);
 }
 
 /// Convert Packed Single Data to Packed BF16 Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
 ///
 /// \param __A
 ///    A 256-bit vector of [8 x float].
 /// \returns A 128-bit vector of [8 x bfloat] comes from conversion of __A.
-static __inline__ __m128bh __DEFAULT_FN_ATTRS256
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
 _mm256_cvtneps_pbh(__m256 __A) {
-  return (__m128bh)__builtin_ia32_cvtneps2bf16_256_mask((__v8sf)__A,
+  return (__m128i)__builtin_ia32_cvtneps2bf16_256_mask((__v8sf)__A,
                                                   (__v8hi)_mm_undefined_si128(),
                                                   (__mmask8)-1);
 }
 
 /// Convert Packed Single Data to Packed BF16 Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
 ///
 /// \param __A
 ///    A 256-bit vector of [8 x float].
 /// \param __W
 ///    A 256-bit vector of [8 x bfloat].
 /// \param __U
 ///    A 8-bit mask value specifying what is chosen for each element.
 ///    A 1 means conversion of __A. A 0 means element from __W.
 /// \returns A 128-bit vector of [8 x bfloat] comes from conversion of __A.
-static __inline__ __m128bh __DEFAULT_FN_ATTRS256
-_mm256_mask_cvtneps_pbh(__m128bh __W, __mmask8 __U, __m256 __A) {
-  return (__m128bh)__builtin_ia32_cvtneps2bf16_256_mask((__v8sf)__A,
-                                                        (__v8hi)__W,
-                                                        (__mmask8)__U);
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
+_mm256_mask_cvtneps_pbh(__m128i __W, __mmask8 __U, __m256 __A) {
+  return (__m128i)__builtin_ia32_cvtneps2bf16_256_mask((__v8sf)__A,
 }
 
 /// Convert Packed Single Data to Packed BF16 Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VCVTNEPS2BF16 </c> instructions.
 ///
 /// \param __A
 ///    A 256-bit vector of [8 x float].
 /// \param __U
 ///    A 8-bit mask value specifying what is chosen for each element.
 ///    A 1 means conversion of __A. A 0 means element is zero.
 /// \returns A 128-bit vector of [8 x bfloat] comes from conversion of __A.
-static __inline__ __m128bh __DEFAULT_FN_ATTRS256
+static __inline__ __m128i __DEFAULT_FN_ATTRS256
 _mm256_maskz_cvtneps_pbh(__mmask8 __U, __m256 __A) {
-  return (__m128bh)__builtin_ia32_cvtneps2bf16_256_mask((__v8sf)__A,
+  return (__m128i)__builtin_ia32_cvtneps2bf16_256_mask((__v8sf)__A,
                                                     (__v8hi)_mm_setzero_si128(),
                                                     (__mmask8)__U);
 }
 
 /// Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VDPBF16PS </c> instructions.
 ///
 /// \param __A
 ///    A 128-bit vector of [8 x bfloat].
 /// \param __B
 ///    A 128-bit vector of [8 x bfloat].
 /// \param __D
 ///    A 128-bit vector of [4 x float].
 /// \returns A 128-bit vector of [4 x float] comes from  Dot Product of
 ///  __A, __B and __D
 static __inline__ __m128 __DEFAULT_FN_ATTRS128
-_mm_dpbf16_ps(__m128 __D, __m128bh __A, __m128bh __B) {
+_mm_dpbf16_ps(__m128 __D, __m128i __A, __m128i __B) {
   return (__m128)__builtin_ia32_dpbf16ps_128((__v4sf)__D,
                                              (__v4si)__A,
                                              (__v4si)__B);
 }
 
 /// Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VDPBF16PS </c> instructions.
 ///
 /// \param __A
 ///    A 128-bit vector of [8 x bfloat].
 /// \param __B
 ///    A 128-bit vector of [8 x bfloat].
 /// \param __D
 ///    A 128-bit vector of [4 x float].
 /// \param __U
 ///    A 8-bit mask value specifying what is chosen for each element.
 ///    A 1 means __A and __B's dot product accumulated with __D. A 0 means __D.
 /// \returns A 128-bit vector of [4 x float] comes from  Dot Product of
 ///  __A, __B and __D
 static __inline__ __m128 __DEFAULT_FN_ATTRS128
-_mm_mask_dpbf16_ps(__m128 __D, __mmask8 __U, __m128bh __A, __m128bh __B) {
+_mm_mask_dpbf16_ps(__m128 __D, __mmask8 __U, __m128i __A, __m128i __B) {
   return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
                                            (__v4sf)_mm_dpbf16_ps(__D, __A, __B),
                                            (__v4sf)__D);
 }
 
 /// Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VDPBF16PS </c> instructions.
 ///
 /// \param __A
 ///    A 128-bit vector of [8 x bfloat].
 /// \param __B
 ///    A 128-bit vector of [8 x bfloat].
 /// \param __D
 ///    A 128-bit vector of [4 x float].
 /// \param __U
 ///    A 8-bit mask value specifying what is chosen for each element.
 ///    A 1 means __A and __B's dot product accumulated with __D. A 0 means 0.
 /// \returns A 128-bit vector of [4 x float] comes from  Dot Product of
 ///  __A, __B and __D
 static __inline__ __m128 __DEFAULT_FN_ATTRS128
-_mm_maskz_dpbf16_ps(__mmask8 __U, __m128 __D, __m128bh __A, __m128bh __B) {
+_mm_maskz_dpbf16_ps(__mmask8 __U, __m128 __D, __m128i __A, __m128i __B) {
   return (__m128)__builtin_ia32_selectps_128((__mmask8)__U,
                                            (__v4sf)_mm_dpbf16_ps(__D, __A, __B),
                                            (__v4sf)_mm_setzero_si128());
 }
 
 /// Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VDPBF16PS </c> instructions.
 ///
 /// \param __A
 ///    A 256-bit vector of [16 x bfloat].
 /// \param __B
 ///    A 256-bit vector of [16 x bfloat].
 /// \param __D
 ///    A 256-bit vector of [8 x float].
 /// \returns A 256-bit vector of [8 x float] comes from  Dot Product of
 ///  __A, __B and __D
 static __inline__ __m256 __DEFAULT_FN_ATTRS256
-_mm256_dpbf16_ps(__m256 __D, __m256bh __A, __m256bh __B) {
+_mm256_dpbf16_ps(__m256 __D, __m256i __A, __m256i __B) {
   return (__m256)__builtin_ia32_dpbf16ps_256((__v8sf)__D,
                                              (__v8si)__A,
                                              (__v8si)__B);
 }
 
 /// Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VDPBF16PS </c> instructions.
 ///
 /// \param __A
 ///    A 256-bit vector of [16 x bfloat].
 /// \param __B
 ///    A 256-bit vector of [16 x bfloat].
 /// \param __D
 ///    A 256-bit vector of [8 x float].
 /// \param __U
 ///    A 16-bit mask value specifying what is chosen for each element.
 ///    A 1 means __A and __B's dot product accumulated with __D. A 0 means __D.
 /// \returns A 256-bit vector of [8 x float] comes from  Dot Product of
 ///  __A, __B and __D
 static __inline__ __m256 __DEFAULT_FN_ATTRS256
-_mm256_mask_dpbf16_ps(__m256 __D, __mmask8 __U, __m256bh __A, __m256bh __B) {
+_mm256_mask_dpbf16_ps(__m256 __D, __mmask8 __U, __m256i __A, __m256i __B) {
   return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
                                         (__v8sf)_mm256_dpbf16_ps(__D, __A, __B),
                                         (__v8sf)__D);
 }
 
 /// Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// This intrinsic corresponds to the <c> VDPBF16PS </c> instructions.
 ///
 /// \param __A
 ///    A 256-bit vector of [16 x bfloat].
 /// \param __B
 ///    A 256-bit vector of [16 x bfloat].
 /// \param __D
 ///    A 256-bit vector of [8 x float].
 /// \param __U
 ///    A 8-bit mask value specifying what is chosen for each element.
 ///    A 1 means __A and __B's dot product accumulated with __D. A 0 means 0.
 /// \returns A 256-bit vector of [8 x float] comes from  Dot Product of
 ///  __A, __B and __D
 static __inline__ __m256 __DEFAULT_FN_ATTRS256
-_mm256_maskz_dpbf16_ps(__mmask8 __U, __m256 __D, __m256bh __A, __m256bh __B) {
+_mm256_maskz_dpbf16_ps(__mmask8 __U, __m256 __D, __m256i __A, __m256i __B) {
   return (__m256)__builtin_ia32_selectps_256((__mmask8)__U,
                                         (__v8sf)_mm256_dpbf16_ps(__D, __A, __B),
                                         (__v8sf)_mm256_setzero_si256());
 }
 
 /// Convert One Single float Data to One BF16 Data.
 ///
 /// \headerfile <x86intrin.h>

 
 /// Convert Packed BF16 Data to Packed float Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// \param __A
 ///    A 128-bit vector of [4 x bfloat].
 /// \returns A 128-bit vector of [4 x float] come from conversion of __A
-static __inline__ __m128 __DEFAULT_FN_ATTRS128 _mm_cvtpbh_ps(__m128bh __A) {
+static __inline__ __m128 __DEFAULT_FN_ATTRS128 _mm_cvtpbh_ps(__m128i __A) {
   return _mm_castsi128_ps(
       (__m128i)_mm_slli_epi32((__m128i)_mm_cvtepi16_epi32((__m128i)__A), 16));
 }
 
 /// Convert Packed BF16 Data to Packed float Data.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// \param __A
 ///    A 128-bit vector of [8 x bfloat].
 /// \returns A 256-bit vector of [8 x float] come from conversion of __A
-static __inline__ __m256 __DEFAULT_FN_ATTRS256 _mm256_cvtpbh_ps(__m128bh __A) {
+static __inline__ __m256 __DEFAULT_FN_ATTRS256 _mm256_cvtpbh_ps(__m128i __A) {
   return _mm256_castsi256_ps((__m256i)_mm256_slli_epi32(
       (__m256i)_mm256_cvtepi16_epi32((__m128i)__A), 16));
 }
 
 /// Convert Packed BF16 Data to Packed float Data using zeroing mask.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// \param __U
 ///    A 4-bit mask. Elements are zeroed out when the corresponding mask
 ///    bit is not set.
 /// \param __A
 ///    A 128-bit vector of [4 x bfloat].
 /// \returns A 128-bit vector of [4 x float] come from conversion of __A
 static __inline__ __m128 __DEFAULT_FN_ATTRS128
-_mm_maskz_cvtpbh_ps(__mmask8 __U, __m128bh __A) {
+_mm_maskz_cvtpbh_ps(__mmask8 __U, __m128i __A) {
   return _mm_castsi128_ps((__m128i)_mm_slli_epi32(
       (__m128i)_mm_maskz_cvtepi16_epi32((__mmask8)__U, (__m128i)__A), 16));
 }
 
 /// Convert Packed BF16 Data to Packed float Data using zeroing mask.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// \param __U
 ///    A 8-bit mask. Elements are zeroed out when the corresponding mask
 ///    bit is not set.
 /// \param __A
 ///    A 128-bit vector of [8 x bfloat].
 /// \returns A 256-bit vector of [8 x float] come from conversion of __A
 static __inline__ __m256 __DEFAULT_FN_ATTRS256
-_mm256_maskz_cvtpbh_ps(__mmask8 __U, __m128bh __A) {
+_mm256_maskz_cvtpbh_ps(__mmask8 __U, __m128i __A) {
   return _mm256_castsi256_ps((__m256i)_mm256_slli_epi32(
       (__m256i)_mm256_maskz_cvtepi16_epi32((__mmask8)__U, (__m128i)__A), 16));
 }
 
 /// Convert Packed BF16 Data to Packed float Data using merging mask.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// \param __S
 ///    A 128-bit vector of [4 x float]. Elements are copied from __S when
 ///     the corresponding mask bit is not set.
 /// \param __U
 ///    A 4-bit mask. Elements are zeroed out when the corresponding mask
 ///    bit is not set.
 /// \param __A
 ///    A 128-bit vector of [4 x bfloat].
 /// \returns A 128-bit vector of [4 x float] come from conversion of __A
 static __inline__ __m128 __DEFAULT_FN_ATTRS128
-_mm_mask_cvtpbh_ps(__m128 __S, __mmask8 __U, __m128bh __A) {
+_mm_mask_cvtpbh_ps(__m128 __S, __mmask8 __U, __m128i __A) {
   return _mm_castsi128_ps((__m128i)_mm_mask_slli_epi32(
       (__m128i)__S, (__mmask8)__U, (__m128i)_mm_cvtepi16_epi32((__m128i)__A),
       16));
 }
 
 /// Convert Packed BF16 Data to Packed float Data using merging mask.
 ///
 /// \headerfile <x86intrin.h>
 ///
 /// \param __S
 ///    A 256-bit vector of [8 x float]. Elements are copied from __S when
 ///     the corresponding mask bit is not set.
 /// \param __U
 ///    A 8-bit mask. Elements are zeroed out when the corresponding mask
 ///    bit is not set.
 /// \param __A
 ///    A 128-bit vector of [8 x bfloat].
 /// \returns A 256-bit vector of [8 x float] come from conversion of __A
 static __inline__ __m256 __DEFAULT_FN_ATTRS256
-_mm256_mask_cvtpbh_ps(__m256 __S, __mmask8 __U, __m128bh __A) {
+_mm256_mask_cvtpbh_ps(__m256 __S, __mmask8 __U, __m128i __A) {
   return _mm256_castsi256_ps((__m256i)_mm256_mask_slli_epi32(
       (__m256i)__S, (__mmask8)__U, (__m256i)_mm256_cvtepi16_epi32((__m128i)__A),
       16));
 }
 
 #undef __DEFAULT_FN_ATTRS128
 #undef __DEFAULT_FN_ATTRS256
 
 #endif

clang/test/CodeGen/X86/avx512bf16-builtins.c

 //  RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin \
 //  RUN:            -target-feature +avx512bf16 -emit-llvm -o - -Wall -Werror \
 //  RUN:            | FileCheck %s
 
 #include <immintrin.h>
 
 float test_mm_cvtsbh_ss(__bfloat16 A) {
   // CHECK-LABEL: @test_mm_cvtsbh_ss
   // CHECK: zext i16 %{{.*}} to i32
   // CHECK: shl i32 %{{.*}}, 16
   // CHECK: bitcast i32 %{{.*}} to float
   // CHECK: ret float %{{.*}}
   return _mm_cvtsbh_ss(A);
 }
 
-__m512bh test_mm512_cvtne2ps_pbh(__m512 A, __m512 B) {
+__m512i test_mm512_cvtne2ps_pbh(__m512 A, __m512 B) {
   // CHECK-LABEL: @test_mm512_cvtne2ps_pbh
   // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.512
-  // CHECK: ret <32 x i16> %{{.*}}
+  // CHECK: ret <8 x i64> %{{.*}}
   return _mm512_cvtne2ps_pbh(A, B);
 }
 
-__m512bh test_mm512_maskz_cvtne2ps_pbh(__m512 A, __m512 B, __mmask32 U) {
+__m512i test_mm512_maskz_cvtne2ps_pbh(__m512 A, __m512 B, __mmask32 U) {
   // CHECK-LABEL: @test_mm512_maskz_cvtne2ps_pbh
   // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.512
   // CHECK: select <32 x i1> %{{.*}}, <32 x i16> %{{.*}}, <32 x i16> %{{.*}}
-  // CHECK: ret <32 x i16> %{{.*}}
+  // CHECK: ret <8 x i64> %{{.*}}
   return _mm512_maskz_cvtne2ps_pbh(U, A, B);
 }
 
-__m512bh test_mm512_mask_cvtne2ps_pbh(__m512bh C, __mmask32 U, __m512 A, __m512 B) {
+__m512i test_mm512_mask_cvtne2ps_pbh(__m512i C, __mmask32 U, __m512 A, __m512 B) {
   // CHECK-LABEL: @test_mm512_mask_cvtne2ps_pbh
   // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.512
   // CHECK: select <32 x i1> %{{.*}}, <32 x i16> %{{.*}}, <32 x i16> %{{.*}}
-  // CHECK: ret <32 x i16> %{{.*}}
+  // CHECK: ret <8 x i64> %{{.*}}
   return _mm512_mask_cvtne2ps_pbh(C, U, A, B);
 }
 
-__m256bh test_mm512_cvtneps_pbh(__m512 A) {
+__m256i test_mm512_cvtneps_pbh(__m512 A) {
   // CHECK-LABEL: @test_mm512_cvtneps_pbh
   // CHECK: @llvm.x86.avx512bf16.cvtneps2bf16.512
-  // CHECK: ret <16 x i16> %{{.*}}
+  // CHECK: ret <4 x i64> %{{.*}}
   return _mm512_cvtneps_pbh(A);
 }
 
-__m256bh test_mm512_mask_cvtneps_pbh(__m256bh C, __mmask16 U, __m512 A) {
+__m256i test_mm512_mask_cvtneps_pbh(__m256i C, __mmask16 U, __m512 A) {
   // CHECK-LABEL: @test_mm512_mask_cvtneps_pbh
   // CHECK: @llvm.x86.avx512bf16.cvtneps2bf16.512
   // CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
-  // CHECK: ret <16 x i16> %{{.*}}
+  // CHECK: ret <4 x i64> %{{.*}}
   return _mm512_mask_cvtneps_pbh(C, U, A);
 }
 
-__m256bh test_mm512_maskz_cvtneps_pbh(__m512 A, __mmask16 U) {
+__m256i test_mm512_maskz_cvtneps_pbh(__m512 A, __mmask16 U) {
   // CHECK-LABEL: @test_mm512_maskz_cvtneps_pbh
   // CHECK: @llvm.x86.avx512bf16.cvtneps2bf16.512
   // CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
-  // CHECK: ret <16 x i16> %{{.*}}
+  // CHECK: ret <4 x i64> %{{.*}}
   return _mm512_maskz_cvtneps_pbh(U, A);
 }
 
-__m512 test_mm512_dpbf16_ps(__m512 D, __m512bh A, __m512bh B) {
+__m512 test_mm512_dpbf16_ps(__m512 D, __m512i A, __m512i B) {
   // CHECK-LABEL: @test_mm512_dpbf16_ps
   // CHECK: @llvm.x86.avx512bf16.dpbf16ps.512
   // CHECK: ret <16 x float> %{{.*}}
   return _mm512_dpbf16_ps(D, A, B);
 }
 
-__m512 test_mm512_maskz_dpbf16_ps(__m512 D, __m512bh A, __m512bh B, __mmask16 U) {
+__m512 test_mm512_maskz_dpbf16_ps(__m512 D, __m512i A, __m512i B, __mmask16 U) {
   // CHECK-LABEL: @test_mm512_maskz_dpbf16_ps
   // CHECK: @llvm.x86.avx512bf16.dpbf16ps.512
   // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
   // CHECK: ret <16 x float> %{{.*}}
   return _mm512_maskz_dpbf16_ps(U, D, A, B);
 }
 
-__m512 test_mm512_mask_dpbf16_ps(__m512 D, __m512bh A, __m512bh B, __mmask16 U) {
+__m512 test_mm512_mask_dpbf16_ps(__m512 D, __m512i A, __m512i B, __mmask16 U) {
   // CHECK-LABEL: @test_mm512_mask_dpbf16_ps
   // CHECK: @llvm.x86.avx512bf16.dpbf16ps.512
   // CHECK: select <16 x i1> %{{.*}}, <16 x float> %{{.*}}, <16 x float> %{{.*}}
   // CHECK: ret <16 x float> %{{.*}}
   return _mm512_mask_dpbf16_ps(D, U, A, B);
 }
 
-__m512 test_mm512_cvtpbh_ps(__m256bh A) {
+__m512 test_mm512_cvtpbh_ps(__m256i A) {
   // CHECK-LABEL: @test_mm512_cvtpbh_ps
-  // CHECK: sext <16 x i16> %{{.*}} to <16 x i32>
+  // CHECK: bitcast <8 x i64> %{{.*}} to <16 x i32>
   // CHECK: @llvm.x86.avx512.pslli.d.512
   // CHECK: bitcast <8 x i64> %{{.*}} to <16 x float>
   // CHECK: ret <16 x float> %{{.*}}
   return _mm512_cvtpbh_ps(A);
 }
 
-__m512 test_mm512_maskz_cvtpbh_ps(__mmask16 M, __m256bh A) {
+__m512 test_mm512_maskz_cvtpbh_ps(__mmask16 M, __m256i A) {
   // CHECK-LABEL: @test_mm512_maskz_cvtpbh_ps
-  // CHECK: sext <16 x i16> %{{.*}} to <16 x i32>
+  // CHECK: bitcast <8 x i64> %{{.*}} to <16 x i32>
   // CHECK: select <16 x i1> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> %{{.*}}
   // CHECK: @llvm.x86.avx512.pslli.d.512
   // CHECK: bitcast <8 x i64> %{{.*}} to <16 x float>
   // CHECK: ret <16 x float> %{{.*}}
   return _mm512_maskz_cvtpbh_ps(M, A);
 }
 
-__m512 test_mm512_mask_cvtpbh_ps(__m512 S, __mmask16 M, __m256bh A) {
+__m512 test_mm512_mask_cvtpbh_ps(__m512 S, __mmask16 M, __m256i A) {
   // CHECK-LABEL: @test_mm512_mask_cvtpbh_ps
-  // CHECK: sext <16 x i16> %{{.*}} to <16 x i32>
+  // CHECK: bitcast <8 x i64> %{{.*}} to <16 x i32>
   // CHECK: @llvm.x86.avx512.pslli.d.512
   // CHECK: select <16 x i1> %{{.*}}, <16 x i32> %{{.*}}, <16 x i32> %{{.*}}
   // CHECK: bitcast <8 x i64> %{{.*}} to <16 x float>
   // CHECK: ret <16 x float> %{{.*}}
   return _mm512_mask_cvtpbh_ps(S, M, A);
 }

clang/test/CodeGen/X86/avx512bf16-error.c

 // RUN: %clang_cc1 -fsyntax-only -verify -ffreestanding -triple x86_64-linux-pc %s
 
 // expected-error@+1 3 {{unknown type name '__bfloat16'}}
 __bfloat16 foo(__bfloat16 a, __bfloat16 b) {
   return a + b;
 }
 
 #include <immintrin.h>
 
 // expected-error@+2 {{invalid operands to binary expression ('__bfloat16' (aka 'struct __bfloat16_s') and '__bfloat16')}}
 __bfloat16 bar(__bfloat16 a, __bfloat16 b) {
   return a + b;
 }
+
+// expected-warning@+2 3 {{'__m128bh' is deprecated: use __m128i instead}}
+// expected-note@* 3 {{'__m128bh' has been explicitly marked deprecated here}}
+__m128bh baz(__m128bh a, __m128bh b) {
+  return a + b;
+}

clang/test/CodeGen/X86/avx512vlbf16-builtins.c

 //  RUN: %clang_cc1 -flax-vector-conversions=none -ffreestanding %s -triple=x86_64-apple-darwin \
 //  RUN:            -target-feature +avx512bf16 -target-feature \
 //  RUN:            +avx512vl -emit-llvm -o - -Wall -Werror | FileCheck %s
 
 #include <immintrin.h>
 
-__m128bh test_mm_cvtne2ps2bf16(__m128 A, __m128 B) {
+__m128i test_mm_cvtne2ps2bf16(__m128 A, __m128 B) {
   // CHECK-LABEL: @test_mm_cvtne2ps2bf16
   // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.128
-  // CHECK: ret <8 x i16> %{{.*}}
+  // CHECK: ret <2 x i64> %{{.*}}
   return _mm_cvtne2ps_pbh(A, B);
 }
 
-__m128bh test_mm_maskz_cvtne2ps2bf16(__m128 A, __m128 B, __mmask8 U) {
+__m128i test_mm_maskz_cvtne2ps2bf16(__m128 A, __m128 B, __mmask8 U) {
   // CHECK-LABEL: @test_mm_maskz_cvtne2ps2bf16
   // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.128
   // CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
-  // CHECK: ret <8 x i16> %{{.*}}
+  // CHECK: ret <2 x i64> %{{.*}}
   return _mm_maskz_cvtne2ps_pbh(U, A, B);
 }
 
-__m128bh test_mm_mask_cvtne2ps2bf16(__m128bh C, __mmask8 U, __m128 A, __m128 B) {
+__m128i test_mm_mask_cvtne2ps2bf16(__m128i C, __mmask8 U, __m128 A, __m128 B) {
   // CHECK-LABEL: @test_mm_mask_cvtne2ps2bf16
   // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.128
   // CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
-  // CHECK: ret <8 x i16> %{{.*}}
+  // CHECK: ret <2 x i64> %{{.*}}
   return _mm_mask_cvtne2ps_pbh(C, U, A, B);
 }
 
-__m256bh test_mm256_cvtne2ps2bf16(__m256 A, __m256 B) {
+__m256i test_mm256_cvtne2ps2bf16(__m256 A, __m256 B) {
   // CHECK-LABEL: @test_mm256_cvtne2ps2bf16
   // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.256
-  // CHECK: ret <16 x i16> %{{.*}}
+  // CHECK: ret <4 x i64> %{{.*}}
   return _mm256_cvtne2ps_pbh(A, B);
 }
 
-__m256bh test_mm256_maskz_cvtne2ps2bf16(__m256 A, __m256 B, __mmask16 U) {
+__m256i test_mm256_maskz_cvtne2ps2bf16(__m256 A, __m256 B, __mmask16 U) {
   // CHECK-LABEL: @test_mm256_maskz_cvtne2ps2bf16
   // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.256
   // CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
-  // CHECK: ret <16 x i16> %{{.*}}
+  // CHECK: ret <4 x i64> %{{.*}}
   return _mm256_maskz_cvtne2ps_pbh(U, A, B);
 }
 
-__m256bh test_mm256_mask_cvtne2ps2bf16(__m256bh C, __mmask16 U, __m256 A, __m256 B) {
+__m256i test_mm256_mask_cvtne2ps2bf16(__m256i C, __mmask16 U, __m256 A, __m256 B) {
   // CHECK-LABEL: @test_mm256_mask_cvtne2ps2bf16
   // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.256
   // CHECK: select <16 x i1> %{{.*}}, <16 x i16> %{{.*}}, <16 x i16> %{{.*}}
-  // CHECK: ret <16 x i16> %{{.*}}
+  // CHECK: ret <4 x i64> %{{.*}}
   return _mm256_mask_cvtne2ps_pbh(C, U, A, B);
 }
 
-__m512bh test_mm512_cvtne2ps2bf16(__m512 A, __m512 B) {
+__m512i test_mm512_cvtne2ps2bf16(__m512 A, __m512 B) {
   // CHECK-LABEL: @test_mm512_cvtne2ps2bf16
   // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.512
-  // CHECK: ret <32 x i16> %{{.*}}
+  // CHECK: ret <8 x i64> %{{.*}}
   return _mm512_cvtne2ps_pbh(A, B);
 }
 
-__m512bh test_mm512_maskz_cvtne2ps2bf16(__m512 A, __m512 B, __mmask32 U) {
+__m512i test_mm512_maskz_cvtne2ps2bf16(__m512 A, __m512 B, __mmask32 U) {
   // CHECK-LABEL: @test_mm512_maskz_cvtne2ps2bf16
   // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.512
   // CHECK: select <32 x i1> %{{.*}}, <32 x i16> %{{.*}}, <32 x i16> %{{.*}}
-  // CHECK: ret <32 x i16> %{{.*}}
+  // CHECK: ret <8 x i64> %{{.*}}
   return _mm512_maskz_cvtne2ps_pbh(U, A, B);
 }
 
-__m512bh test_mm512_mask_cvtne2ps2bf16(__m512bh C, __mmask32 U, __m512 A, __m512 B) {
+__m512i test_mm512_mask_cvtne2ps2bf16(__m512i C, __mmask32 U, __m512 A, __m512 B) {
   // CHECK-LABEL: @test_mm512_mask_cvtne2ps2bf16
   // CHECK: @llvm.x86.avx512bf16.cvtne2ps2bf16.512
   // CHECK: select <32 x i1> %{{.*}}, <32 x i16> %{{.*}}, <32 x i16> %{{.*}}
-  // CHECK: ret <32 x i16> %{{.*}}
+  // CHECK: ret <8 x i64> %{{.*}}
   return _mm512_mask_cvtne2ps_pbh(C, U, A, B);
 }
 
-__m128bh test_mm_cvtneps2bf16(__m128 A) {
+__m128i test_mm_cvtneps2bf16(__m128 A) {
   // CHECK-LABEL: @test_mm_cvtneps2bf16
   // CHECK: @llvm.x86.avx512bf16.mask.cvtneps2bf16.128
-  // CHECK: ret <8 x i16> %{{.*}}
+  // CHECK: ret <2 x i64> %{{.*}}
   return _mm_cvtneps_pbh(A);
 }
 
-__m128bh test_mm_mask_cvtneps2bf16(__m128bh C, __mmask8 U, __m128 A) {
+__m128i test_mm_mask_cvtneps2bf16(__m128i C, __mmask8 U, __m128 A) {
   // CHECK-LABEL: @test_mm_mask_cvtneps2bf16
   // CHECK: @llvm.x86.avx512bf16.mask.cvtneps2bf16.
-  // CHECK: ret <8 x i16> %{{.*}}
+  // CHECK: ret <2 x i64> %{{.*}}
   return _mm_mask_cvtneps_pbh(C, U, A);
 }
 
-__m128bh test_mm_maskz_cvtneps2bf16(__m128 A, __mmask8 U) {
+__m128i test_mm_maskz_cvtneps2bf16(__m128 A, __mmask8 U) {
   // CHECK-LABEL: @test_mm_maskz_cvtneps2bf16
   // CHECK: @llvm.x86.avx512bf16.mask.cvtneps2bf16.128
-  // CHECK: ret <8 x i16> %{{.*}}
+  // CHECK: ret <2 x i64> %{{.*}}
   return _mm_maskz_cvtneps_pbh(U, A);
 }
 
-__m128bh test_mm256_cvtneps2bf16(__m256 A) {
+__m128i test_mm256_cvtneps2bf16(__m256 A) {
   // CHECK-LABEL: @test_mm256_cvtneps2bf16
   // CHECK: @llvm.x86.avx512bf16.cvtneps2bf16.256
-  // CHECK: ret <8 x i16> %{{.*}}
+  // CHECK: ret <2 x i64> %{{.*}}
   return _mm256_cvtneps_pbh(A);
 }
 
-__m128bh test_mm256_mask_cvtneps2bf16(__m128bh C, __mmask8 U, __m256 A) {
+__m128i test_mm256_mask_cvtneps2bf16(__m128i C, __mmask8 U, __m256 A) {
   // CHECK-LABEL: @test_mm256_mask_cvtneps2bf16
   // CHECK: @llvm.x86.avx512bf16.cvtneps2bf16.256
   // CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
-  // CHECK: ret <8 x i16> %{{.*}}
+  // CHECK: ret <2 x i64> %{{.*}}
   return _mm256_mask_cvtneps_pbh(C, U, A);
 }
 
-__m128bh test_mm256_maskz_cvtneps2bf16(__m256 A, __mmask8 U) {
+__m128i test_mm256_maskz_cvtneps2bf16(__m256 A, __mmask8 U) {
   // CHECK-LABEL: @test_mm256_maskz_cvtneps2bf16
   // CHECK: @llvm.x86.avx512bf16.cvtneps2bf16.256
   // CHECK: select <8 x i1> %{{.*}}, <8 x i16> %{{.*}}, <8 x i16> %{{.*}}
-  // CHECK: ret <8 x i16> %{{.*}}
+  // CHECK: ret <2 x i64> %{{.*}}
   return _mm256_maskz_cvtneps_pbh(U, A);
 }
 
-__m128 test_mm_dpbf16_ps(__m128 D, __m128bh A, __m128bh B) {
+__m128 test_mm_dpbf16_ps(__m128 D, __m128i A, __m128i B) {
   // CHECK-LABEL: @test_mm_dpbf16_ps
   // CHECK: @llvm.x86.avx512bf16.dpbf16ps.128
   // CHECK: ret <4 x float> %{{.*}}
   return _mm_dpbf16_ps(D, A, B);
 }
 
-__m128 test_mm_maskz_dpbf16_ps(__m128 D, __m128bh A, __m128bh B, __mmask8 U) {
+__m128 test_mm_maskz_dpbf16_ps(__m128 D, __m128i A, __m128i B, __mmask8 U) {
   // CHECK-LABEL: @test_mm_maskz_dpbf16_ps
   // CHECK: @llvm.x86.avx512bf16.dpbf16ps.128
   // CHECK: select <4 x i1> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}
   // CHECK: ret <4 x float> %{{.*}}
   return _mm_maskz_dpbf16_ps(U, D, A, B);
 }
 
-__m128 test_mm_mask_dpbf16_ps(__m128 D, __m128bh A, __m128bh B, __mmask8 U) {
+__m128 test_mm_mask_dpbf16_ps(__m128 D, __m128i A, __m128i B, __mmask8 U) {
   // CHECK-LABEL: @test_mm_mask_dpbf16_ps
   // CHECK: @llvm.x86.avx512bf16.dpbf16ps.128
   // CHECK: select <4 x i1> %{{.*}}, <4 x float> %{{.*}}, <4 x float> %{{.*}}
   // CHECK: ret <4 x float> %{{.*}}
   return _mm_mask_dpbf16_ps(D, U, A, B);
 }
-__m256 test_mm256_dpbf16_ps(__m256 D, __m256bh A, __m256bh B) {
+__m256 test_mm256_dpbf16_ps(__m256 D, __m256i A, __m256i B) {
   // CHECK-LABEL: @test_mm256_dpbf16_ps
   // CHECK: @llvm.x86.avx512bf16.dpbf16ps.256
   // CHECK: ret <8 x float> %{{.*}}
   return _mm256_dpbf16_ps(D, A, B);
 }
 
-__m256 test_mm256_maskz_dpbf16_ps(__m256 D, __m256bh A, __m256bh B, __mmask8 U) {
+__m256 test_mm256_maskz_dpbf16_ps(__m256 D, __m256i A, __m256i B, __mmask8 U) {
   // CHECK-LABEL: @test_mm256_maskz_dpbf16_ps
   // CHECK: @llvm.x86.avx512bf16.dpbf16ps.256
   // CHECK: select <8 x i1> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}
   // CHECK: ret <8 x float> %{{.*}}
   return _mm256_maskz_dpbf16_ps(U, D, A, B);
 }
 
-__m256 test_mm256_mask_dpbf16_ps(__m256 D, __m256bh A, __m256bh B, __mmask8 U) {
+__m256 test_mm256_mask_dpbf16_ps(__m256 D, __m256i A, __m256i B, __mmask8 U) {
   // CHECK-LABEL: @test_mm256_mask_dpbf16_ps
   // CHECK: @llvm.x86.avx512bf16.dpbf16ps.256
   // CHECK: select <8 x i1> %{{.*}}, <8 x float> %{{.*}}, <8 x float> %{{.*}}
   // CHECK: ret <8 x float> %{{.*}}
   return _mm256_mask_dpbf16_ps(D, U, A, B);
 }
 
 __bfloat16 test_mm_cvtness_sbh(float A) {
   // CHECK-LABEL: @test_mm_cvtness_sbh
   // CHECK: @llvm.x86.avx512bf16.mask.cvtneps2bf16.128
   // CHECK: ret i16 %{{.*}}
   return _mm_cvtness_sbh(A);
 }
 
-__m128 test_mm_cvtpbh_ps(__m128bh A) {
+__m128 test_mm_cvtpbh_ps(__m128i A) {
   // CHECK-LABEL: @test_mm_cvtpbh_ps
   // CHECK: sext <4 x i16> %{{.*}} to <4 x i32>
   // CHECK: @llvm.x86.sse2.pslli.d
   // CHECK: bitcast <2 x i64> %{{.*}} to <4 x float>
   // CHECK: ret <4 x float> %{{.*}}
   return _mm_cvtpbh_ps(A);
 }
 
-__m256 test_mm256_cvtpbh_ps(__m128bh A) {
+__m256 test_mm256_cvtpbh_ps(__m128i A) {
   // CHECK-LABEL: @test_mm256_cvtpbh_ps
   // CHECK: sext <8 x i16> %{{.*}} to <8 x i32>
   // CHECK: @llvm.x86.avx2.pslli.d
   // CHECK: bitcast <4 x i64> %{{.*}} to <8 x float>
   // CHECK: ret <8 x float> %{{.*}}
   return _mm256_cvtpbh_ps(A);
 }
 
-__m128 test_mm_maskz_cvtpbh_ps(__mmask8 M, __m128bh A) {
+__m128 test_mm_maskz_cvtpbh_ps(__mmask8 M, __m128i A) {
   // CHECK-LABEL: @test_mm_maskz_cvtpbh_ps
   // CHECK: sext <4 x i16> %{{.*}} to <4 x i32>
   // CHECK: select <4 x i1> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}
   // CHECK: @llvm.x86.sse2.pslli.d
   // CHECK: bitcast <2 x i64> %{{.*}} to <4 x float>
   // CHECK: ret <4 x float> %{{.*}}
   return _mm_maskz_cvtpbh_ps(M, A);
 }
 
-__m256 test_mm256_maskz_cvtpbh_ps(__mmask8 M, __m128bh A) {
+__m256 test_mm256_maskz_cvtpbh_ps(__mmask8 M, __m128i A) {
   // CHECK-LABEL: @test_mm256_maskz_cvtpbh_ps
   // CHECK: sext <8 x i16> %{{.*}} to <8 x i32>
   // CHECK: select <8 x i1> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> %{{.*}}
   // CHECK: @llvm.x86.avx2.pslli.d
   // CHECK: bitcast <4 x i64> %{{.*}} to <8 x float>
   // CHECK: ret <8 x float> %{{.*}}
   return _mm256_maskz_cvtpbh_ps(M, A);
 }
 
-__m128 test_mm_mask_cvtpbh_ps(__m128 S, __mmask8 M, __m128bh A) {
+__m128 test_mm_mask_cvtpbh_ps(__m128 S, __mmask8 M, __m128i A) {
   // CHECK-LABEL: @test_mm_mask_cvtpbh_ps
   // CHECK: sext <4 x i16> %{{.*}} to <4 x i32>
   // CHECK: @llvm.x86.sse2.pslli.d
   // CHECK: select <4 x i1> %{{.*}}, <4 x i32> %{{.*}}, <4 x i32> %{{.*}}
   // CHECK: bitcast <2 x i64> %{{.*}} to <4 x float>
   // CHECK: ret <4 x float> %{{.*}}
   return _mm_mask_cvtpbh_ps(S, M, A);
 }
 
-__m256 test_mm256_mask_cvtpbh_ps(__m256 S, __mmask8 M, __m128bh A) {
+__m256 test_mm256_mask_cvtpbh_ps(__m256 S, __mmask8 M, __m128i A) {
   // CHECK-LABEL: @test_mm256_mask_cvtpbh_ps
   // CHECK: sext <8 x i16> %{{.*}} to <8 x i32>
   // CHECK: @llvm.x86.avx2.pslli.d
   // CHECK: select <8 x i1> %{{.*}}, <8 x i32> %{{.*}}, <8 x i32> %{{.*}}
   // CHECK: bitcast <4 x i64> %{{.*}} to <8 x float>
   // CHECK: ret <8 x float> %{{.*}}
   return _mm256_mask_cvtpbh_ps(S, M, A);
 }