diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp --- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp @@ -1059,10 +1059,10 @@ // If Callee is a reg, since it is used by a target specific instruction, // it must have a register class matching the constraint of that instruction. - if (Info.Callee.isReg()) + if (MIB->getOperand(0).isReg()) constrainOperandRegClass(MF, *TRI, MRI, *MF.getSubtarget().getInstrInfo(), *MF.getSubtarget().getRegBankInfo(), *MIB, - MIB->getDesc(), Info.Callee, 0); + MIB->getDesc(), MIB->getOperand(0), 0); MF.getFrameInfo().setHasTailCall(); Info.LoweredTailCall = true; @@ -1139,12 +1139,16 @@ Opc = getCallOpcode(MF, Info.Callee.isReg(), false); auto MIB = MIRBuilder.buildInstrNoInsert(Opc); + unsigned CalleeOpNo = 0; + if (Opc == AArch64::BLR_RVMARKER) { // Add a target global address for the retainRV/claimRV runtime function // just before the call target. Function *ARCFn = *objcarc::getAttachedARCFunction(Info.CB); MIB.addGlobalAddress(ARCFn); + ++CalleeOpNo; } + MIB.add(Info.Callee); // Tell the call which registers are clobbered. @@ -1175,10 +1179,10 @@ // If Callee is a reg, since it is used by a target specific // instruction, it must have a register class matching the // constraint of that instruction. - if (Info.Callee.isReg()) + if (MIB->getOperand(CalleeOpNo).isReg()) constrainOperandRegClass(MF, *TRI, MRI, *Subtarget.getInstrInfo(), *Subtarget.getRegBankInfo(), *MIB, MIB->getDesc(), - Info.Callee, 0); + MIB->getOperand(CalleeOpNo), CalleeOpNo); // Finally we can copy the returned value back into its virtual-register. In // symmetry with the arguments, the physical register must be an