diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -270,13 +270,17 @@
   unsigned NF = 1;
   RISCVII::VLMUL LMul = RISCVII::LMUL_1;
   unsigned SubRegIdx = RISCV::sub_vrm1_0;
-  if (RISCV::FPR16RegClass.contains(DstReg, SrcReg)) {
+  if (RISCV::FPR16RegClass.contains(DstReg, SrcReg) ||
+      RISCV::GPRF16RegClass.contains(DstReg, SrcReg)) {
     Opc = RISCV::FSGNJ_H;
     IsScalableVector = false;
-  } else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg)) {
+  } else if (RISCV::FPR32RegClass.contains(DstReg, SrcReg) ||
+             RISCV::GPRF32RegClass.contains(DstReg, SrcReg)) {
     Opc = RISCV::FSGNJ_S;
     IsScalableVector = false;
-  } else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg)) {
+  } else if (RISCV::FPR64RegClass.contains(DstReg, SrcReg) ||
+             RISCV::GPRF64RegClass.contains(DstReg, SrcReg) ||
+             RISCV::GPRPF64RegClass.contains(DstReg, SrcReg)) {
     Opc = RISCV::FSGNJ_D;
     IsScalableVector = false;
   } else if (RISCV::VRRegClass.contains(DstReg, SrcReg)) {