diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -162,7 +162,7 @@ OperandMatchResultTy parseRegister(OperandVector &Operands, bool AllowParens = false); OperandMatchResultTy parseMemOpBaseReg(OperandVector &Operands); - OperandMatchResultTy parseAtomicMemOp(OperandVector &Operands); + OperandMatchResultTy parseZeroOffsetMemOp(OperandVector &Operands); OperandMatchResultTy parseOperandWithModifier(OperandVector &Operands); OperandMatchResultTy parseBareSymbol(OperandVector &Operands); OperandMatchResultTy parseCallSymbol(OperandVector &Operands); @@ -1858,7 +1858,8 @@ return MatchOperand_Success; } -OperandMatchResultTy RISCVAsmParser::parseAtomicMemOp(OperandVector &Operands) { +OperandMatchResultTy +RISCVAsmParser::parseZeroOffsetMemOp(OperandVector &Operands) { // Atomic operations such as lr.w, sc.w, and amo*.w accept a "memory operand" // as one of their register operands, such as `(a0)`. This just denotes that // the register (in this case `a0`) contains a memory address. @@ -1874,9 +1875,9 @@ // offset if it is zero; require (and discard) parentheses; and add only the // parsed register operand to `Operands`. // - // These operands are printed with RISCVInstPrinter::printAtomicMemOp, which - // will only print the register surrounded by parentheses (which GNU as also - // uses as its canonical representation for these operands). + // These operands are printed with RISCVInstPrinter::printZeroOffsetMemOp, + // which will only print the register surrounded by parentheses (which GNU as + // also uses as its canonical representation for these operands). std::unique_ptr OptionalImmOp; if (getLexer().isNot(AsmToken::LParen)) { diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h @@ -40,8 +40,8 @@ const MCSubtargetInfo &STI, raw_ostream &O); void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); - void printAtomicMemOp(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, raw_ostream &O); + void printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, raw_ostream &O); void printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); void printVMaskReg(const MCInst *MI, unsigned OpNo, diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -156,12 +156,12 @@ O << RISCVFPRndMode::roundingModeToString(FRMArg); } -void RISCVInstPrinter::printAtomicMemOp(const MCInst *MI, unsigned OpNo, - const MCSubtargetInfo &STI, - raw_ostream &O) { +void RISCVInstPrinter::printZeroOffsetMemOp(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { const MCOperand &MO = MI->getOperand(OpNo); - assert(MO.isReg() && "printAtomicMemOp can only print register operands"); + assert(MO.isReg() && "printZeroOffsetMemOp can only print register operands"); O << "("; printRegName(O, MO.getReg()); O << ")"; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -105,6 +105,19 @@ let DiagnosticType = !strconcat("Invalid", Name); } +// A parse method for (${gpr}) or 0(${gpr}), where the 0 is be silently ignored. +def ZeroOffsetMemOpOperand : AsmOperandClass { + let Name = "ZeroOffsetMemOpOperand"; + let RenderMethod = "addRegOperands"; + let PredicateMethod = "isGPR"; + let ParserMethod = "parseZeroOffsetMemOp"; +} + +def GPRMemZeroOffset : RegisterOperand { + let ParserMatchClass = ZeroOffsetMemOpOperand; + let PrintMethod = "printZeroOffsetMemOp"; +} + class SImmAsmOperand : ImmAsmOperand<"S", width, suffix> { } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td @@ -11,24 +11,6 @@ // //===----------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// -// Operand and SDNode transformation definitions. -//===----------------------------------------------------------------------===// - -// A parse method for (${gpr}) or 0(${gpr}), where the 0 is be silently ignored. -// Used for GNU as Compatibility. -def AtomicMemOpOperand : AsmOperandClass { - let Name = "AtomicMemOpOperand"; - let RenderMethod = "addRegOperands"; - let PredicateMethod = "isGPR"; - let ParserMethod = "parseAtomicMemOp"; -} - -def GPRMemAtomic : RegisterOperand { - let ParserMatchClass = AtomicMemOpOperand; - let PrintMethod = "printAtomicMemOp"; -} - //===----------------------------------------------------------------------===// // Instruction class templates //===----------------------------------------------------------------------===// @@ -36,7 +18,7 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in class LR_r funct3, string opcodestr> : RVInstRAtomic<0b00010, aq, rl, funct3, OPC_AMO, - (outs GPR:$rd), (ins GPRMemAtomic:$rs1), + (outs GPR:$rd), (ins GPRMemZeroOffset:$rs1), opcodestr, "$rd, $rs1"> { let rs2 = 0; } @@ -51,7 +33,7 @@ let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in class AMO_rr funct5, bit aq, bit rl, bits<3> funct3, string opcodestr> : RVInstRAtomic; multiclass AMO_rr_aq_rl funct5, bits<3> funct3, string opcodestr> {