diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1005,6 +1005,8 @@
   VSETVLIInfo CurInfo;
   // Only be set if current VSETVLIInfo is from an explicit VSET(I)VLI.
   MachineInstr *PrevVSETVLIMI = nullptr;
+  // Only be set if VSET(I)VLI is from ScalarMove.
+  MachineInstr *ScalarMoveVSETVLI = nullptr;
 
   for (MachineInstr &MI : MBB) {
     // If this is an explicit VSETVLI or VSETIVLI, update our state.
@@ -1050,6 +1052,8 @@
         if (needVSETVLI(NewInfo, BlockInfo[MBB.getNumber()].Pred) &&
             needVSETVLIPHI(NewInfo, MBB)) {
           insertVSETVLI(MBB, MI, NewInfo, BlockInfo[MBB.getNumber()].Pred);
+          if (isScalarMoveInstr(MI))
+            ScalarMoveVSETVLI = MI.getPrevNode();
           CurInfo = NewInfo;
         }
       } else {
@@ -1085,8 +1089,26 @@
               NeedInsertVSETVLI = false;
             }
           }
-          if (NeedInsertVSETVLI)
+          if (ScalarMoveVSETVLI) {
+            if (NewInfo.hasAVLImm() &&
+                ((NewInfo.hasNonZeroAVL() && CurInfo.hasNonZeroAVL()) ||
+                 (CurInfo.hasZeroAVL() && CurInfo.hasZeroAVL())) &&
+                NewInfo.hasSameSEW(CurInfo) && NewInfo.hasSamePolicy(CurInfo)) {
+              // Because VSETVLI from ScalarMove don't care LMUL and non-zero
+              // AVL, so we can use new VSETVLI to instead old VSETVLI.
+              insertVSETVLI(MBB, *ScalarMoveVSETVLI, NewInfo, CurInfo);
+              ScalarMoveVSETVLI->removeFromParent();
+              NeedInsertVSETVLI = false;
+            }
+          }
+          if (NeedInsertVSETVLI) {
             insertVSETVLI(MBB, MI, NewInfo, CurInfo);
+            if (isScalarMoveInstr(MI))
+              ScalarMoveVSETVLI = MI.getPrevNode();
+            else
+              ScalarMoveVSETVLI = nullptr;
+          }
+
           CurInfo = NewInfo;
         }
       }
@@ -1099,6 +1121,7 @@
         MI.modifiesRegister(RISCV::VTYPE)) {
       CurInfo = VSETVLIInfo::getUnknown();
       PrevVSETVLIMI = nullptr;
+      ScalarMoveVSETVLI = nullptr;
     }
 
     // If we reach the end of the block and our current info doesn't match the
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
@@ -500,9 +500,8 @@
 ; RV32-NEXT:    li a1, 3
 ; RV32-NEXT:    sb a1, 8(a0)
 ; RV32-NEXT:    li a1, 73
-; RV32-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
-; RV32-NEXT:    vmv.s.x v0, a1
 ; RV32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; RV32-NEXT:    vmv.s.x v0, a1
 ; RV32-NEXT:    vmv.v.i v9, 2
 ; RV32-NEXT:    li a1, 36
 ; RV32-NEXT:    vmv.s.x v8, a1
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
@@ -376,9 +376,8 @@
 ; CHECK-LABEL: splat_ve2_we0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a0, 66
-; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vrgather.vi v10, v8, 2
 ; CHECK-NEXT:    vrgather.vi v10, v9, 0, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v10
@@ -410,9 +409,8 @@
 ; CHECK-LABEL: splat_ve2_we0_ins_i0we4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a0, 67
-; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vrgather.vi v10, v8, 2
 ; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, mu
 ; CHECK-NEXT:    vmv.v.i v8, 4
@@ -466,9 +464,8 @@
 ; CHECK-NEXT:    vsetivli zero, 3, e8, mf2, tu, mu
 ; CHECK-NEXT:    vslideup.vi v11, v10, 2
 ; CHECK-NEXT:    li a0, 70
-; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT:    vmv.s.x v0, a0
 ; CHECK-NEXT:    vrgather.vi v10, v8, 2
 ; CHECK-NEXT:    vrgather.vv v10, v9, v11, v0.t
 ; CHECK-NEXT:    vmv1r.v v8, v10
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
@@ -954,10 +954,9 @@
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, mu
 ; CHECK-NEXT:    vmv.v.i v11, 0
 ; CHECK-NEXT:    lui a1, 1048568
-; CHECK-NEXT:    vsetvli zero, zero, e16, m1, tu, mu
-; CHECK-NEXT:    vmv.v.i v12, 0
-; CHECK-NEXT:    vmv.s.x v12, a1
 ; CHECK-NEXT:    vsetivli zero, 7, e16, m1, tu, mu
+; CHECK-NEXT:    vmv1r.v v12, v11
+; CHECK-NEXT:    vmv.s.x v12, a1
 ; CHECK-NEXT:    vslideup.vi v11, v9, 6
 ; CHECK-NEXT:    vsetivli zero, 8, e16, m1, ta, mu
 ; CHECK-NEXT:    lui a1, %hi(.LCPI53_0)
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
@@ -481,9 +481,8 @@
 ; CHECK-LABEL: buildvec_mask_nonconst_v4i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a2, 3
-; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT:    vmv.s.x v0, a2
 ; CHECK-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
+; CHECK-NEXT:    vmv.s.x v0, a2
 ; CHECK-NEXT:    vmv.v.x v8, a1
 ; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; CHECK-NEXT:    vand.vi v8, v8, 1
@@ -493,9 +492,8 @@
 ; RV32-ELEN32-LABEL: buildvec_mask_nonconst_v4i1:
 ; RV32-ELEN32:       # %bb.0:
 ; RV32-ELEN32-NEXT:    li a2, 3
-; RV32-ELEN32-NEXT:    vsetivli zero, 1, e8, mf4, ta, mu
-; RV32-ELEN32-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN32-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
+; RV32-ELEN32-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN32-NEXT:    vmv.v.x v8, a1
 ; RV32-ELEN32-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32-ELEN32-NEXT:    vand.vi v8, v8, 1
@@ -505,9 +503,8 @@
 ; RV64-ELEN32-LABEL: buildvec_mask_nonconst_v4i1:
 ; RV64-ELEN32:       # %bb.0:
 ; RV64-ELEN32-NEXT:    li a2, 3
-; RV64-ELEN32-NEXT:    vsetivli zero, 1, e8, mf4, ta, mu
-; RV64-ELEN32-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN32-NEXT:    vsetivli zero, 4, e8, mf4, ta, mu
+; RV64-ELEN32-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN32-NEXT:    vmv.v.x v8, a1
 ; RV64-ELEN32-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV64-ELEN32-NEXT:    vand.vi v8, v8, 1
@@ -517,9 +514,8 @@
 ; RV32-ELEN16-LABEL: buildvec_mask_nonconst_v4i1:
 ; RV32-ELEN16:       # %bb.0:
 ; RV32-ELEN16-NEXT:    li a2, 3
-; RV32-ELEN16-NEXT:    vsetivli zero, 1, e8, mf2, ta, mu
-; RV32-ELEN16-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN16-NEXT:    vsetivli zero, 4, e8, mf2, ta, mu
+; RV32-ELEN16-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN16-NEXT:    vmv.v.x v8, a1
 ; RV32-ELEN16-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32-ELEN16-NEXT:    vand.vi v8, v8, 1
@@ -529,9 +525,8 @@
 ; RV64-ELEN16-LABEL: buildvec_mask_nonconst_v4i1:
 ; RV64-ELEN16:       # %bb.0:
 ; RV64-ELEN16-NEXT:    li a2, 3
-; RV64-ELEN16-NEXT:    vsetivli zero, 1, e8, mf2, ta, mu
-; RV64-ELEN16-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN16-NEXT:    vsetivli zero, 4, e8, mf2, ta, mu
+; RV64-ELEN16-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN16-NEXT:    vmv.v.x v8, a1
 ; RV64-ELEN16-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV64-ELEN16-NEXT:    vand.vi v8, v8, 1
@@ -541,9 +536,8 @@
 ; RV32-ELEN8-LABEL: buildvec_mask_nonconst_v4i1:
 ; RV32-ELEN8:       # %bb.0:
 ; RV32-ELEN8-NEXT:    li a2, 3
-; RV32-ELEN8-NEXT:    vsetivli zero, 1, e8, m1, ta, mu
-; RV32-ELEN8-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN8-NEXT:    vsetivli zero, 4, e8, m1, ta, mu
+; RV32-ELEN8-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN8-NEXT:    vmv.v.x v8, a1
 ; RV32-ELEN8-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32-ELEN8-NEXT:    vand.vi v8, v8, 1
@@ -553,9 +547,8 @@
 ; RV64-ELEN8-LABEL: buildvec_mask_nonconst_v4i1:
 ; RV64-ELEN8:       # %bb.0:
 ; RV64-ELEN8-NEXT:    li a2, 3
-; RV64-ELEN8-NEXT:    vsetivli zero, 1, e8, m1, ta, mu
-; RV64-ELEN8-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN8-NEXT:    vsetivli zero, 4, e8, m1, ta, mu
+; RV64-ELEN8-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN8-NEXT:    vmv.v.x v8, a1
 ; RV64-ELEN8-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV64-ELEN8-NEXT:    vand.vi v8, v8, 1
@@ -870,9 +863,8 @@
 ; CHECK-LABEL: buildvec_mask_nonconst_v8i1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    li a2, 19
-; CHECK-NEXT:    vsetivli zero, 1, e8, mf8, ta, mu
-; CHECK-NEXT:    vmv.s.x v0, a2
 ; CHECK-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; CHECK-NEXT:    vmv.s.x v0, a2
 ; CHECK-NEXT:    vmv.v.x v8, a1
 ; CHECK-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; CHECK-NEXT:    vand.vi v8, v8, 1
@@ -882,9 +874,8 @@
 ; RV32-ELEN32-LABEL: buildvec_mask_nonconst_v8i1:
 ; RV32-ELEN32:       # %bb.0:
 ; RV32-ELEN32-NEXT:    li a2, 19
-; RV32-ELEN32-NEXT:    vsetivli zero, 1, e8, mf4, ta, mu
-; RV32-ELEN32-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; RV32-ELEN32-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN32-NEXT:    vmv.v.x v8, a1
 ; RV32-ELEN32-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32-ELEN32-NEXT:    vand.vi v8, v8, 1
@@ -894,9 +885,8 @@
 ; RV64-ELEN32-LABEL: buildvec_mask_nonconst_v8i1:
 ; RV64-ELEN32:       # %bb.0:
 ; RV64-ELEN32-NEXT:    li a2, 19
-; RV64-ELEN32-NEXT:    vsetivli zero, 1, e8, mf4, ta, mu
-; RV64-ELEN32-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN32-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; RV64-ELEN32-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN32-NEXT:    vmv.v.x v8, a1
 ; RV64-ELEN32-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV64-ELEN32-NEXT:    vand.vi v8, v8, 1
@@ -906,9 +896,8 @@
 ; RV32-ELEN16-LABEL: buildvec_mask_nonconst_v8i1:
 ; RV32-ELEN16:       # %bb.0:
 ; RV32-ELEN16-NEXT:    li a2, 19
-; RV32-ELEN16-NEXT:    vsetivli zero, 1, e8, mf2, ta, mu
-; RV32-ELEN16-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN16-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; RV32-ELEN16-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN16-NEXT:    vmv.v.x v8, a1
 ; RV32-ELEN16-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32-ELEN16-NEXT:    vand.vi v8, v8, 1
@@ -918,9 +907,8 @@
 ; RV64-ELEN16-LABEL: buildvec_mask_nonconst_v8i1:
 ; RV64-ELEN16:       # %bb.0:
 ; RV64-ELEN16-NEXT:    li a2, 19
-; RV64-ELEN16-NEXT:    vsetivli zero, 1, e8, mf2, ta, mu
-; RV64-ELEN16-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN16-NEXT:    vsetivli zero, 8, e8, mf2, ta, mu
+; RV64-ELEN16-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN16-NEXT:    vmv.v.x v8, a1
 ; RV64-ELEN16-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV64-ELEN16-NEXT:    vand.vi v8, v8, 1
@@ -930,9 +918,8 @@
 ; RV32-ELEN8-LABEL: buildvec_mask_nonconst_v8i1:
 ; RV32-ELEN8:       # %bb.0:
 ; RV32-ELEN8-NEXT:    li a2, 19
-; RV32-ELEN8-NEXT:    vsetivli zero, 1, e8, m1, ta, mu
-; RV32-ELEN8-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN8-NEXT:    vsetivli zero, 8, e8, m1, ta, mu
+; RV32-ELEN8-NEXT:    vmv.s.x v0, a2
 ; RV32-ELEN8-NEXT:    vmv.v.x v8, a1
 ; RV32-ELEN8-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV32-ELEN8-NEXT:    vand.vi v8, v8, 1
@@ -942,9 +929,8 @@
 ; RV64-ELEN8-LABEL: buildvec_mask_nonconst_v8i1:
 ; RV64-ELEN8:       # %bb.0:
 ; RV64-ELEN8-NEXT:    li a2, 19
-; RV64-ELEN8-NEXT:    vsetivli zero, 1, e8, m1, ta, mu
-; RV64-ELEN8-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN8-NEXT:    vsetivli zero, 8, e8, m1, ta, mu
+; RV64-ELEN8-NEXT:    vmv.s.x v0, a2
 ; RV64-ELEN8-NEXT:    vmv.v.x v8, a1
 ; RV64-ELEN8-NEXT:    vmerge.vxm v8, v8, a0, v0
 ; RV64-ELEN8-NEXT:    vand.vi v8, v8, 1