diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -54789,8 +54789,9 @@ // In any sort of PIC mode addresses need to be computed at runtime by // adding in a register or some sort of table lookup. These can't - // be used as immediates. - if (Subtarget.isPICStyleGOT() || Subtarget.isPICStyleStubPIC()) + // be used as immediates. BlockAddresses are fine though. + if ((Subtarget.isPICStyleGOT() || Subtarget.isPICStyleStubPIC()) && + !isa(Op)) return; // If we are in non-pic codegen mode, we allow the address of a global (with diff --git a/llvm/test/CodeGen/X86/asm-block-labels-pic.ll b/llvm/test/CodeGen/X86/asm-block-labels-pic.ll new file mode 100644 --- /dev/null +++ b/llvm/test/CodeGen/X86/asm-block-labels-pic.ll @@ -0,0 +1,41 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc --relocation-model=pic %s -o - | FileCheck %s +target triple = "i386-unknown-linux-gnu" + +; The intent of this test is to ensure that we handle blockaddress' correctly +; with "i" constraints for -m32 -fPIC. + +define void @x() { +; CHECK-LABEL: x: +; CHECK: # %bb.0: +; CHECK-NEXT: #APP +; CHECK-NEXT: # .Ltmp0 +; CHECK-EMPTY: +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: # %bb.2: # %return +; CHECK-NEXT: retl +; CHECK-NEXT: .Ltmp0: # Block address taken +; CHECK-NEXT: .LBB0_1: # %overflow +; CHECK-NEXT: retl + callbr void asm "# ${0:l}\0A", "i"(i8* blockaddress(@x, %overflow)) + to label %return [label %overflow] + +overflow: + br label %return + +return: + ret void +} + +; Test unusual case of blockaddress from @x in @y's asm. +define void @y() { +; CHECK-LABEL: y: +; CHECK: # %bb.0: +; CHECK-NEXT: #APP +; CHECK-NEXT: # .Ltmp0 +; CHECK-EMPTY: +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: retl + call void asm "# ${0:l}\0A", "i"(i8* blockaddress(@x, %overflow)) + ret void +}