diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td b/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td --- a/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td +++ b/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td @@ -256,34 +256,34 @@ } // FmtBSTR_W -// +// class FmtBSTR_W op, dag outs, dag ins, string asmstr, list pattern = []> : LAInst { - bits<5> msb; - bits<5> lsb; + bits<5> msbw; + bits<5> lsbw; bits<5> rj; bits<5> rd; let Inst{31-21} = op{11-1}; - let Inst{20-16} = msb; + let Inst{20-16} = msbw; let Inst{15} = op{0}; - let Inst{14-10} = lsb; + let Inst{14-10} = lsbw; let Inst{9-5} = rj; let Inst{4-0} = rd; } // FmtBSTR_D -// +// class FmtBSTR_D op, dag outs, dag ins, string asmstr, list pattern = []> : LAInst { - bits<6> msb; - bits<6> lsb; + bits<6> msbd; + bits<6> lsbd; bits<5> rj; bits<5> rd; let Inst{31-22} = op; - let Inst{21-16} = msb; - let Inst{15-10} = lsb; + let Inst{21-16} = msbd; + let Inst{15-10} = lsbd; let Inst{9-5} = rj; let Inst{4-0} = rd; } diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td --- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td +++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td @@ -86,13 +86,6 @@ : Fmt1RI20; -class ALU_BSTRW op, string opstr, Operand ImmOpnd> - : FmtBSTR_W; -class ALU_BSTRD op, string opstr, Operand ImmOpnd> - : FmtBSTR_D; - class MISC_I15 op, string opstr> : FmtI15; @@ -150,12 +143,12 @@ let mayLoad = 1 in class LLBase op, string opstr> - : Fmt2RI14; let mayStore = 1, Constraints = "$rd = $dst" in class SCBase op, string opstr> - : Fmt2RI14; //===----------------------------------------------------------------------===// @@ -214,8 +207,14 @@ def REVB_2H : ALU_2R<0b0000000000000000001100, "revb.2h">; def BITREV_4B : ALU_2R<0b0000000000000000010010, "bitrev.4b">; def BITREV_W : ALU_2R<0b0000000000000000010100, "bitrev.w">; -def BSTRINS_W : ALU_BSTRW<0b000000000110, "bstrins.w", uimm5>; -def BSTRPICK_W : ALU_BSTRW<0b000000000111, "bstrpick.w", uimm5>; +let Constraints = "$rd = $dst" in { +def BSTRINS_W : FmtBSTR_W<0b000000000110, (outs GPR:$dst), + (ins GPR:$rd, GPR:$rj, uimm5:$msbw, uimm5:$lsbw), + "bstrins.w\t$rd, $rj, $msbw, $lsbw">; +} +def BSTRPICK_W : FmtBSTR_W<0b000000000111, (outs GPR:$rd), + (ins GPR:$rj, uimm5:$msbw, uimm5:$lsbw), + "bstrpick.w\t$rd, $rj, $msbw, $lsbw">; def MASKEQZ : ALU_3R<0b00000000000100110, "maskeqz">; def MASKNEZ : ALU_3R<0b00000000000100111, "masknez">; @@ -309,8 +308,14 @@ def REVH_D : ALU_2R<0b0000000000000000010001, "revh.d">; def BITREV_8B : ALU_2R<0b0000000000000000010011, "bitrev.8b">; def BITREV_D : ALU_2R<0b0000000000000000010101, "bitrev.d">; -def BSTRINS_D : ALU_BSTRD<0b0000000010, "bstrins.d", uimm6>; -def BSTRPICK_D : ALU_BSTRD<0b0000000011, "bstrpick.d", uimm6>; +let Constraints = "$rd = $dst" in { +def BSTRINS_D : FmtBSTR_D<0b0000000010, (outs GPR:$dst), + (ins GPR:$rd, GPR:$rj, uimm6:$msbd, uimm6:$lsbd), + "bstrins.d\t$rd, $rj, $msbd, $lsbd">; +} +def BSTRPICK_D : FmtBSTR_D<0b0000000011, (outs GPR:$rd), + (ins GPR:$rj, uimm6:$msbd, uimm6:$lsbd), + "bstrpick.d\t$rd, $rj, $msbd, $lsbd">; // Common Memory Access Instructions for 64-bits def LD_WU : LOAD_2RI12<0b0010101010, "ld.wu">; diff --git a/llvm/test/CodeGen/LoongArch/misc.mir b/llvm/test/CodeGen/LoongArch/misc.mir --- a/llvm/test/CodeGen/LoongArch/misc.mir +++ b/llvm/test/CodeGen/LoongArch/misc.mir @@ -94,7 +94,7 @@ name: test_BSTRINS_W body: | bb.0: - $r4 = BSTRINS_W $r5, 7, 2 + $r4 = BSTRINS_W $r4, $r5, 7, 2 ... --- # CHECK-LABEL: test_BSTRPICK_W: @@ -122,7 +122,7 @@ name: test_BSTRINS_D body: | bb.0: - $r4 = BSTRINS_D $r5, 7, 2 + $r4 = BSTRINS_D $r4, $r5, 7, 2 ... --- # CHECK-LABEL: test_BSTRPICK_D: