diff --git a/llvm/lib/Target/VE/VEInstrPatternsVec.td b/llvm/lib/Target/VE/VEInstrPatternsVec.td
--- a/llvm/lib/Target/VE/VEInstrPatternsVec.td
+++ b/llvm/lib/Target/VE/VEInstrPatternsVec.td
@@ -105,3 +105,10 @@
 defm : vbrd_elem64<v512f32, i64, simm7, LO7>;
 defm : vbrd_elem64<v512i32, f64, simm7fp, LO7FP>;
 defm : vbrd_elem64<v512f32, f64, simm7fp, LO7FP>;
+
+class Mask_Binary<ValueType MaskVT, SDPatternOperator MaskOp, string InstName> :
+  Pat<(MaskVT (MaskOp MaskVT:$ma, MaskVT:$mb)), (!cast<Instruction>(InstName#"mm") $ma, $mb)>;
+
+def: Mask_Binary<v256i1, and, "ANDM">;
+def: Mask_Binary<v256i1, or,  "ORM">;
+def: Mask_Binary<v256i1, xor, "XORM">;
diff --git a/llvm/test/CodeGen/VE/Vector/mask_binary.ll b/llvm/test/CodeGen/VE/Vector/mask_binary.ll
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/VE/Vector/mask_binary.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
+
+; Function Attrs: nounwind
+define fastcc <256 x i1> @and_mm_v256i1(<256 x i1> %x, <256 x i1> %y) {
+; CHECK-LABEL: and_mm_v256i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    andm %vm1, %vm1, %vm2
+; CHECK-NEXT:    b.l.t (, %s10)
+  %z = and <256 x i1> %x, %y
+  ret <256 x i1> %z
+}
+
+; Function Attrs: nounwind
+define fastcc <256 x i1> @or_mm_v256i1(<256 x i1> %x, <256 x i1> %y) {
+; CHECK-LABEL: or_mm_v256i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    orm %vm1, %vm1, %vm2
+; CHECK-NEXT:    b.l.t (, %s10)
+  %z = or <256 x i1> %x, %y
+  ret <256 x i1> %z
+}
+
+; Function Attrs: nounwind
+define fastcc <256 x i1> @xor_mm_v256i1(<256 x i1> %x, <256 x i1> %y) {
+; CHECK-LABEL: xor_mm_v256i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorm %vm1, %vm1, %vm2
+; CHECK-NEXT:    b.l.t (, %s10)
+  %z = xor <256 x i1> %x, %y
+  ret <256 x i1> %z
+}
+