Index: llvm/lib/Target/AMDGPU/SIRegisterInfo.h
===================================================================
--- llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -64,6 +64,8 @@
   MCRegister reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
+  bool isAsmClobberable(const MachineFunction &MF,
+                        MCRegister PhysReg) const override;
 
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
   const MCPhysReg *getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
Index: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -690,6 +690,11 @@
   return Reserved;
 }
 
+bool SIRegisterInfo::isAsmClobberable(const MachineFunction &MF,
+                                      MCRegister PhysReg) const {
+  return !MF.getRegInfo().isReserved(PhysReg);
+}
+
 bool SIRegisterInfo::shouldRealignStack(const MachineFunction &MF) const {
   const SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
   // On entry, the base address is 0, so it can't possibly need any more
Index: llvm/test/CodeGen/AMDGPU/inline-asm-reserved-regs.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/inline-asm-reserved-regs.ll
@@ -0,0 +1,52 @@
+; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs -o /dev/null 2>&1 %s | FileCheck -check-prefix=ERR %s
+
+; ERR: warning: inline asm clobber list contains reserved registers: VGPR42
+; ERR: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
+define amdgpu_kernel void @clobber_occupancy_limited_vgpr() #0 {
+entry:
+  call void asm sideeffect "; clobber $0", "~{v42}"()
+  ret void
+}
+
+; ERR: warning: inline asm clobber list contains reserved registers: VGPR42_VGPR43
+; ERR: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
+define amdgpu_kernel void @clobber_occupancy_limited_vgpr64() #0 {
+entry:
+  call void asm sideeffect "; clobber $0", "~{v[42:43]}"()
+  ret void
+}
+
+; ERR: warning: inline asm clobber list contains reserved registers: M0
+; ERR: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
+define amdgpu_kernel void @clobber_m0() {
+entry:
+  call void asm sideeffect "; clobber $0", "~{m0}"()
+  ret void
+}
+
+; ERR: warning: inline asm clobber list contains reserved registers: EXEC
+; ERR: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
+define amdgpu_kernel void @clobber_exec() {
+entry:
+  call void asm sideeffect "; clobber $0", "~{exec}"()
+  ret void
+}
+
+; ERR: warning: inline asm clobber list contains reserved registers: EXEC_LO
+; ERR: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
+define amdgpu_kernel void @clobber_exec_lo() {
+entry:
+  call void asm sideeffect "; clobber $0", "~{exec_lo}"()
+  ret void
+}
+
+; FIXME: This should warn too
+; ERR-NOT: warning
+define amdgpu_kernel void @def_exec(i64 addrspace(1)* %ptr) {
+entry:
+  %exec = call i64 asm sideeffect "; def $0", "={exec}"()
+  store i64 %exec, i64 addrspace(1)* %ptr
+  ret void
+}
+
+attributes #0 = { "amdgpu-waves-per-eu"="10,10" }