diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -82,10 +82,6 @@
                        cl::init(false), cl::Hidden,
                        cl::desc("Restrict remat for statepoint operands"));
 
-static cl::opt<bool> DisableSpillOtherClass("disable-spill-other-class",
-                                      cl::init(false), cl::Hidden,
-                                      cl::desc("Disable spilling to other register classes"));
-
 namespace {
 
 class HoistSpillHelper : private LiveRangeEdit::Delegate {
@@ -251,8 +247,8 @@
 
 void Spiller::anchor() {}
 
-Spiller *llvm::createInlineSpiller(MachineFunctionPass &pass,
-                                   MachineFunction &mf,
+Spiller *llvm::createInlineSpiller(MachineFunctionPass &Pass,
+                                   MachineFunction &MF,
                                    VirtRegMap &VRM,
                                    const RegisterClassInfo &RegClassInfo,
                                    LiveRegMatrix &Matrix) {
@@ -1194,9 +1190,6 @@
 }
 
 bool InlineSpiller::spillToOtherClass() {
-  if (DisableSpillOtherClass)
-    return false;
-
   const TargetRegisterClass* SpillRC = TRI.spillToOtherClass(MRI, Original);
   if (SpillRC == nullptr)
     return false;
diff --git a/llvm/lib/Target/X86/X86FrameLowering.cpp b/llvm/lib/Target/X86/X86FrameLowering.cpp
--- a/llvm/lib/Target/X86/X86FrameLowering.cpp
+++ b/llvm/lib/Target/X86/X86FrameLowering.cpp
@@ -2374,24 +2374,26 @@
     if (!X86::GR64RegClass.contains(Reg) && !X86::GR32RegClass.contains(Reg))
       continue;
 
-    // Try to spill to XMM register.
-    if (Reg != X86::RBP && X86::GR64RegClass.contains(Reg) && !MF.callsUnwindInit()) {
-      const MachineRegisterInfo &MRI = MF.getRegInfo();
-      MCRegister SpillReg = MCRegister::NoRegister;
-      for (unsigned NumRegs = X86::FR64RegClass.getNumRegs();
-           lastUsedXmm < NumRegs; lastUsedXmm++) {
-        MCRegister Candidate = X86::FR64RegClass.getRegister(lastUsedXmm);
-        if (!MRI.isPhysRegUsed(Candidate)) {
-          SpillReg = Candidate;
-          lastUsedXmm++;
-          break;
+    if (this->TRI->getSpillToSSE()) {
+      // Try to spill to XMM register.
+      if (Reg != X86::RBP && X86::GR64RegClass.contains(Reg) && !MF.callsUnwindInit()) {
+        const MachineRegisterInfo &MRI = MF.getRegInfo();
+        MCRegister SpillReg = MCRegister::NoRegister;
+        for (unsigned NumRegs = X86::FR64RegClass.getNumRegs();
+             lastUsedXmm < NumRegs; lastUsedXmm++) {
+          MCRegister Candidate = X86::FR64RegClass.getRegister(lastUsedXmm);
+          if (!MRI.isPhysRegUsed(Candidate)) {
+            SpillReg = Candidate;
+            lastUsedXmm++;
+            break;
+          }
+        }
+        if (SpillReg != MCRegister::NoRegister) {
+          LLVM_DEBUG(dbgs() << "Save " << printReg(Reg, TRI)
+                     << " by copy to " << printReg(SpillReg, TRI) << '\n');
+          CSI[i - 1].setDstReg(SpillReg);
+          continue;
         }
-      }
-      if (SpillReg != MCRegister::NoRegister) {
-        LLVM_DEBUG(dbgs() << "Save " << printReg(Reg, TRI)
-                   << " by copy to " << printReg(SpillReg, TRI) << '\n');
-        CSI[i - 1].setDstReg(SpillReg);
-        continue;
       }
     }
 
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.h b/llvm/lib/Target/X86/X86RegisterInfo.h
--- a/llvm/lib/Target/X86/X86RegisterInfo.h
+++ b/llvm/lib/Target/X86/X86RegisterInfo.h
@@ -48,6 +48,8 @@
   /// variable size stack objects.
   unsigned BasePtr;
 
+  bool SpillToSSE;
+
 public:
   explicit X86RegisterInfo(const Triple &TT);
 
@@ -144,6 +146,7 @@
   Register getFramePtr() const { return FramePtr; }
   // FIXME: Move to FrameInfok
   unsigned getSlotSize() const { return SlotSize; }
+  bool getSpillToSSE() const { return SpillToSSE; }
 
   bool getRegAllocationHints(Register VirtReg, ArrayRef<MCPhysReg> Order,
                              SmallVectorImpl<MCPhysReg> &Hints,
diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
--- a/llvm/lib/Target/X86/X86RegisterInfo.cpp
+++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -43,11 +43,16 @@
 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
           cl::desc("Enable use of a base pointer for complex stack frames"));
 
+static cl::opt<bool>
+EnableSpillToSSE("x86-spill-to-sse", cl::Hidden, cl::ZeroOrMore,
+          cl::desc("Enable spilling from GP to SSE registers"));
+
 X86RegisterInfo::X86RegisterInfo(const Triple &TT)
     : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
                          X86_MC::getDwarfRegFlavour(TT, false),
                          X86_MC::getDwarfRegFlavour(TT, true),
-                         (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
+                         (TT.isArch64Bit() ? X86::RIP : X86::EIP)),
+      SpillToSSE(EnableSpillToSSE) {
   X86_MC::initLLVMToSEHAndCVRegMapping(this);
 
   // Cache some information.
@@ -935,6 +940,8 @@
 }
 
 const TargetRegisterClass* X86RegisterInfo::spillToOtherClass(const MachineRegisterInfo& MRI, Register Reg) const {
+  if (!SpillToSSE)
+    return nullptr;
   unsigned RCId = MRI.getRegClass(Reg)->getID();
   // TODO: We should somehow compute a list of relevant classes
   // (all classes that only have RxX registers as members)