diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -15422,6 +15422,12 @@ N->getOperand(0)->getOpcode() == ISD::SETCC); const SDValue SetCC = N->getOperand(0); + const SDValue CCOp0 = SetCC.getOperand(0); + const SDValue CCOp1 = SetCC.getOperand(1); + if (!CCOp0->getValueType(0).isInteger() || + !CCOp1->getValueType(0).isInteger()) + return SDValue(); + ISD::CondCode Code = cast(SetCC->getOperand(2).getNode())->get(); @@ -15431,9 +15437,9 @@ if (isCheapToExtend(SetCC.getOperand(0)) && isCheapToExtend(SetCC.getOperand(1))) { const SDValue Ext1 = - DAG.getNode(ExtType, SDLoc(N), N->getValueType(0), SetCC.getOperand(0)); + DAG.getNode(ExtType, SDLoc(N), N->getValueType(0), CCOp0); const SDValue Ext2 = - DAG.getNode(ExtType, SDLoc(N), N->getValueType(0), SetCC.getOperand(1)); + DAG.getNode(ExtType, SDLoc(N), N->getValueType(0), CCOp1); return DAG.getSetCC( SDLoc(SetCC), N->getValueType(0), Ext1, Ext2, diff --git a/llvm/test/CodeGen/AArch64/select_cc.ll b/llvm/test/CodeGen/AArch64/select_cc.ll --- a/llvm/test/CodeGen/AArch64/select_cc.ll +++ b/llvm/test/CodeGen/AArch64/select_cc.ll @@ -52,3 +52,19 @@ %sel = select i1 %cc, i64 0, i64 4 ret i64 %sel } + +define <2 x double> @select_olt_load_cmp(<2 x double> %a, <2 x float>* %src) { +; CHECK-LABEL: select_olt_load_cmp: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: movi d1, #0000000000000000 +; CHECK-NEXT: ldr d2, [x0] +; CHECK-NEXT: fcmgt v1.2s, v2.2s, v1.2s +; CHECK-NEXT: sshll v1.2d, v1.2s, #0 +; CHECK-NEXT: and v0.16b, v0.16b, v1.16b +; CHECK-NEXT: ret +entry: + %l = load <2 x float>, <2 x float>* %src, align 4 + %cmp = fcmp olt <2 x float> zeroinitializer, %l + %sel = select <2 x i1> %cmp, <2 x double> %a, <2 x double> zeroinitializer + ret <2 x double> %sel +}