diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1206,19 +1206,6 @@
                 list<SubtargetFeature> TuneFeatures>
  : ProcessorModel<Name, Model, Features, TuneFeatures>;
 
-// NOTE: CMPXCHG8B is here for legacy compatibility so that it is only disabled
-// if i386/i486 is specifically requested.
-// NOTE: 64Bit is here as "generic" is the default llc CPU. The X86Subtarget
-// constructor checks that any CPU used in 64-bit mode has Feature64Bit enabled.
-// It has no effect on code generation.
-def : ProcModel<"generic", SandyBridgeModel,
-                [FeatureX87, FeatureCMPXCHG8B, Feature64Bit],
-                [TuningSlow3OpsLEA,
-                 TuningSlowDivide64,
-                 TuningSlowIncDec,
-                 TuningMacroFusion,
-                 TuningInsertVZEROUPPER]>;
-
 def : Proc<"i386",            [FeatureX87],
                               [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
 def : Proc<"i486",            [FeatureX87],
@@ -1495,6 +1482,14 @@
                                FeatureSSE1, FeatureFXSR, FeatureCMOV],
                               [TuningSlowUAMem16, TuningInsertVZEROUPPER]>;
 
+// NOTE: Here "generic" is used for "-mtune" which represents the most common
+//       processors at the time. We set the tuning the same as "x86-64-v3" to
+//       better match with GCC, while still using the least features to provide
+//       backward compatiblity.
+def : ProcModel<"generic", HaswellModel,
+                [FeatureX87, FeatureCMPXCHG8B, Feature64Bit],
+                ProcessorFeatures.HSWTuning>;
+
 // We also provide a generic 64-bit specific x86 processor model which tries to
 // be good for modern chips without enabling instruction set encodings past the
 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
diff --git a/llvm/test/CodeGen/X86/rdtsc-upgrade.ll b/llvm/test/CodeGen/X86/rdtsc-upgrade.ll
--- a/llvm/test/CodeGen/X86/rdtsc-upgrade.ll
+++ b/llvm/test/CodeGen/X86/rdtsc-upgrade.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=generic | FileCheck %s --check-prefix=X86
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=generic | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefix=X64
 
 ; Verify upgrading of the old form of the rdtscp intrinsic.
 
diff --git a/llvm/test/CodeGen/X86/rdtsc.ll b/llvm/test/CodeGen/X86/rdtsc.ll
--- a/llvm/test/CodeGen/X86/rdtsc.ll
+++ b/llvm/test/CodeGen/X86/rdtsc.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=generic | FileCheck %s --check-prefix=X86
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=generic | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefix=X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefix=X64
 
 ; Verify that we correctly lower ISD::READCYCLECOUNTER.
 
diff --git a/llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll b/llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll
--- a/llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll
+++ b/llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll
@@ -1,10 +1,10 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mcpu=generic -mtriple=i686-linux -verify-machineinstrs | FileCheck %s -check-prefix=X86
-; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux -verify-machineinstrs | FileCheck %s -check-prefix=X64
-; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux-gnux32 -verify-machineinstrs | FileCheck %s -check-prefix=X32ABI
-; RUN: llc < %s -mcpu=generic -mtriple=i686-linux -filetype=obj
-; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux -filetype=obj
-; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux-gnux32 -filetype=obj
+; RUN: llc < %s -mcpu=x86-64 -mtriple=i686-linux -verify-machineinstrs | FileCheck %s -check-prefix=X86
+; RUN: llc < %s -mcpu=x86-64 -mtriple=x86_64-linux -verify-machineinstrs | FileCheck %s -check-prefix=X64
+; RUN: llc < %s -mcpu=x86-64 -mtriple=x86_64-linux-gnux32 -verify-machineinstrs | FileCheck %s -check-prefix=X32ABI
+; RUN: llc < %s -mcpu=x86-64 -mtriple=i686-linux -filetype=obj
+; RUN: llc < %s -mcpu=x86-64 -mtriple=x86_64-linux -filetype=obj
+; RUN: llc < %s -mcpu=x86-64 -mtriple=x86_64-linux-gnux32 -filetype=obj
 
 ; Just to prevent the alloca from being optimized away
 declare void @dummy_use(i32*, i32)
diff --git a/llvm/test/CodeGen/X86/twoaddr-lea.ll b/llvm/test/CodeGen/X86/twoaddr-lea.ll
--- a/llvm/test/CodeGen/X86/twoaddr-lea.ll
+++ b/llvm/test/CodeGen/X86/twoaddr-lea.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mcpu=generic -mtriple=x86_64-apple-darwin | FileCheck %s
+; RUN: llc < %s -mcpu=x86-64 -mtriple=x86_64-apple-darwin | FileCheck %s
 
 ;; X's live range extends beyond the shift, so the register allocator
 ;; cannot coalesce it with Y.  Because of this, a copy needs to be
diff --git a/llvm/test/MC/X86/x86-directive-nops-errors.s b/llvm/test/MC/X86/x86-directive-nops-errors.s
--- a/llvm/test/MC/X86/x86-directive-nops-errors.s
+++ b/llvm/test/MC/X86/x86-directive-nops-errors.s
@@ -1,5 +1,5 @@
 # RUN: not llvm-mc -triple i386 %s -filetype=obj -o /dev/null 2>&1 | FileCheck --check-prefix=X86 %s
-# RUN: not llvm-mc -triple=x86_64 %s -filetype=obj -o /dev/null 2>&1 | FileCheck --check-prefix=X64 %s
+# RUN: not llvm-mc -triple=x86_64 -mcpu=x86-64 %s -filetype=obj -o /dev/null 2>&1 | FileCheck --check-prefix=X64 %s
 
 .nops 4, 3
 # X86: :[[@LINE-1]]:1: error: illegal NOP size 3.
diff --git a/llvm/test/tools/llvm-mca/X86/cv_fpo_directive_no_segfault.s b/llvm/test/tools/llvm-mca/X86/cv_fpo_directive_no_segfault.s
--- a/llvm/test/tools/llvm-mca/X86/cv_fpo_directive_no_segfault.s
+++ b/llvm/test/tools/llvm-mca/X86/cv_fpo_directive_no_segfault.s
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=generic -resource-pressure=false -instruction-info=false < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -resource-pressure=false -instruction-info=false < %s | FileCheck %s
 
 .cv_fpo_pushreg ebx
 add %eax, %eax