diff --git a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
--- a/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AVR/AVRExpandPseudoInsts.cpp
@@ -448,7 +448,7 @@
   auto MIBHI =
       buildMI(MBB, MBBI, AVR::NEGRd)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-          .addReg(DstHiReg, getKillRegState(DstIsKill));
+          .addReg(DstHiReg, RegState::Kill);
   // SREG is always implicitly dead
   MIBHI->getOperand(2).setIsDead();
 
@@ -1300,6 +1300,7 @@
   unsigned OpShift, OpCarry;
   Register DstReg = MI.getOperand(0).getReg();
   bool DstIsDead = MI.getOperand(0).isDead();
+  bool DstIsKill = MI.getOperand(1).isKill();
   OpShift = AVR::ADDRdRr;
   OpCarry = AVR::ADCRdRr;
 
@@ -1309,13 +1310,13 @@
   // Shift part
   buildMI(MBB, MBBI, OpShift)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg)
-      .addReg(DstReg);
+      .addReg(DstReg, RegState::Kill)
+      .addReg(DstReg, RegState::Kill);
 
   // Add the carry bit
   auto MIB = buildMI(MBB, MBBI, OpCarry)
                  .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-                 .addReg(DstReg)
+                 .addReg(DstReg, getKillRegState(DstIsKill))
                  .addReg(ZERO_REGISTER);
 
   // SREG is always implicitly killed
@@ -1368,13 +1369,13 @@
   // Low part
   buildMI(MBB, MBBI, OpLo)
       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstLoReg)
+      .addReg(DstLoReg, getKillRegState(DstIsKill))
       .addReg(DstLoReg, getKillRegState(DstIsKill));
 
   auto MIBHI =
       buildMI(MBB, MBBI, OpHi)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-          .addReg(DstHiReg)
+          .addReg(DstHiReg, getKillRegState(DstIsKill))
           .addReg(DstHiReg, getKillRegState(DstIsKill));
 
   if (ImpIsDead)
@@ -1424,16 +1425,16 @@
   // swap Rl
   buildMI(MBB, MBBI, AVR::SWAPRd)
       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstHiReg, getKillRegState(DstIsKill));
+      .addReg(DstHiReg, RegState::Kill);
   buildMI(MBB, MBBI, AVR::SWAPRd)
       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstLoReg, getKillRegState(DstIsKill));
+      .addReg(DstLoReg, RegState::Kill);
 
   // andi Rh, 0xf0
   auto MI0 =
       buildMI(MBB, MBBI, AVR::ANDIRdK)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-          .addReg(DstHiReg, getKillRegState(DstIsKill))
+          .addReg(DstHiReg, RegState::Kill)
           .addImm(0xf0);
   // SREG is implicitly dead.
   MI0->getOperand(3).setIsDead();
@@ -1442,7 +1443,7 @@
   auto MI1 =
       buildMI(MBB, MBBI, AVR::EORRdRr)
           .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-          .addReg(DstHiReg, getKillRegState(DstIsKill))
+          .addReg(DstHiReg, RegState::Kill)
           .addReg(DstLoReg);
   // SREG is implicitly dead.
   MI1->getOperand(3).setIsDead();
@@ -1513,7 +1514,7 @@
   // swap Rh
   buildMI(MBB, MBBI, AVR::SWAPRd)
       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstHiReg, getKillRegState(DstIsKill));
+      .addReg(DstHiReg, RegState::Kill);
 
   // andi Rh, 0xf0
   auto MI0 =
@@ -1622,16 +1623,16 @@
   // swap Rl
   buildMI(MBB, MBBI, AVR::SWAPRd)
       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstHiReg, getKillRegState(DstIsKill));
+      .addReg(DstHiReg, RegState::Kill);
   buildMI(MBB, MBBI, AVR::SWAPRd)
       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstLoReg, getKillRegState(DstIsKill));
+      .addReg(DstLoReg, RegState::Kill);
 
   // andi Rl, 0xf
   auto MI0 =
       buildMI(MBB, MBBI, AVR::ANDIRdK)
           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
-          .addReg(DstLoReg, getKillRegState(DstIsKill))
+          .addReg(DstLoReg, RegState::Kill)
           .addImm(0xf);
   // SREG is implicitly dead.
   MI0->getOperand(3).setIsDead();
@@ -1640,7 +1641,7 @@
   auto MI1 =
       buildMI(MBB, MBBI, AVR::EORRdRr)
           .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
-          .addReg(DstLoReg, getKillRegState(DstIsKill))
+          .addReg(DstLoReg, RegState::Kill)
           .addReg(DstHiReg);
   // SREG is implicitly dead.
   MI1->getOperand(3).setIsDead();
@@ -1711,7 +1712,7 @@
   // swap Rl
   buildMI(MBB, MBBI, AVR::SWAPRd)
       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstLoReg, getKillRegState(DstIsKill));
+      .addReg(DstLoReg, RegState::Kill);
 
   // andi Rl, 0xf
   auto MI0 =
@@ -1835,9 +1836,9 @@
 
   // Move the sign bit to the C flag.
   buildMI(MBB, MBBI, AVR::ADDRdRr)
-      .addReg(DstHiReg, RegState::Define, getDeadRegState(DstIsDead))
-      .addReg(DstHiReg, getKillRegState(DstIsKill) | getDeadRegState(DstIsDead))
-      .addReg(DstHiReg, getKillRegState(DstIsKill));
+      .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
+      .addReg(DstHiReg, RegState::Kill)
+      .addReg(DstHiReg, RegState::Kill);
 
   // Set upper byte to 0 or -1.
   auto MIBHI =
@@ -1878,14 +1879,14 @@
 
   buildMI(MBB, MBBI, AVR::RORRd)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg, getKillRegState(DstIsKill))
+      .addReg(DstReg, RegState::Kill)
       ->getOperand(3)
       .setIsUndef(true);
 
   buildMI(MBB, MBBI, AVR::EORRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg, getKillRegState(DstIsKill))
-      .addReg(DstReg, getKillRegState(DstIsKill));
+      .addReg(DstReg, RegState::Kill)
+      .addReg(DstReg, RegState::Kill);
 
   auto MIRRC =
       buildMI(MBB, MBBI, AVR::RORRd)
@@ -1928,15 +1929,15 @@
 
   buildMI(MBB, MBBI, AVR::ADCRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg, getKillRegState(DstIsKill))
-      .addReg(DstReg, getKillRegState(DstIsKill))
+      .addReg(DstReg, RegState::Kill)
+      .addReg(DstReg, RegState::Kill)
       ->getOperand(4)
       .setIsUndef(true);
 
   buildMI(MBB, MBBI, AVR::EORRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg, getKillRegState(DstIsKill))
-      .addReg(DstReg, getKillRegState(DstIsKill));
+      .addReg(DstReg, RegState::Kill)
+      .addReg(DstReg, RegState::Kill);
 
   auto MIRRC =
       buildMI(MBB, MBBI, AVR::ADCRdRr)
@@ -1986,13 +1987,13 @@
 
   buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rd
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg, getKillRegState(DstIsKill))
-      .addReg(DstReg, getKillRegState(DstIsKill));
+      .addReg(DstReg, RegState::Kill)
+      .addReg(DstReg, RegState::Kill);
 
   buildMI(MBB, MBBI, AVR::SBCRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg, getKillRegState(DstIsKill))
-      .addReg(DstReg, getKillRegState(DstIsKill));
+      .addReg(DstReg, RegState::Kill)
+      .addReg(DstReg, RegState::Kill);
 
   buildMI(MBB, MBBI, AVR::BLD)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
@@ -2017,8 +2018,8 @@
 
   buildMI(MBB, MBBI, AVR::ADDRdRr)
       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
-      .addReg(DstReg, getKillRegState(DstIsKill))
-      .addReg(DstReg, getKillRegState(DstIsKill));
+      .addReg(DstReg, RegState::Kill)
+      .addReg(DstReg, RegState::Kill);
 
   auto MIRRC =
       buildMI(MBB, MBBI, AVR::SBCRdRr)
@@ -2074,26 +2075,22 @@
   bool ImpIsDead = MI.getOperand(2).isDead();
   TRI->splitReg(DstReg, DstLoReg, DstHiReg);
 
-  if (SrcReg != DstLoReg) {
-    auto MOV =
-        buildMI(MBB, MBBI, AVR::MOVRdRr)
-            .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
-            .addReg(SrcReg);
-
-    if (SrcReg == DstHiReg) {
-      MOV->getOperand(1).setIsKill();
-    }
-  }
+  if (SrcReg != DstLoReg)
+    buildMI(MBB, MBBI, AVR::MOVRdRr)
+        .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
+        .addReg(SrcReg);
 
   if (SrcReg != DstHiReg) {
-    buildMI(MBB, MBBI, AVR::MOVRdRr)
-        .addReg(DstHiReg, RegState::Define)
-        .addReg(SrcReg, getKillRegState(SrcIsKill));
+    auto MOV = buildMI(MBB, MBBI, AVR::MOVRdRr)
+                   .addReg(DstHiReg, RegState::Define)
+                   .addReg(SrcReg);
+    if (SrcReg != DstLoReg && SrcIsKill)
+      MOV->getOperand(1).setIsKill();
   }
 
   buildMI(MBB, MBBI, AVR::ADDRdRr) // LSL Rd <==> ADD Rd, Rr
       .addReg(DstHiReg, RegState::Define)
-      .addReg(DstHiReg)
+      .addReg(DstHiReg, RegState::Kill)
       .addReg(DstHiReg, RegState::Kill);
 
   auto SBC =
diff --git a/llvm/test/CodeGen/AVR/pseudo/ASRBNRd.mir b/llvm/test/CodeGen/AVR/pseudo/ASRBNRd.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/pseudo/ASRBNRd.mir
@@ -0,0 +1,22 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+--- |
+  target triple = "avr--"
+  define void @test() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test
+body: |
+  bb.0.entry:
+    liveins: $r17
+
+    ; CHECK-LABEL: test
+
+    ; CHECK:      $r17 = ADDRdRr killed $r17, killed $r17, implicit-def $sreg
+    ; CHECK-NEXT: $r17 = SBCRdRr $r17, $r17, implicit-def $sreg, implicit killed $sreg
+    $r17 = ASRBNRd $r17, 7, implicit-def $sreg
+...
diff --git a/llvm/test/CodeGen/AVR/pseudo/LSLBNRd.mir b/llvm/test/CodeGen/AVR/pseudo/LSLBNRd.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/pseudo/LSLBNRd.mir
@@ -0,0 +1,23 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+--- |
+  target triple = "avr--"
+  define void @test() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test
+body: |
+  bb.0.entry:
+    liveins: $r17
+
+    ; CHECK-LABEL: test
+
+    ; CHECK:      $r17 = RORRd killed $r17, implicit-def $sreg, implicit undef $sreg
+    ; CHECK-NEXT: $r17 = EORRdRr killed $r17, killed $r17, implicit-def $sreg
+    ; CHECK-NEXT: $r17 = RORRd $r17, implicit-def $sreg, implicit killed $sreg
+    $r17 = LSLBNRd $r17, 7, implicit-def $sreg
+...
diff --git a/llvm/test/CodeGen/AVR/pseudo/LSLWNRd.mir b/llvm/test/CodeGen/AVR/pseudo/LSLWNRd.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/pseudo/LSLWNRd.mir
@@ -0,0 +1,36 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+--- |
+  target triple = "avr--"
+  define void @test() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test
+body: |
+  bb.0.entry:
+    liveins: $r17r16, $r19r18, $r21r20
+
+    ; CHECK-LABEL: test
+
+    ; CHECK:      $r17 = SWAPRd killed $r17
+    ; CHECK-NEXT: $r16 = SWAPRd killed $r16
+    ; CHECK-NEXT: $r17 = ANDIRdK killed $r17, 240, implicit-def dead $sreg
+    ; CHECK-NEXT: $r17 = EORRdRr killed $r17, $r16, implicit-def dead $sreg
+    ; CHECK-NEXT: $r16 = ANDIRdK $r16, 240, implicit-def dead $sreg
+    ; CHECK-NEXT: $r17 = EORRdRr $r17, $r16, implicit-def $sreg
+    $r17r16 = LSLWNRd $r17r16,  4, implicit-def $sreg
+
+    ; CHECK-NEXT: $r19 = MOVRdRr $r18
+    ; CHECK-NEXT: $r18 = EORRdRr $r18, $r18, implicit-def $sreg
+    $r19r18 = LSLWNRd $r19r18,  8, implicit-def $sreg
+
+    ; CHECK-NEXT: $r21 = MOVRdRr $r20
+    ; CHECK-NEXT: $r21 = SWAPRd killed $r21
+    ; CHECK-NEXT: $r21 = ANDIRdK $r21, 240, implicit-def dead $sreg
+    ; CHECK-NEXT: $r20 = EORRdRr $r20, $r20, implicit-def $sreg
+    $r21r20 = LSLWNRd $r21r20, 12, implicit-def $sreg
+...
diff --git a/llvm/test/CodeGen/AVR/pseudo/LSRBNRd.mir b/llvm/test/CodeGen/AVR/pseudo/LSRBNRd.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/pseudo/LSRBNRd.mir
@@ -0,0 +1,23 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+--- |
+  target triple = "avr--"
+  define void @test() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test
+body: |
+  bb.0.entry:
+    liveins: $r17
+
+    ; CHECK-LABEL: test
+
+    ; CHECK:      $r17 = ADCRdRr killed $r17, killed $r17, implicit-def $sreg, implicit undef $sreg
+    ; CHECK-NEXT: $r17 = EORRdRr killed $r17, killed $r17, implicit-def $sreg
+    ; CHECK-NEXT: $r17 = ADCRdRr $r17, $r17, implicit-def $sreg, implicit killed $sreg
+    $r17 = LSRBNRd $r17, 7, implicit-def $sreg
+...
diff --git a/llvm/test/CodeGen/AVR/pseudo/LSRWNRd.mir b/llvm/test/CodeGen/AVR/pseudo/LSRWNRd.mir
new file mode 100644
--- /dev/null
+++ b/llvm/test/CodeGen/AVR/pseudo/LSRWNRd.mir
@@ -0,0 +1,36 @@
+# RUN: llc -O0 -run-pass=avr-expand-pseudo %s -o - | FileCheck %s
+
+--- |
+  target triple = "avr--"
+  define void @test() {
+  entry:
+    ret void
+  }
+...
+
+---
+name:            test
+body: |
+  bb.0.entry:
+    liveins: $r17r16, $r19r18, $r21r20
+
+    ; CHECK-LABEL: test
+
+    ; CHECK:      $r17 = SWAPRd killed $r17
+    ; CHECK-NEXT: $r16 = SWAPRd killed $r16
+    ; CHECK-NEXT: $r16 = ANDIRdK killed $r16, 15, implicit-def dead $sreg
+    ; CHECK-NEXT: $r16 = EORRdRr killed $r16, $r17, implicit-def dead $sreg
+    ; CHECK-NEXT: $r17 = ANDIRdK $r17, 15, implicit-def dead $sreg
+    ; CHECK-NEXT: $r16 = EORRdRr $r16, $r17, implicit-def $sreg
+    $r17r16 = LSRWNRd $r17r16,  4, implicit-def $sreg
+
+    ; CHECK-NEXT: $r18 = MOVRdRr $r19
+    ; CHECK-NEXT: $r19 = EORRdRr $r19, $r19, implicit-def $sreg
+    $r19r18 = LSRWNRd $r19r18,  8, implicit-def $sreg
+
+    ; CHECK-NEXT: $r20 = MOVRdRr $r21
+    ; CHECK-NEXT: $r20 = SWAPRd killed $r20
+    ; CHECK-NEXT: $r20 = ANDIRdK $r20, 15, implicit-def dead $sreg
+    ; CHECK-NEXT: $r21 = EORRdRr $r21, $r21, implicit-def $sreg
+    $r21r20 = LSRWNRd $r21r20, 12, implicit-def $sreg
+...
diff --git a/llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir b/llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir
--- a/llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/NEGWRd.mir
@@ -18,7 +18,7 @@
 
     ; CHECK-LABEL: test_negwrd
 
-    ; CHECK:      $r15 = NEGRd $r15, implicit-def dead $sreg
+    ; CHECK:      $r15 = NEGRd killed $r15, implicit-def dead $sreg
     ; CHECK-NEXT: $r14 = NEGRd $r14
     ; CHECK-NEXT: $r15 = SBCRdRr $r15, $r1, implicit-def $sreg, implicit killed $sreg
 
diff --git a/llvm/test/CodeGen/AVR/pseudo/SEXT.mir b/llvm/test/CodeGen/AVR/pseudo/SEXT.mir
--- a/llvm/test/CodeGen/AVR/pseudo/SEXT.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/SEXT.mir
@@ -18,7 +18,7 @@
 
     ; CHECK:      $r14 = MOVRdRr $r31
     ; CHECK-NEXT: $r15 = MOVRdRr $r31
-    ; CHECK-NEXT: $r15 = ADDRdRr $r15, killed $r15, implicit-def $sreg
+    ; CHECK-NEXT: $r15 = ADDRdRr killed $r15, killed $r15, implicit-def $sreg
     ; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
 
     $r15r14 = SEXT $r31, implicit-def $sreg
diff --git a/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir b/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir
--- a/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/ZEXT.mir
@@ -18,7 +18,7 @@
 
     ; CHECK:      $r14 = MOVRdRr $r31
     ; CHECK-NEXT: $r15 = MOVRdRr $r31
-    ; CHECK-NEXT: $r15 = ADDRdRr $r15, killed $r15, implicit-def $sreg
+    ; CHECK-NEXT: $r15 = ADDRdRr killed $r15, killed $r15, implicit-def $sreg
     ; CHECK-NEXT: $r15 = SBCRdRr killed $r15, killed $r15, implicit-def $sreg, implicit killed $sreg
 
     $r15r14 = SEXT $r31, implicit-def $sreg