Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp =================================================================== --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -14537,7 +14537,7 @@ unsigned NumElts = 1; EVT VT = N->getValueType(0); if (VT.isVector() && DAG.isSplatValue(N1)) - NumElts = VT.getVectorNumElements(); + NumElts = VT.getVectorMinNumElements(); if (!MinUses || (N1->use_size() * NumElts) < MinUses) return SDValue(); Index: llvm/test/CodeGen/AArch64/fdiv-combine-vec.ll =================================================================== --- /dev/null +++ llvm/test/CodeGen/AArch64/fdiv-combine-vec.ll @@ -0,0 +1,36 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=aarch64 < %s | FileCheck %s + +define @splat_fdiv_nxv4f32( %vx, float %y) #0 { +; CHECK-LABEL: splat_fdiv_nxv4f32: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: // kill: def $s1 killed $s1 def $z1 +; CHECK-NEXT: fmov z2.s, #1.00000000 +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: mov z1.s, s1 +; CHECK-NEXT: fdivr z1.s, p0/m, z1.s, z2.s +; CHECK-NEXT: fmul z0.s, z0.s, z1.s +; CHECK-NEXT: ret +entry: + %vy.ins = insertelement poison, float %y, i64 0 + %splat = shufflevector %vy.ins, poison, zeroinitializer + %div = fdiv fast %vx, %splat + ret %div +} + +define @splat_fdiv_nxv2f64( %vx, double %y) #0 { +; CHECK-LABEL: splat_fdiv_nxv2f64: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: mov z1.d, d1 +; CHECK-NEXT: fdiv z0.d, p0/m, z0.d, z1.d +; CHECK-NEXT: ret +entry: + %vy.ins = insertelement poison, double %y, i64 0 + %splat = shufflevector %vy.ins, poison, zeroinitializer + %div = fdiv fast %vx, %splat + ret %div +} + +attributes #0 = { "target-features"="+sve" }