diff --git a/clang/lib/Basic/Targets/RISCV.cpp b/clang/lib/Basic/Targets/RISCV.cpp
--- a/clang/lib/Basic/Targets/RISCV.cpp
+++ b/clang/lib/Basic/Targets/RISCV.cpp
@@ -188,7 +188,9 @@
   if (ISAInfo->hasExtension("c"))
     Builder.defineMacro("__riscv_compressed");
 
-  if (ISAInfo->hasExtension("zve32x") || ISAInfo->hasExtension("v"))
+  if (ISAInfo->hasExtension("zve32x") || ISAInfo->hasExtension("zve32f") ||
+      ISAInfo->hasExtension("zve64x") || ISAInfo->hasExtension("zve64f") ||
+      ISAInfo->hasExtension("zve64d") || ISAInfo->hasExtension("v"))
     Builder.defineMacro("__riscv_vector");
 }
 
diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c
--- a/clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c
+++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/rvv-error.c
@@ -11,7 +11,7 @@
 // CHECK-RV64V-NEXT:    ret i32 [[CONV]]
 //
 
-// CHECK-RV64-ERR: error: builtin requires at least one of the following extensions support to be enabled : 'Zve32x', 'V'
+// CHECK-RV64-ERR: error: builtin requires at least one of the following extensions support to be enabled : 'Zve32x', 'Zve32f', 'Zve64x', 'Zve64f', 'Zve64d', 'V'
 
 int test() {
   return __builtin_rvv_vsetvli(1, 0, 0);
diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c
--- a/clang/test/Preprocessor/riscv-target-features.c
+++ b/clang/test/Preprocessor/riscv-target-features.c
@@ -295,11 +295,7 @@
 // CHECK-ZVE64D-EXT: __riscv_v_elen_fp 64
 // CHECK-ZVE64D-EXT: __riscv_v_min_vlen 64
 // CHECK-ZVE64D-EXT: __riscv_vector 1
-// CHECK-ZVE64D-EXT: __riscv_zve32f 1000000{{$}}
-// CHECK-ZVE64D-EXT: __riscv_zve32x 1000000{{$}}
 // CHECK-ZVE64D-EXT: __riscv_zve64d 1000000{{$}}
-// CHECK-ZVE64D-EXT: __riscv_zve64f 1000000{{$}}
-// CHECK-ZVE64D-EXT: __riscv_zve64x 1000000{{$}}
 
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64ifzve64f1p0 -x c -E -dM %s -o - \
@@ -308,10 +304,7 @@
 // CHECK-ZVE64F-EXT: __riscv_v_elen_fp 32
 // CHECK-ZVE64F-EXT: __riscv_v_min_vlen 64
 // CHECK-ZVE64F-EXT: __riscv_vector 1
-// CHECK-ZVE64F-EXT: __riscv_zve32f 1000000{{$}}
-// CHECK-ZVE64F-EXT: __riscv_zve32x 1000000{{$}}
 // CHECK-ZVE64F-EXT: __riscv_zve64f 1000000{{$}}
-// CHECK-ZVE64F-EXT: __riscv_zve64x 1000000{{$}}
 
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izve64x1p0 -x c -E -dM %s -o - \
@@ -320,7 +313,6 @@
 // CHECK-ZVE64X-EXT: __riscv_v_elen_fp 0
 // CHECK-ZVE64X-EXT: __riscv_v_min_vlen 64
 // CHECK-ZVE64X-EXT: __riscv_vector 1
-// CHECK-ZVE64X-EXT: __riscv_zve32x 1000000{{$}}
 // CHECK-ZVE64X-EXT: __riscv_zve64x 1000000{{$}}
 
 // RUN: %clang -target riscv64-unknown-linux-gnu \
@@ -331,7 +323,6 @@
 // CHECK-ZVE32F-EXT: __riscv_v_min_vlen 32
 // CHECK-ZVE32F-EXT: __riscv_vector 1
 // CHECK-ZVE32F-EXT: __riscv_zve32f 1000000{{$}}
-// CHECK-ZVE32F-EXT: __riscv_zve32x 1000000{{$}}
 
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izve32x1p0 -x c -E -dM %s -o - \
diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp
--- a/clang/utils/TableGen/RISCVVEmitter.cpp
+++ b/clang/utils/TableGen/RISCVVEmitter.cpp
@@ -1040,7 +1040,7 @@
 
   OS << "#if defined(TARGET_BUILTIN) && !defined(RISCVV_BUILTIN)\n";
   OS << "#define RISCVV_BUILTIN(ID, TYPE, ATTRS) TARGET_BUILTIN(ID, TYPE, "
-        "ATTRS, \"zve32x|v\")\n";
+        "ATTRS, \"zve32x|zve32f|zve64x|zve64f|zve64d|v\")\n";
   OS << "#endif\n";
   for (auto &Def : Defs) {
     auto P =
diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp
--- a/llvm/lib/Support/RISCVISAInfo.cpp
+++ b/llvm/lib/Support/RISCVISAInfo.cpp
@@ -704,9 +704,13 @@
   bool HasF = Exts.count("f") != 0;
   bool HasZve32x = Exts.count("zve32x") != 0;
   bool HasZve32f = Exts.count("zve32f") != 0;
+  bool HasZve64x = Exts.count("zve64x") != 0;
+  bool HasZve64f = Exts.count("zve64f") != 0;
   bool HasZve64d = Exts.count("zve64d") != 0;
+  bool HasZve = HasZve32x || HasZve32f || HasZve64x || HasZve64f || HasZve64d;
+  bool HasZvef = HasZve32f || HasZve64f || HasZve64d;
   bool HasV = Exts.count("v") != 0;
-  bool HasVector = HasZve32x || HasV;
+  bool HasVector = HasZve || HasV;
   bool HasZvl = MinVLen != 0;
 
   if (HasE && !IsRv32)
@@ -723,10 +727,10 @@
                              "d requires f extension to also be specified");
 
   // FIXME: Consider Zfinx in the future
-  if (HasZve32f && !HasF)
+  if (HasZvef && !HasF)
     return createStringError(
         errc::invalid_argument,
-        "zve32f requires f extension to also be specified");
+        "zve*f requires f extension to also be specified");
 
   // FIXME: Consider Zdinx in the future
   if (HasZve64d && !HasD)
@@ -739,8 +743,14 @@
         errc::invalid_argument,
         "zvl*b requires v or zve* extension to also be specified");
 
+  // Could not implement multiple Zve* extensions.
+  if (HasZve32x + HasZve32f + HasZve64x + HasZve64f + HasZve64d > 1)
+    return createStringError(
+        errc::invalid_argument,
+        "It is illegal to specify multiple zve* extensions");
+
   // Could not implement Zve* extension and the V extension at the same time.
-  if (HasZve32x && HasV)
+  if (HasZve && HasV)
     return createStringError(
         errc::invalid_argument,
         "It is illegal to specify the v extension with zve* extensions");
@@ -754,10 +764,10 @@
 
 static const char *ImpliedExtsV[] = {"zvl128b", "f", "d"};
 static const char *ImpliedExtsZfh[] = {"zfhmin"};
-static const char *ImpliedExtsZve64d[] = {"zve64f"};
-static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
-static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"};
-static const char *ImpliedExtsZve32f[] = {"zve32x"};
+static const char *ImpliedExtsZve64d[] = {"zvl64b"};
+static const char *ImpliedExtsZve64f[] = {"zvl64b"};
+static const char *ImpliedExtsZve64x[] = {"zvl64b"};
+static const char *ImpliedExtsZve32f[] = {"zvl32b"};
 static const char *ImpliedExtsZve32x[] = {"zvl32b"};
 static const char *ImpliedExtsZvl65536b[] = {"zvl32768b"};
 static const char *ImpliedExtsZvl32768b[] = {"zvl16384b"};
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -305,24 +305,24 @@
     : SubtargetFeature<"zve32f", "HasStdExtZve32f", "true",
                        "'Zve32f' (Vector Extensions for Embedded Processors "
                        "with maximal 32 EEW and F extension)",
-                       [FeatureStdExtZve32x]>;
+                       [FeatureStdExtZvl32b]>;
 
 def FeatureStdExtZve64x
     : SubtargetFeature<"zve64x", "HasStdExtZve64x", "true",
                        "'Zve64x' (Vector Extensions for Embedded Processors "
-                       "with maximal 64 EEW)", [FeatureStdExtZve32x, FeatureStdExtZvl64b]>;
+                       "with maximal 64 EEW)", [FeatureStdExtZvl64b]>;
 
 def FeatureStdExtZve64f
     : SubtargetFeature<"zve64f", "HasStdExtZve64f", "true",
                        "'Zve64f' (Vector Extensions for Embedded Processors "
                        "with maximal 64 EEW and F extension)",
-                       [FeatureStdExtZve32f, FeatureStdExtZve64x]>;
+                       [FeatureStdExtZvl64b]>;
 
 def FeatureStdExtZve64d
     : SubtargetFeature<"zve64d", "HasStdExtZve64d", "true",
                        "'Zve64d' (Vector Extensions for Embedded Processors "
                        "with maximal 64 EEW, F and D extension)",
-                       [FeatureStdExtZve64f]>;
+                       [FeatureStdExtZvl64b]>;
 
 def FeatureStdExtV
     : SubtargetFeature<"v", "HasStdExtV", "true",
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -202,18 +202,29 @@
   }
 
   // Vector codegen related methods.
-  bool hasVInstructions() const { return HasStdExtV || HasStdExtZve32x; }
-  bool hasVInstructionsI64() const { return HasStdExtV || HasStdExtZve64x; }
+  bool hasZve() const {
+    return HasStdExtZve32x || HasStdExtZve32f || HasStdExtZve64x ||
+           HasStdExtZve64f || HasStdExtZve64d;
+  }
+  bool hasZve64() const {
+    return HasStdExtZve64x || HasStdExtZve64f || HasStdExtZve64d;
+  }
+  bool hasZvef() const {
+    return HasStdExtZve32f || HasStdExtZve64f || HasStdExtZve64d;
+  }
+  bool hasZved() const { return HasStdExtZve64d; }
+  bool hasVInstructions() const { return HasStdExtV || hasZve(); }
+  bool hasVInstructionsI64() const { return HasStdExtV || hasZve64(); }
   bool hasVInstructionsF16() const {
-    return (HasStdExtV || HasStdExtZve32f) && HasStdExtZfh;
+    return HasStdExtZfh && (HasStdExtV || hasZvef());
   }
   // FIXME: Consider Zfinx in the future
   bool hasVInstructionsF32() const {
-    return HasStdExtV || (HasStdExtZve32f && HasStdExtF);
+    return HasStdExtV || (hasZvef() && HasStdExtF);
   }
   // FIXME: Consider Zdinx in the future
   bool hasVInstructionsF64() const {
-    return HasStdExtV || (HasStdExtZve64d && HasStdExtD);
+    return HasStdExtV || (hasZved() && HasStdExtD);
   }
   // F16 and F64 both require F32.
   bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); }
diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s
--- a/llvm/test/MC/RISCV/attribute-arch.s
+++ b/llvm/test/MC/RISCV/attribute-arch.s
@@ -76,16 +76,16 @@
 # CHECK: attribute      5, "rv32i2p0_zve32x1p0_zvl32b1p0"
 
 .attribute arch, "rv32ifzve32f"
-# CHECK: attribute      5, "rv32i2p0_f2p0_zve32f1p0_zve32x1p0_zvl32b1p0"
+# CHECK: attribute      5, "rv32i2p0_f2p0_zve32f1p0_zvl32b1p0"
 
 .attribute arch, "rv32izve64x"
-# CHECK: attribute      5, "rv32i2p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute      5, "rv32i2p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ifzve64f"
-# CHECK: attribute      5, "rv32i2p0_f2p0_zve32f1p0_zve32x1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute      5, "rv32i2p0_f2p0_zve64f1p0_zvl32b1p0_zvl64b1p0"
 
 .attribute arch, "rv32ifdzve64d"
-# CHECK: attribute      5, "rv32i2p0_f2p0_d2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
+# CHECK: attribute      5, "rv32i2p0_f2p0_d2p0_zve64d1p0_zvl32b1p0_zvl64b1p0"
 
 ## Experimental extensions require version string to be explicitly specified