Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1071,6 +1071,8 @@
     return (MI.getOperand(1).isReg() &&
             MI.getOperand(1).getReg() == RISCV::X0) ||
            (MI.getOperand(2).isImm() && MI.getOperand(2).getImm() == 0);
+  case RISCV::LUI:
+    return MI.getOperand(1).getTargetFlags() != RISCVII::MO_HI;
   }
   return MI.isAsCheapAsAMove();
 }
Index: llvm/test/CodeGen/RISCV/unroll-loop-cse.ll
===================================================================
--- llvm/test/CodeGen/RISCV/unroll-loop-cse.ll
+++ llvm/test/CodeGen/RISCV/unroll-loop-cse.ll
@@ -16,28 +16,20 @@
 ; RV32I-NEXT:    bne a3, a4, .LBB0_6
 ; RV32I-NEXT:  # %bb.1:
 ; RV32I-NEXT:    addi a1, a1, %lo(x)
-; RV32I-NEXT:    lw a1, 4(a1)
+; RV32I-NEXT:    lw a3, 4(a1)
 ; RV32I-NEXT:    addi a2, a2, %lo(check)
-; RV32I-NEXT:    lw a2, 4(a2)
-; RV32I-NEXT:    bne a1, a2, .LBB0_6
+; RV32I-NEXT:    lw a4, 4(a2)
+; RV32I-NEXT:    bne a3, a4, .LBB0_6
 ; RV32I-NEXT:  # %bb.2:
-; RV32I-NEXT:    lui a1, %hi(x)
-; RV32I-NEXT:    addi a1, a1, %lo(x)
 ; RV32I-NEXT:    lw a3, 8(a1)
-; RV32I-NEXT:    lui a2, %hi(check)
-; RV32I-NEXT:    addi a2, a2, %lo(check)
 ; RV32I-NEXT:    lw a4, 8(a2)
 ; RV32I-NEXT:    bne a3, a4, .LBB0_6
 ; RV32I-NEXT:  # %bb.3:
-; RV32I-NEXT:    lw a1, 12(a1)
-; RV32I-NEXT:    lw a2, 12(a2)
-; RV32I-NEXT:    bne a1, a2, .LBB0_6
+; RV32I-NEXT:    lw a3, 12(a1)
+; RV32I-NEXT:    lw a4, 12(a2)
+; RV32I-NEXT:    bne a3, a4, .LBB0_6
 ; RV32I-NEXT:  # %bb.4:
-; RV32I-NEXT:    lui a1, %hi(x)
-; RV32I-NEXT:    addi a1, a1, %lo(x)
 ; RV32I-NEXT:    lw a3, 16(a1)
-; RV32I-NEXT:    lui a2, %hi(check)
-; RV32I-NEXT:    addi a2, a2, %lo(check)
 ; RV32I-NEXT:    lw a4, 16(a2)
 ; RV32I-NEXT:    bne a3, a4, .LBB0_6
 ; RV32I-NEXT:  # %bb.5: