Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -130,24 +130,10 @@
   return false;
 }
 
-static bool readsExecAsData(const MachineInstr &MI) {
-  if (MI.isCompare())
-    return true;
-
-  switch (MI.getOpcode()) {
-  default:
-    break;
-  case AMDGPU::V_READFIRSTLANE_B32:
-    return true;
-  }
-
-  return false;
-}
-
 bool SIInstrInfo::isIgnorableUse(const MachineOperand &MO) const {
   // Any implicit use of exec by VALU is not a real register read.
   return MO.getReg() == AMDGPU::EXEC && MO.isImplicit() &&
-         isVALU(*MO.getParent()) && !readsExecAsData(*MO.getParent());
+         isVALU(*MO.getParent());
 }
 
 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1,
Index: llvm/lib/Target/AMDGPU/VOPCInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -89,6 +89,7 @@
   let mayLoad = 0;
   let mayStore = 0;
   let hasSideEffects = 0;
+  let isConvergent = 1;
 
   let ReadsModeReg = isFloatType<P.Src0VT>.ret;
 
@@ -216,7 +217,7 @@
              VCMPXNoSDstTable<1, opName#"_e32"> {
     let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
     let SchedRW = P.Schedule;
-    let isConvergent = DefExec;
+    let isConvergent = 1;
     let isCompare = 1;
     let isCommutable = 1;
   }
@@ -228,13 +229,14 @@
     let SchedRW = P.Schedule;
     let isCompare = 1;
     let isCommutable = 1;
+    let isConvergent = 1;
   }
 
   foreach _ = BoolToList<P.HasExtSDWA>.ret in
   def _sdwa : VOPC_SDWA_Pseudo <opName, P> {
     let Defs = !if(DefExec, [EXEC], []);
     let SchedRW = P.Schedule;
-    let isConvergent = DefExec;
+    let isConvergent = 1;
     let isCompare = 1;
   }
 }
@@ -254,6 +256,7 @@
     let isConvergent = 1;
     let isCompare = 1;
     let isCommutable = 1;
+    let isConvergent = 1;
     let SubtargetPredicate = HasNoSdstCMPX;
   }
 
@@ -264,6 +267,7 @@
     let SchedRW = P_NoSDst.Schedule;
     let isCompare = 1;
     let isCommutable = 1;
+    let isConvergent = 1;
     let SubtargetPredicate = HasNoSdstCMPX;
   }
 
@@ -668,13 +672,14 @@
     let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]),
                             !if(DefVcc, [VCC], []));
     let SchedRW = p.Schedule;
-    let isConvergent = DefExec;
+    let isConvergent = 1;
   }
 
   def _e64 : VOP3_Pseudo<opName, p, getVOPCClassPat64<p>.ret>,
              VCMPXNoSDstTable<1, opName#"_e64"> {
     let Defs = !if(DefExec, [EXEC], []);
     let SchedRW = p.Schedule;
+    let isConvergent = 1;
   }
 
   foreach _ = BoolToList<p.HasExtSDWA>.ret in
@@ -682,7 +687,7 @@
     let Defs = !if(DefExec, !if(DefVcc, [VCC, EXEC], [EXEC]),
                             !if(DefVcc, [VCC], []));
     let SchedRW = p.Schedule;
-    let isConvergent = DefExec;
+    let isConvergent = 1;
   }
 }
 
@@ -705,6 +710,7 @@
     let Defs = [EXEC];
     let SchedRW = P_NoSDst.Schedule;
     let SubtargetPredicate = HasNoSdstCMPX;
+    let isConvergent = 1;
   }
 
   foreach _ = BoolToList<P_NoSDst.HasExtSDWA>.ret in
Index: llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
+++ llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
@@ -52,13 +52,10 @@
 ; CHECK-NEXT:    v_mov_b32_e32 v2, 0x7fc00000
 ; CHECK-NEXT:    buffer_store_dword v2, off, s[0:3], 0
 ; CHECK-NEXT:    buffer_store_dwordx4 v[0:3], off, s[0:3], 0
-; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1
-; CHECK-NEXT:    s_waitcnt expcnt(0)
-; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
-; CHECK-NEXT:    v_cmp_ne_u32_e64 s[0:1], 1, v1
+; CHECK-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v1
 ; CHECK-NEXT:  .LBB1_1: ; %bb9
 ; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    s_and_b64 vcc, exec, s[0:1]
+; CHECK-NEXT:    s_andn2_b64 vcc, exec, s[0:1]
 ; CHECK-NEXT:    s_cbranch_vccnz .LBB1_1
 ; CHECK-NEXT:  ; %bb.2: ; %bb11
 ; CHECK-NEXT:    s_mov_b32 s3, 0xf000