Index: include/llvm/Target/TargetRegisterInfo.h =================================================================== --- include/llvm/Target/TargetRegisterInfo.h +++ include/llvm/Target/TargetRegisterInfo.h @@ -35,8 +35,6 @@ class raw_ostream; class LiveRegMatrix; -extern cl::opt ForceStackAlign; - class TargetRegisterClass { public: typedef const MCPhysReg* iterator; Index: include/llvm/Target/TargetSubtargetInfo.h =================================================================== --- include/llvm/Target/TargetSubtargetInfo.h +++ include/llvm/Target/TargetSubtargetInfo.h @@ -181,6 +181,10 @@ /// \brief Enable the use of the early if conversion pass. virtual bool enableEarlyIfConversion() const { return false; } + /// \brief Force align the stack to the minimum alignment needed for the + /// function. + virtual bool forceAlignStack() const = 0; + /// \brief Return PBQPConstraint(s) for the target. /// /// Override to provide custom PBQP constraints. Index: lib/CodeGen/TargetRegisterInfo.cpp =================================================================== --- lib/CodeGen/TargetRegisterInfo.cpp +++ lib/CodeGen/TargetRegisterInfo.cpp @@ -24,14 +24,6 @@ #define DEBUG_TYPE "target-reg-info" -namespace llvm { -cl::opt - ForceStackAlign("force-align-stack", - cl::desc("Force align the stack to the minimum alignment" - " needed for the function."), - cl::init(false), cl::Hidden); -} // end namespace llvm - using namespace llvm; TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID, @@ -321,7 +313,7 @@ unsigned StackAlign = TFI->getStackAlignment(); bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) || F->hasFnAttribute(Attribute::StackAlignment)); - if (ForceStackAlign || requiresRealignment) { + if (MF.getSubtarget().forceAlignStack() || requiresRealignment) { if (canRealignStack(MF)) return true; DEBUG(dbgs() << "Can't realign function's stack: " << F->getName() << "\n"); Index: lib/Target/AArch64/AArch64.td =================================================================== --- lib/Target/AArch64/AArch64.td +++ lib/Target/AArch64/AArch64.td @@ -49,6 +49,10 @@ "Reserve X18, making it unavailable " "as a GPR">; +// FIXME: Make this a "generic" subtarget feature. +def ForceAlignStack : SubtargetFeature<"force-align-stack", "ForceAlignStack", + "true", "Force align the stack">; + //===----------------------------------------------------------------------===// // Architectures. // Index: lib/Target/AArch64/AArch64Subtarget.h =================================================================== --- lib/Target/AArch64/AArch64Subtarget.h +++ lib/Target/AArch64/AArch64Subtarget.h @@ -57,6 +57,9 @@ // ReserveX18 - X18 is not available as a general purpose register. bool ReserveX18; + // Force align the stack to the minimum alignment needed for the function. + bool ForceAlignStack; + bool IsLittle; /// CPUString - String name of used CPU. @@ -158,6 +161,8 @@ bool enableEarlyIfConversion() const override; + bool forceAlignStack() const override { return ForceAlignStack; } + std::unique_ptr getCustomPBQPConstraints() const override; }; } // End llvm namespace Index: lib/Target/AArch64/AArch64Subtarget.cpp =================================================================== --- lib/Target/AArch64/AArch64Subtarget.cpp +++ lib/Target/AArch64/AArch64Subtarget.cpp @@ -48,10 +48,10 @@ : AArch64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others), HasV8_1aOps(false), HasFPARMv8(false), HasNEON(false), HasCrypto(false), HasCRC(false), HasZeroCycleRegMove(false), HasZeroCycleZeroing(false), - StrictAlign(false), ReserveX18(false), IsLittle(LittleEndian), - CPUString(CPU), TargetTriple(TT), FrameLowering(), - InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(), - TLInfo(TM, *this) {} + StrictAlign(false), ReserveX18(false), ForceAlignStack(false), + IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), + FrameLowering(), InstrInfo(initializeSubtargetDependencies(FS)), + TSInfo(), TLInfo(TM, *this) {} /// ClassifyGlobalReference - Find the target operand flags that describe /// how a global value should be referenced for the current subtarget. Index: lib/Target/AMDGPU/AMDGPU.td =================================================================== --- lib/Target/AMDGPU/AMDGPU.td +++ lib/Target/AMDGPU/AMDGPU.td @@ -128,6 +128,10 @@ "true", "Enable scratch buffer sizes greater than 128 GB">; +// FIXME: Make this a "generic" subtarget feature. +def ForceAlignStack : SubtargetFeature<"force-align-stack", "ForceAlignStack", + "true", "Force align the stack">; + class SubtargetFeatureFetchLimit : SubtargetFeature <"fetch"#Value, "TexVTXClauseSize", Index: lib/Target/AMDGPU/AMDGPUSubtarget.h =================================================================== --- lib/Target/AMDGPU/AMDGPUSubtarget.h +++ lib/Target/AMDGPU/AMDGPUSubtarget.h @@ -90,6 +90,7 @@ int LDSBankCount; unsigned IsaVersion; bool EnableHugeScratchBuffer; + bool ForceAlignStack; AMDGPUFrameLowering FrameLowering; std::unique_ptr TLInfo; @@ -299,6 +300,8 @@ return true; } + bool forceAlignStack() const override { return ForceAlignStack; } + /// \brief Returns the offset in bytes from the start of the input buffer /// of the first explicit kernel argument. unsigned getExplicitKernelArgOffset() const { Index: lib/Target/AMDGPU/AMDGPUSubtarget.cpp =================================================================== --- lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -74,6 +74,7 @@ EnableVGPRSpilling(false), SGPRInitBug(false), IsGCN(false), GCN1Encoding(false), GCN3Encoding(false), CIInsts(false), LDSBankCount(0), IsaVersion(ISAVersion0_0_0), EnableHugeScratchBuffer(false), + ForceAlignStack(false), FrameLowering(TargetFrameLowering::StackGrowsUp, 64 * 16, // Maximum stack alignment (long16) 0), Index: lib/Target/ARM/ARM.td =================================================================== --- lib/Target/ARM/ARM.td +++ lib/Target/ARM/ARM.td @@ -167,6 +167,10 @@ "Don't use movt/movw pairs for 32-bit " "imms">; +// FIXME: Make this a "generic" subtarget feature. +def ForceAlignStack : SubtargetFeature<"force-align-stack", "ForceAlignStack", + "true", "Force align the stack">; + // ARM ISAs. def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true", "Support ARM v4T instructions">; Index: lib/Target/ARM/ARMSubtarget.h =================================================================== --- lib/Target/ARM/ARMSubtarget.h +++ lib/Target/ARM/ARMSubtarget.h @@ -216,6 +216,9 @@ /// entry to the function and which must be maintained by every function. unsigned stackAlignment; + /// Force align the stack to the minimum alignment needed for the function. + bool ForceAlignStack; + /// CPUString - String name of used CPU. std::string CPUString; @@ -439,6 +442,8 @@ /// True for some subtargets at > -O0. bool enablePostRAScheduler() const override; + bool forceAlignStack() const override { return ForceAlignStack; } + // enableAtomicExpand- True if we need to expand our atomics. bool enableAtomicExpand() const override; Index: lib/Target/ARM/ARMSubtarget.cpp =================================================================== --- lib/Target/ARM/ARMSubtarget.cpp +++ lib/Target/ARM/ARMSubtarget.cpp @@ -121,6 +121,7 @@ NoARM = false; ReserveR9 = false; NoMovt = false; + ForceAlignStack= false; SupportsTailCall = false; HasFP16 = false; HasD16 = false; Index: lib/Target/BPF/BPF.td =================================================================== --- lib/Target/BPF/BPF.td +++ lib/Target/BPF/BPF.td @@ -29,3 +29,7 @@ let InstructionSet = BPFInstrInfo; let AssemblyWriters = [BPFInstPrinter]; } + +// FIXME: Make this a "generic" subtarget feature. +def ForceAlignStack : SubtargetFeature<"force-align-stack", "ForceAlignStack", + "true", "Force align the stack">; \ No newline at end of file Index: lib/Target/BPF/BPFSubtarget.h =================================================================== --- lib/Target/BPF/BPFSubtarget.h +++ lib/Target/BPF/BPFSubtarget.h @@ -35,6 +35,9 @@ BPFTargetLowering TLInfo; TargetSelectionDAGInfo TSInfo; + /// Force align the stack to the minimum alignment needed for the function. + bool ForceAlignStack; + public: // This constructor initializes the data members to match that // of the specified triple. @@ -58,6 +61,8 @@ const TargetRegisterInfo *getRegisterInfo() const override { return &InstrInfo.getRegisterInfo(); } + + bool forceAlignStack() const override { return ForceAlignStack; } }; } // End llvm namespace Index: lib/Target/BPF/BPFSubtarget.cpp =================================================================== --- lib/Target/BPF/BPFSubtarget.cpp +++ lib/Target/BPF/BPFSubtarget.cpp @@ -28,4 +28,6 @@ BPFSubtarget::BPFSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM) : BPFGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this), - TLInfo(TM, *this) {} + TLInfo(TM, *this), ForceAlignStack(false) { + ParseSubtargetFeatures(CPU, FS); +} Index: lib/Target/Hexagon/Hexagon.td =================================================================== --- lib/Target/Hexagon/Hexagon.td +++ lib/Target/Hexagon/Hexagon.td @@ -25,6 +25,10 @@ def ArchV4: SubtargetFeature<"v4", "HexagonArchVersion", "V4", "Hexagon V4">; def ArchV5: SubtargetFeature<"v5", "HexagonArchVersion", "V5", "Hexagon V5">; +// FIXME: Make this a "generic" subtarget feature. +def ForceAlignStack : SubtargetFeature<"force-align-stack", "ForceAlignStack", + "true", "Force align the stack">; + //===----------------------------------------------------------------------===// // Hexagon Instruction Predicate Definitions. //===----------------------------------------------------------------------===// Index: lib/Target/Hexagon/HexagonSubtarget.h =================================================================== --- lib/Target/Hexagon/HexagonSubtarget.h +++ lib/Target/Hexagon/HexagonSubtarget.h @@ -44,6 +44,9 @@ HexagonArchEnum HexagonArchVersion; private: + /// Force align the stack to the minimum alignment needed for the function. + bool ForceAlignStack; + std::string CPUString; HexagonInstrInfo InstrInfo; HexagonTargetLowering TLInfo; @@ -100,6 +103,8 @@ const HexagonArchEnum &getHexagonArchVersion() const { return HexagonArchVersion; } + + bool forceAlignStack() const override { return ForceAlignStack; } }; } // end namespace llvm Index: lib/Target/Hexagon/HexagonSubtarget.cpp =================================================================== --- lib/Target/Hexagon/HexagonSubtarget.cpp +++ lib/Target/Hexagon/HexagonSubtarget.cpp @@ -72,7 +72,8 @@ HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM) - : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU), + : HexagonGenSubtargetInfo(TT, CPU, FS), ForceAlignStack(false), + CPUString(CPU), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), FrameLowering() { Index: lib/Target/MSP430/MSP430.td =================================================================== --- lib/Target/MSP430/MSP430.td +++ lib/Target/MSP430/MSP430.td @@ -22,6 +22,10 @@ : SubtargetFeature<"ext", "ExtendedInsts", "true", "Enable MSP430-X extensions">; +// FIXME: Make this a "generic" subtarget feature. +def ForceAlignStack : SubtargetFeature<"force-align-stack", "ForceAlignStack", + "true", "Force align the stack">; + //===----------------------------------------------------------------------===// // MSP430 supported processors. //===----------------------------------------------------------------------===// Index: lib/Target/MSP430/MSP430Subtarget.h =================================================================== --- lib/Target/MSP430/MSP430Subtarget.h +++ lib/Target/MSP430/MSP430Subtarget.h @@ -31,6 +31,10 @@ class MSP430Subtarget : public MSP430GenSubtargetInfo { virtual void anchor(); + + /// Force align the stack to the minimum alignment needed for the function. + bool ForceAlignStack; + bool ExtendedInsts; MSP430FrameLowering FrameLowering; MSP430InstrInfo InstrInfo; @@ -63,6 +67,8 @@ const TargetSelectionDAGInfo *getSelectionDAGInfo() const override { return &TSInfo; } + + bool forceAlignStack() const override { return ForceAlignStack; } }; } // End llvm namespace Index: lib/Target/MSP430/MSP430Subtarget.cpp =================================================================== --- lib/Target/MSP430/MSP430Subtarget.cpp +++ lib/Target/MSP430/MSP430Subtarget.cpp @@ -33,5 +33,6 @@ MSP430Subtarget::MSP430Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM) - : MSP430GenSubtargetInfo(TT, CPU, FS), FrameLowering(), - InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this) {} + : MSP430GenSubtargetInfo(TT, CPU, FS), ForceAlignStack(false), + FrameLowering(), InstrInfo(initializeSubtargetDependencies(CPU, FS)), + TLInfo(TM, *this) {} Index: lib/Target/Mips/Mips.td =================================================================== --- lib/Target/Mips/Mips.td +++ lib/Target/Mips/Mips.td @@ -164,6 +164,10 @@ "true", "Octeon cnMIPS Support", [FeatureMips64r2]>; +// FIXME: Make this a "generic" subtarget feature. +def ForceAlignStack : SubtargetFeature<"force-align-stack", "ForceAlignStack", + "true", "Force align the stack">; + //===----------------------------------------------------------------------===// // Mips processors supported. //===----------------------------------------------------------------------===// Index: lib/Target/Mips/MipsSubtarget.h =================================================================== --- lib/Target/Mips/MipsSubtarget.h +++ lib/Target/Mips/MipsSubtarget.h @@ -130,6 +130,9 @@ // HasMSA -- supports MSA ASE. bool HasMSA; + // Force align the stack to the minimum alignment needed for the function. + bool ForceAlignStack; + InstrItineraryData InstrItins; // We can override the determination of whether we are in mips16 mode @@ -258,6 +261,8 @@ unsigned stackAlignment() const { return hasMips64() ? 16 : 8; } + bool forceAlignStack() const override { return ForceAlignStack; } + // Grab relocation model Reloc::Model getRelocationModel() const; Index: lib/Target/Mips/MipsSubtarget.cpp =================================================================== --- lib/Target/Mips/MipsSubtarget.cpp +++ lib/Target/Mips/MipsSubtarget.cpp @@ -70,7 +70,7 @@ HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), HasDSPR2(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), - HasMSA(false), TM(TM), TargetTriple(TT), TSInfo(), + HasMSA(false), ForceAlignStack(false), TM(TM), TargetTriple(TT), TSInfo(), InstrInfo( MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))), FrameLowering(MipsFrameLowering::create(*this)), Index: lib/Target/NVPTX/NVPTX.td =================================================================== --- lib/Target/NVPTX/NVPTX.td +++ lib/Target/NVPTX/NVPTX.td @@ -55,6 +55,10 @@ def PTX42 : SubtargetFeature<"ptx42", "PTXVersion", "42", "Use PTX version 4.2">; +// FIXME: Make this a "generic" subtarget feature. +def ForceAlignStack : SubtargetFeature<"force-align-stack", "ForceAlignStack", + "true", "Force align the stack">; + //===----------------------------------------------------------------------===// // NVPTX supported processors. //===----------------------------------------------------------------------===// Index: lib/Target/NVPTX/NVPTXSubtarget.h =================================================================== --- lib/Target/NVPTX/NVPTXSubtarget.h +++ lib/Target/NVPTX/NVPTXSubtarget.h @@ -39,6 +39,9 @@ // SM version x.y is represented as 10*x+y, e.g. 3.1 == 31 unsigned int SmVersion; + // Force align the stack to the minimum alignment needed for the function. + bool ForceAlignStack; + const NVPTXTargetMachine &TM; NVPTXInstrInfo InstrInfo; NVPTXTargetLowering TLInfo; @@ -93,6 +96,7 @@ inline bool hasROT32() const { return hasHWROT32() || hasSWROT32(); } inline bool hasROT64() const { return SmVersion >= 20; } bool hasImageHandles() const; + bool forceAlignStack() const override { return ForceAlignStack; } unsigned int getSmVersion() const { return SmVersion; } std::string getTargetName() const { return TargetName; } Index: lib/Target/NVPTX/NVPTXSubtarget.cpp =================================================================== --- lib/Target/NVPTX/NVPTXSubtarget.cpp +++ lib/Target/NVPTX/NVPTXSubtarget.cpp @@ -46,9 +46,9 @@ NVPTXSubtarget::NVPTXSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const NVPTXTargetMachine &TM) - : NVPTXGenSubtargetInfo(TT, CPU, FS), PTXVersion(0), SmVersion(20), TM(TM), - InstrInfo(), TLInfo(TM, initializeSubtargetDependencies(CPU, FS)), - FrameLowering() {} + : NVPTXGenSubtargetInfo(TT, CPU, FS), PTXVersion(0), SmVersion(20), + ForceAlignStack(false), TM(TM), InstrInfo(), + TLInfo(TM, initializeSubtargetDependencies(CPU, FS)), FrameLowering() {} bool NVPTXSubtarget::hasImageHandles() const { // Enable handles for Kepler+, where CUDA supports indirect surfaces and Index: lib/Target/PowerPC/PPC.td =================================================================== --- lib/Target/PowerPC/PPC.td +++ lib/Target/PowerPC/PPC.td @@ -141,6 +141,10 @@ def DeprecatedDST : SubtargetFeature<"", "DeprecatedDST", "true", "Treat vector data stream cache control instructions as deprecated">; +// FIXME: Make this a "generic" subtarget feature. +def ForceAlignStack : SubtargetFeature<"force-align-stack", "ForceAlignStack", + "true", "Force align the stack">; + /* Since new processors generally contain a superset of features of those that came before them, the idea is to make implementations of new processors less error prone and easier to read. Index: lib/Target/PowerPC/PPCSubtarget.h =================================================================== --- lib/Target/PowerPC/PPCSubtarget.h +++ lib/Target/PowerPC/PPCSubtarget.h @@ -125,6 +125,9 @@ /// of the stack. bool IsQPXStackUnaligned; + /// Force align the stack to the minimum alignment needed for the function. + bool ForceAlignStack; + const PPCTargetMachine &TM; PPCFrameLowering FrameLowering; PPCInstrInfo InstrInfo; @@ -285,6 +288,8 @@ bool useAA() const override; bool enableSubRegLiveness() const override; + + bool forceAlignStack() const override { return ForceAlignStack; } }; } // End llvm namespace Index: lib/Target/PowerPC/PPCSubtarget.cpp =================================================================== --- lib/Target/PowerPC/PPCSubtarget.cpp +++ lib/Target/PowerPC/PPCSubtarget.cpp @@ -99,6 +99,7 @@ HasPartwordAtomics = false; HasDirectMove = false; IsQPXStackUnaligned = false; + ForceAlignStack = false; HasHTM = false; } Index: lib/Target/Sparc/Sparc.td =================================================================== --- lib/Target/Sparc/Sparc.td +++ lib/Target/Sparc/Sparc.td @@ -43,6 +43,10 @@ def UsePopc : SubtargetFeature<"popc", "UsePopc", "true", "Use the popc (population count) instruction">; +// FIXME: Make this a "generic" subtarget feature. +def ForceAlignStack : SubtargetFeature<"force-align-stack", "ForceAlignStack", + "true", "Force align the stack">; + //===----------------------------------------------------------------------===// // Register File, Calling Conv, Instruction Descriptions //===----------------------------------------------------------------------===// Index: lib/Target/Sparc/SparcSubtarget.h =================================================================== --- lib/Target/Sparc/SparcSubtarget.h +++ lib/Target/Sparc/SparcSubtarget.h @@ -37,6 +37,8 @@ bool Is64Bit; bool HasHardQuad; bool UsePopc; + bool ForceAlignStack; + SparcInstrInfo InstrInfo; SparcTargetLowering TLInfo; TargetSelectionDAGInfo TSInfo; @@ -86,6 +88,7 @@ /// spills and arguments. int getAdjustedFrameSize(int stackSize) const; + bool forceAlignStack() const override { return ForceAlignStack; } }; } // end namespace llvm Index: lib/Target/Sparc/SparcSubtarget.cpp =================================================================== --- lib/Target/Sparc/SparcSubtarget.cpp +++ lib/Target/Sparc/SparcSubtarget.cpp @@ -53,6 +53,7 @@ const std::string &FS, TargetMachine &TM, bool is64Bit) : SparcGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), + ForceAlignStack(false), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), FrameLowering(*this) {} Index: lib/Target/SystemZ/SystemZProcessors.td =================================================================== --- lib/Target/SystemZ/SystemZProcessors.td +++ lib/Target/SystemZ/SystemZProcessors.td @@ -76,6 +76,10 @@ >; def FeatureNoVector : SystemZMissingFeature<"Vector">; +// FIXME: Make this a "generic" subtarget feature. +def ForceAlignStack : SubtargetFeature<"force-align-stack", "ForceAlignStack", + "true", "Force align the stack">; + def : Processor<"generic", NoItineraries, []>; def : Processor<"z10", NoItineraries, []>; def : Processor<"z196", NoItineraries, Index: lib/Target/SystemZ/SystemZSubtarget.h =================================================================== --- lib/Target/SystemZ/SystemZSubtarget.h +++ lib/Target/SystemZ/SystemZSubtarget.h @@ -45,6 +45,7 @@ bool HasTransactionalExecution; bool HasProcessorAssist; bool HasVector; + bool ForceAlignStack; private: Triple TargetTriple; @@ -120,6 +121,8 @@ CodeModel::Model CM) const; bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } + + bool forceAlignStack() const override { return ForceAlignStack; } }; } // end namespace llvm Index: lib/Target/SystemZ/SystemZSubtarget.cpp =================================================================== --- lib/Target/SystemZ/SystemZSubtarget.cpp +++ lib/Target/SystemZ/SystemZSubtarget.cpp @@ -40,7 +40,7 @@ HasPopulationCount(false), HasFastSerialization(false), HasInterlockedAccess1(false), HasMiscellaneousExtensions(false), HasTransactionalExecution(false), HasProcessorAssist(false), - HasVector(false), TargetTriple(TT), + HasVector(false), ForceAlignStack(false), TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), TSInfo(), FrameLowering() {} Index: lib/Target/WebAssembly/WebAssembly.td =================================================================== --- lib/Target/WebAssembly/WebAssembly.td +++ lib/Target/WebAssembly/WebAssembly.td @@ -25,6 +25,10 @@ def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "false", "Enable 128-bit SIMD">; +// FIXME: Make this a "generic" subtarget feature. +def ForceAlignStack : SubtargetFeature<"force-align-stack", "ForceAlignStack", + "true", "Force align the stack">; + //===----------------------------------------------------------------------===// // Architectures. //===----------------------------------------------------------------------===// Index: lib/Target/WebAssembly/WebAssemblySubtarget.h =================================================================== --- lib/Target/WebAssembly/WebAssemblySubtarget.h +++ lib/Target/WebAssembly/WebAssemblySubtarget.h @@ -31,6 +31,9 @@ class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo { bool HasSIMD128; + /// Force align the stack to the minimum alignment needed for the function. + bool ForceAlignStack; + /// String name of used CPU. std::string CPUString; @@ -78,6 +81,8 @@ /// Parses features string setting specified subtarget options. Definition of /// function is auto generated by tblgen. void ParseSubtargetFeatures(StringRef CPU, StringRef FS); + + bool forceAlignStack() const override { return ForceAlignStack; } }; } // end namespace llvm Index: lib/Target/WebAssembly/WebAssemblySubtarget.cpp =================================================================== --- lib/Target/WebAssembly/WebAssemblySubtarget.cpp +++ lib/Target/WebAssembly/WebAssemblySubtarget.cpp @@ -41,7 +41,7 @@ const std::string &FS, const TargetMachine &TM) : WebAssemblyGenSubtargetInfo(TT, CPU, FS), HasSIMD128(false), - CPUString(CPU), TargetTriple(TT), FrameLowering(), + ForceAlignStack(false), CPUString(CPU), TargetTriple(TT), FrameLowering(), InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(), TLInfo(TM, *this) {} Index: lib/Target/X86/X86.td =================================================================== --- lib/Target/X86/X86.td +++ lib/Target/X86/X86.td @@ -199,6 +199,10 @@ : SubtargetFeature<"soft-float", "UseSoftFloat", "true", "Use software floating point features.">; +// FIXME: Make this a "generic" subtarget feature. +def ForceAlignStack : SubtargetFeature<"force-align-stack", "ForceAlignStack", + "true", "Force align the stack">; + //===----------------------------------------------------------------------===// // X86 processors supported. //===----------------------------------------------------------------------===// Index: lib/Target/X86/X86FrameLowering.cpp =================================================================== --- lib/Target/X86/X86FrameLowering.cpp +++ lib/Target/X86/X86FrameLowering.cpp @@ -498,7 +498,7 @@ const MachineFrameInfo *MFI = MF.getFrameInfo(); uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment. unsigned StackAlign = getStackAlignment(); - if (ForceStackAlign) { + if (MF.getSubtarget().forceAlignStack()) { if (MFI->hasCalls()) MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign; else if (MaxAlign < SlotSize) Index: lib/Target/X86/X86Subtarget.h =================================================================== --- lib/Target/X86/X86Subtarget.h +++ lib/Target/X86/X86Subtarget.h @@ -228,6 +228,9 @@ /// Instruction itineraries for scheduling InstrItineraryData InstrItins; + /// Force align the stack to the minimum alignment needed for the function. + bool ForceAlignStack; + private: /// Override the stack alignment. @@ -498,6 +501,8 @@ bool enableEarlyIfConversion() const override; + bool forceAlignStack() const override { return ForceAlignStack; } + /// Return the instruction itineraries based on the subtarget selection. const InstrItineraryData *getInstrItineraryData() const override { return &InstrItins; Index: lib/Target/X86/X86Subtarget.cpp =================================================================== --- lib/Target/X86/X86Subtarget.cpp +++ lib/Target/X86/X86Subtarget.cpp @@ -273,6 +273,7 @@ stackAlignment = 4; // FIXME: this is a known good value for Yonah. How about others? MaxInlineSizeThreshold = 128; + ForceAlignStack = false; UseSoftFloat = false; } Index: lib/Target/XCore/XCore.td =================================================================== --- lib/Target/XCore/XCore.td +++ lib/Target/XCore/XCore.td @@ -28,6 +28,14 @@ def XCoreInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// +// Subtarget features +//===----------------------------------------------------------------------===// + +// FIXME: Make this a "generic" subtarget feature. +def ForceAlignStack : SubtargetFeature<"force-align-stack", "ForceAlignStack", + "true", "Force align the stack">; + +//===----------------------------------------------------------------------===// // XCore processors supported. //===----------------------------------------------------------------------===// @@ -44,4 +52,4 @@ def XCore : Target { // Pull in Instruction Info: let InstructionSet = XCoreInstrInfo; -} +} \ No newline at end of file Index: lib/Target/XCore/XCoreSubtarget.h =================================================================== --- lib/Target/XCore/XCoreSubtarget.h +++ lib/Target/XCore/XCoreSubtarget.h @@ -36,6 +36,9 @@ XCoreTargetLowering TLInfo; XCoreSelectionDAGInfo TSInfo; + /// Force align the stack to the minimum alignment needed for the function. + bool ForceAlignStack; + public: /// This constructor initializes the data members to match that /// of the specified triple. @@ -60,6 +63,8 @@ const TargetRegisterInfo *getRegisterInfo() const override { return &InstrInfo.getRegisterInfo(); } + + bool forceAlignStack() const override { return ForceAlignStack; } }; } // End llvm namespace Index: lib/Target/XCore/XCoreSubtarget.cpp =================================================================== --- lib/Target/XCore/XCoreSubtarget.cpp +++ lib/Target/XCore/XCoreSubtarget.cpp @@ -28,4 +28,6 @@ XCoreSubtarget::XCoreSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, const TargetMachine &TM) : XCoreGenSubtargetInfo(TT, CPU, FS), InstrInfo(), FrameLowering(*this), - TLInfo(TM, *this), TSInfo() {} + TLInfo(TM, *this), TSInfo(), ForceAlignStack(false) { + ParseSubtargetFeatures(CPU, FS); +} Index: test/CodeGen/Generic/ForceStackAlign.ll =================================================================== --- test/CodeGen/Generic/ForceStackAlign.ll +++ test/CodeGen/Generic/ForceStackAlign.ll @@ -1,7 +1,7 @@ ; Check that stack alignment can be forced. Individual targets should test their ; specific implementation details. -; RUN: llc < %s -force-align-stack -stack-alignment=32 | FileCheck %s +; RUN: llc < %s -mattr=+force-align-stack -stack-alignment=32 | FileCheck %s ; CHECK-LABEL: @f ; CHECK-LABEL: @g Index: test/CodeGen/X86/dynamic-allocas-VLAs.ll =================================================================== --- test/CodeGen/X86/dynamic-allocas-VLAs.ll +++ test/CodeGen/X86/dynamic-allocas-VLAs.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mcpu=generic -march=x86-64 -mattr=+avx -mtriple=i686-apple-darwin10 | FileCheck %s -; RUN: llc < %s -mcpu=generic -force-align-stack -stack-alignment=32 -march=x86-64 -mattr=+avx -mtriple=i686-apple-darwin10 | FileCheck %s -check-prefix=FORCE-ALIGN +; RUN: llc < %s -mcpu=generic -stack-alignment=32 -march=x86-64 -mattr=+force-align-stack,+avx -mtriple=i686-apple-darwin10 | FileCheck %s -check-prefix=FORCE-ALIGN ; rdar://11496434 ; no VLAs or dynamic alignment Index: test/CodeGen/X86/force-align-stack-alloca.ll =================================================================== --- test/CodeGen/X86/force-align-stack-alloca.ll +++ test/CodeGen/X86/force-align-stack-alloca.ll @@ -3,7 +3,7 @@ ; arbitrarily force alignment up to 32-bytes for i386 hoping that this will ; exceed any ABI provisions. ; -; RUN: llc < %s -mcpu=generic -force-align-stack -stack-alignment=32 | FileCheck %s +; RUN: llc < %s -mcpu=generic -mattr=+force-align-stack -stack-alignment=32 | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32-S128" target triple = "i386-unknown-linux-gnu" Index: test/CodeGen/X86/force-align-stack.ll =================================================================== --- test/CodeGen/X86/force-align-stack.ll +++ test/CodeGen/X86/force-align-stack.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -relocation-model=static -force-align-stack | FileCheck %s +; RUN: llc < %s -relocation-model=static -mattr=+force-align-stack | FileCheck %s ; Tests to make sure that we always align the stack out to the minimum needed - ; in this case 16-bytes. target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" Index: test/CodeGen/X86/inline-asm-sp-clobber-memcpy.ll =================================================================== --- test/CodeGen/X86/inline-asm-sp-clobber-memcpy.ll +++ test/CodeGen/X86/inline-asm-sp-clobber-memcpy.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -force-align-stack -mtriple i386-apple-darwin -mcpu=i486 | FileCheck %s +; RUN: llc < %s -mattr=+force-align-stack -mtriple i386-apple-darwin -mcpu=i486 | FileCheck %s %struct.foo = type { [88 x i8] } Index: test/CodeGen/X86/movtopush.ll =================================================================== --- test/CodeGen/X86/movtopush.ll +++ test/CodeGen/X86/movtopush.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=i686-windows | FileCheck %s -check-prefix=NORMAL ; RUN: llc < %s -mtriple=x86_64-windows | FileCheck %s -check-prefix=X64 -; RUN: llc < %s -mtriple=i686-windows -force-align-stack -stack-alignment=32 | FileCheck %s -check-prefix=ALIGNED +; RUN: llc < %s -mtriple=i686-windows -mattr=+force-align-stack -stack-alignment=32 | FileCheck %s -check-prefix=ALIGNED %class.Class = type { i32 } %struct.s = type { i64 } Index: test/CodeGen/X86/pr11468.ll =================================================================== --- test/CodeGen/X86/pr11468.ll +++ test/CodeGen/X86/pr11468.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -force-align-stack -stack-alignment=32 -march=x86-64 -mattr=+avx -mtriple=i686-apple-darwin10 | FileCheck %s +; RUN: llc < %s -stack-alignment=32 -march=x86-64 -mattr=+force-align-stack,+avx -mtriple=i686-apple-darwin10 | FileCheck %s ; PR11468 define void @f(i64 %sz) uwtable { Index: test/CodeGen/X86/stack-align-memcpy.ll =================================================================== --- test/CodeGen/X86/stack-align-memcpy.ll +++ test/CodeGen/X86/stack-align-memcpy.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -force-align-stack -mtriple i386-apple-darwin -mcpu=i486 | FileCheck %s +; RUN: llc < %s -mattr=+force-align-stack -mtriple i386-apple-darwin -mcpu=i486 | FileCheck %s %struct.foo = type { [88 x i8] } Index: test/CodeGen/X86/unaligned-spill-folding.ll =================================================================== --- test/CodeGen/X86/unaligned-spill-folding.ll +++ test/CodeGen/X86/unaligned-spill-folding.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple=i386-unknown-freebsd -mcpu=core2 -stack-alignment=4 -relocation-model=pic < %s | FileCheck %s -check-prefix=UNALIGNED ; RUN: llc -mtriple=i386-unknown-freebsd -mcpu=core2 -stack-alignment=16 -relocation-model=pic < %s | FileCheck %s -check-prefix=ALIGNED -; RUN: llc -mtriple=i386-unknown-freebsd -mcpu=core2 -stack-alignment=4 -force-align-stack -relocation-model=pic < %s | FileCheck %s -check-prefix=FORCEALIGNED +; RUN: llc -mtriple=i386-unknown-freebsd -mcpu=core2 -stack-alignment=4 -mattr=+force-align-stack -relocation-model=pic < %s | FileCheck %s -check-prefix=FORCEALIGNED @arr = internal unnamed_addr global [32 x i32] zeroinitializer, align 16 Index: test/CodeGen/X86/x86-64-baseptr.ll =================================================================== --- test/CodeGen/X86/x86-64-baseptr.ll +++ test/CodeGen/X86/x86-64-baseptr.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=x86_64-pc-linux -force-align-stack -stack-alignment=32 < %s | FileCheck %s -; RUN: llc -mtriple=x86_64-pc-linux-gnux32 -force-align-stack -stack-alignment=32 < %s | FileCheck -check-prefix=X32ABI %s +; RUN: llc -mtriple=x86_64-pc-linux -mattr=+force-align-stack -stack-alignment=32 < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-pc-linux-gnux32 -mattr=+force-align-stack -stack-alignment=32 < %s | FileCheck -check-prefix=X32ABI %s ; This should run with NaCl as well ( -mtriple=x86_64-pc-nacl ) but currently doesn't due to PR22655 ; Make sure the correct register gets set up as the base pointer