Index: llvm/docs/AMDGPU/gfx9_hwreg.rst
===================================================================
--- llvm/docs/AMDGPU/gfx9_hwreg.rst
+++ llvm/docs/AMDGPU/gfx9_hwreg.rst
@@ -52,6 +52,10 @@
     HW_REG_LDS_ALLOC    Per-wave LDS allocation.
     HW_REG_IB_STS       Counters of outstanding instructions.
     HW_REG_SH_MEM_BASES Memory aperture.
+    HW_REG_TBA_LO       tba_lo register.
+    HW_REG_TBA_HI       tba_hi register.
+    HW_REG_TMA_LO       tma_lo register.
+    HW_REG_TMA_HI       tma_hi register.
     =================== ==========================================
 
 Examples:
Index: llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -1028,6 +1028,11 @@
     return isGFX10Plus(STI);
   case ID_XNACK_MASK:
     return isGFX10(STI) && !AMDGPU::isGFX10_BEncoding(STI);
+  case ID_TBA_LO:
+  case ID_TBA_HI:
+  case ID_TMA_LO:
+  case ID_TMA_HI:
+    return isGFX9Plus(STI);
   default:
     return ID_SYMBOLIC_FIRST_ <= Id && Id < getLastSymbolicHwreg(STI) &&
            IdSymbolic[Id];
Index: llvm/test/MC/AMDGPU/sopk-err.s
===================================================================
--- llvm/test/MC/AMDGPU/sopk-err.s
+++ llvm/test/MC/AMDGPU/sopk-err.s
@@ -60,22 +60,22 @@
 s_getreg_b32 s2, hwreg(HW_REG_TBA_LO)
 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9]
 // SICIVI-ERR: error: specified hardware register is not supported on this GPU
-// GFX9-ERR: error: specified hardware register is not supported on this GPU
+// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x82,0xb8]
 
 s_getreg_b32 s2, hwreg(HW_REG_TBA_HI)
 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9]
 // SICIVI-ERR: error: specified hardware register is not supported on this GPU
-// GFX9-ERR: error: specified hardware register is not supported on this GPU
+// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x82,0xb8]
 
 s_getreg_b32 s2, hwreg(HW_REG_TMA_LO)
 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9]
 // SICIVI-ERR: error: specified hardware register is not supported on this GPU
-// GFX9-ERR: error: specified hardware register is not supported on this GPU
+// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x82,0xb8]
 
 s_getreg_b32 s2, hwreg(HW_REG_TMA_HI)
 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9]
 // SICIVI-ERR: error: specified hardware register is not supported on this GPU
-// GFX9-ERR: error: specified hardware register is not supported on this GPU
+// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x82,0xb8]
 
 s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO)
 // GFX10:    s_getreg_b32 s2, hwreg(HW_REG_FLAT_SCR_LO) ; encoding: [0x14,0xf8,0x02,0xb9]
Index: llvm/test/MC/AMDGPU/sopk.s
===================================================================
--- llvm/test/MC/AMDGPU/sopk.s
+++ llvm/test/MC/AMDGPU/sopk.s
@@ -156,23 +156,27 @@
 // GFX10+ registers
 s_getreg_b32 s2, hwreg(16)
 // SICI:  s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x02,0xb9]
-// VI9:   s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x82,0xb8]
 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x02,0xb9]
+// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_LO) ; encoding: [0x10,0xf8,0x82,0xb8]
+// VI: s_getreg_b32 s2, hwreg(16) ; encoding: [0x10,0xf8,0x82,0xb8]
 
 s_getreg_b32 s2, hwreg(17)
 // SICI:  s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x02,0xb9]
-// VI9:   s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x82,0xb8]
 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x02,0xb9]
+// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TBA_HI) ; encoding: [0x11,0xf8,0x82,0xb8]
+// VI: s_getreg_b32 s2, hwreg(17) ; encoding: [0x11,0xf8,0x82,0xb8]
 
 s_getreg_b32 s2, hwreg(18)
 // SICI:  s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x02,0xb9]
-// VI9:   s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x82,0xb8]
 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x02,0xb9]
+// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_LO) ; encoding: [0x12,0xf8,0x82,0xb8]
+// VI: s_getreg_b32 s2, hwreg(18) ; encoding: [0x12,0xf8,0x82,0xb8]
 
 s_getreg_b32 s2, hwreg(19)
 // SICI:  s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x02,0xb9]
-// VI9:   s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x82,0xb8]
 // GFX10: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x02,0xb9]
+// GFX9: s_getreg_b32 s2, hwreg(HW_REG_TMA_HI) ; encoding: [0x13,0xf8,0x82,0xb8]
+// VI: s_getreg_b32 s2, hwreg(19) ; encoding: [0x13,0xf8,0x82,0xb8]
 
 s_getreg_b32 s2, hwreg(20)
 // SICI:  s_getreg_b32 s2, hwreg(20) ; encoding: [0x14,0xf8,0x02,0xb9]
@@ -260,23 +264,27 @@
 // GFX10+ registers
 s_setreg_b32 hwreg(16), s2
 // SICI:  s_setreg_b32 hwreg(16), s2      ; encoding: [0x10,0xf8,0x82,0xb9]
-// VI9:   s_setreg_b32 hwreg(16), s2      ; encoding: [0x10,0xf8,0x02,0xb9]
 // GFX10: s_setreg_b32 hwreg(HW_REG_TBA_LO), s2 ; encoding: [0x10,0xf8,0x82,0xb9]
+// GFX9: s_setreg_b32 hwreg(HW_REG_TBA_LO), s2 ; encoding: [0x10,0xf8,0x02,0xb9]
+// VI: s_setreg_b32 hwreg(16), s2 ; encoding: [0x10,0xf8,0x02,0xb9]
 
 s_setreg_b32 hwreg(17), s2
 // SICI:  s_setreg_b32 hwreg(17), s2      ; encoding: [0x11,0xf8,0x82,0xb9]
-// VI9:   s_setreg_b32 hwreg(17), s2      ; encoding: [0x11,0xf8,0x02,0xb9]
 // GFX10: s_setreg_b32 hwreg(HW_REG_TBA_HI), s2 ; encoding: [0x11,0xf8,0x82,0xb9]
+// GFX9: s_setreg_b32 hwreg(HW_REG_TBA_HI), s2 ; encoding: [0x11,0xf8,0x02,0xb9]
+// VI: s_setreg_b32 hwreg(17), s2 ; encoding: [0x11,0xf8,0x02,0xb9]
 
 s_setreg_b32 hwreg(18), s2
 // SICI:  s_setreg_b32 hwreg(18), s2      ; encoding: [0x12,0xf8,0x82,0xb9]
-// VI9:   s_setreg_b32 hwreg(18), s2      ; encoding: [0x12,0xf8,0x02,0xb9]
 // GFX10: s_setreg_b32 hwreg(HW_REG_TMA_LO), s2 ; encoding: [0x12,0xf8,0x82,0xb9]
+// GFX9: s_setreg_b32 hwreg(HW_REG_TMA_LO), s2 ; encoding: [0x12,0xf8,0x02,0xb9]
+// VI: s_setreg_b32 hwreg(18), s2 ; encoding: [0x12,0xf8,0x02,0xb9]
 
 s_setreg_b32 hwreg(19), s2
 // SICI:  s_setreg_b32 hwreg(19), s2      ; encoding: [0x13,0xf8,0x82,0xb9]
-// VI9:   s_setreg_b32 hwreg(19), s2      ; encoding: [0x13,0xf8,0x02,0xb9]
 // GFX10: s_setreg_b32 hwreg(HW_REG_TMA_HI), s2 ; encoding: [0x13,0xf8,0x82,0xb9]
+// GFX9: s_setreg_b32 hwreg(HW_REG_TMA_HI), s2 ; encoding: [0x13,0xf8,0x02,0xb9]
+// VI: s_setreg_b32 hwreg(19), s2 ; encoding: [0x13,0xf8,0x02,0xb9]
 
 s_setreg_b32 hwreg(20), s2
 // SICI:  s_setreg_b32 hwreg(20), s2      ; encoding: [0x14,0xf8,0x82,0xb9]
Index: llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
===================================================================
--- llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
+++ llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
@@ -20406,13 +20406,13 @@
 # CHECK: s_getreg_b32 exec_hi, hwreg(HW_REG_MODE, 5, 7) ; encoding: [0x41,0x31,0xff,0xb8]
 0x41,0x31,0xff,0xb8
 
-# CHECK: s_getreg_b32 s5, hwreg(17, 7, 25)       ; encoding: [0xd1,0xc1,0x85,0xb8]
+# CHECK: s_getreg_b32 s5, hwreg(HW_REG_TBA_HI, 7, 25) ; encoding: [0xd1,0xc1,0x85,0xb8]
 0xd1,0xc1,0x85,0xb8
 
 # CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), s1 ; encoding: [0x41,0x31,0x01,0xb9]
 0x41,0x31,0x01,0xb9
 
-# CHECK: s_setreg_b32 hwreg(17, 7, 25), s1       ; encoding: [0xd1,0xc1,0x01,0xb9]
+# CHECK: s_setreg_b32 hwreg(HW_REG_TBA_HI, 7, 25), s1 ; encoding: [0xd1,0xc1,0x01,0xb9]
 0xd1,0xc1,0x01,0xb9
 
 # CHECK: s_setreg_b32 hwreg(HW_REG_MODE, 5, 7), s101 ; encoding: [0x41,0x31,0x65,0xb9]
@@ -20442,7 +20442,7 @@
 # CHECK: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 5, 7), 0x11213141 ; encoding: [0x41,0x31,0x00,0xba,0x41,0x31,0x21,0x11]
 0x41,0x31,0x00,0xba,0x41,0x31,0x21,0x11
 
-# CHECK: s_setreg_imm32_b32 hwreg(17, 7, 25), 0x11213141 ; encoding: [0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11]
+# CHECK: s_setreg_imm32_b32 hwreg(HW_REG_TBA_HI, 7, 25), 0x11213141 ; encoding: [0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11]
 0xd1,0xc1,0x00,0xba,0x41,0x31,0x21,0x11
 
 # CHECK: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 5, 7), 0xa1b1c1d1 ; encoding: [0x41,0x31,0x00,0xba,0xd1,0xc1,0xb1,0xa1]