Index: llvm/test/CodeGen/AVR/PR31344.ll
===================================================================
--- llvm/test/CodeGen/AVR/PR31344.ll
+++ llvm/test/CodeGen/AVR/PR31344.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; Unit test for: PR 31344
 
Index: llvm/test/CodeGen/AVR/PR31345.ll
===================================================================
--- llvm/test/CodeGen/AVR/PR31345.ll
+++ llvm/test/CodeGen/AVR/PR31345.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; Unit test for: PR 31345
 
Index: llvm/test/CodeGen/AVR/add.ll
===================================================================
--- llvm/test/CodeGen/AVR/add.ll
+++ llvm/test/CodeGen/AVR/add.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=addsubiw < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=addsubiw < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 define i8 @add8_reg_reg(i8 %a, i8 %b) {
 ; CHECK-LABEL: add8_reg_reg:
Index: llvm/test/CodeGen/AVR/alloca.ll
===================================================================
--- llvm/test/CodeGen/AVR/alloca.ll
+++ llvm/test/CodeGen/AVR/alloca.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mattr=avr6 | FileCheck %s
+; RUN: llc < %s -march=avr -mattr=avr6 -verify-machineinstrs | FileCheck %s
 
 declare i16 @allocate(i16*, i16*)
 
Index: llvm/test/CodeGen/AVR/and.ll
===================================================================
--- llvm/test/CodeGen/AVR/and.ll
+++ llvm/test/CodeGen/AVR/and.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 define i8 @and8_reg_reg(i8 %a, i8 %b) {
 ; CHECK-LABEL: and8_reg_reg:
Index: llvm/test/CodeGen/AVR/atomics/fence.ll
===================================================================
--- llvm/test/CodeGen/AVR/atomics/fence.ll
+++ llvm/test/CodeGen/AVR/atomics/fence.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; Checks that atomic fences are simply removed from IR.
 ; AVR is always singlethreaded so fences do nothing.
Index: llvm/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
===================================================================
--- llvm/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
+++ llvm/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; At one point, the 16-vit atomic load/store operations we defined in TableGen
 ; to use 'PTRREGS', but the pseudo expander would generate LDDW/STDW instructions.
Index: llvm/test/CodeGen/AVR/atomics/load16.ll
===================================================================
--- llvm/test/CodeGen/AVR/atomics/load16.ll
+++ llvm/test/CodeGen/AVR/atomics/load16.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; CHECK-LABEL: atomic_load16
 ; CHECK:      in r0, 63
Index: llvm/test/CodeGen/AVR/atomics/load32.ll
===================================================================
--- llvm/test/CodeGen/AVR/atomics/load32.ll
+++ llvm/test/CodeGen/AVR/atomics/load32.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; CHECK-LABEL: atomic_load32
 ; CHECK: call __sync_val_compare_and_swap_4
Index: llvm/test/CodeGen/AVR/atomics/load64.ll
===================================================================
--- llvm/test/CodeGen/AVR/atomics/load64.ll
+++ llvm/test/CodeGen/AVR/atomics/load64.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; CHECK-LABEL: atomic_load64
 ; CHECK: call __sync_val_compare_and_swap_8
Index: llvm/test/CodeGen/AVR/atomics/load8.ll
===================================================================
--- llvm/test/CodeGen/AVR/atomics/load8.ll
+++ llvm/test/CodeGen/AVR/atomics/load8.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; Tests atomic operations on AVR
 
Index: llvm/test/CodeGen/AVR/atomics/store.ll
===================================================================
--- llvm/test/CodeGen/AVR/atomics/store.ll
+++ llvm/test/CodeGen/AVR/atomics/store.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; CHECK-LABEL: atomic_store8
 ; CHECK:      in r0, 63
Index: llvm/test/CodeGen/AVR/atomics/store16.ll
===================================================================
--- llvm/test/CodeGen/AVR/atomics/store16.ll
+++ llvm/test/CodeGen/AVR/atomics/store16.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; CHECK-LABEL: atomic_store16
 ; CHECK:      in r0, 63
Index: llvm/test/CodeGen/AVR/atomics/swap.ll
===================================================================
--- llvm/test/CodeGen/AVR/atomics/swap.ll
+++ llvm/test/CodeGen/AVR/atomics/swap.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; CHECK-LABEL: atomic_swap8
 ; CHECK: call __sync_lock_test_and_set_1
Index: llvm/test/CodeGen/AVR/avr-rust-issue-123.ll
===================================================================
--- llvm/test/CodeGen/AVR/avr-rust-issue-123.ll
+++ llvm/test/CodeGen/AVR/avr-rust-issue-123.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O1 < %s -march=avr | FileCheck %s
+; RUN: llc -O1 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; This test ensures that the Select8/Select16 expansion
 ; pass inserts an unconditional branch to the previous adjacent
Index: llvm/test/CodeGen/AVR/block-address-is-in-progmem-space.ll
===================================================================
--- llvm/test/CodeGen/AVR/block-address-is-in-progmem-space.ll
+++ llvm/test/CodeGen/AVR/block-address-is-in-progmem-space.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mcpu=atmega328 < %s -march=avr | FileCheck %s
+; RUN: llc -mcpu=atmega328 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; This test verifies that the pointer to a basic block
 ; should always be a pointer in address space 1.
Index: llvm/test/CodeGen/AVR/branch-relaxation-long.ll
===================================================================
--- llvm/test/CodeGen/AVR/branch-relaxation-long.ll
+++ llvm/test/CodeGen/AVR/branch-relaxation-long.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; CHECK-LABEL: relax_to_jmp:
 ; CHECK: cpi     r{{[0-9]+}}, 0
Index: llvm/test/CodeGen/AVR/branch-relaxation.ll
===================================================================
--- llvm/test/CodeGen/AVR/branch-relaxation.ll
+++ llvm/test/CodeGen/AVR/branch-relaxation.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; CHECK-LABEL: relax_breq
 ; CHECK: cpi     r{{[0-9]+}}, 0
Index: llvm/test/CodeGen/AVR/call.ll
===================================================================
--- llvm/test/CodeGen/AVR/call.ll
+++ llvm/test/CodeGen/AVR/call.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mattr=avr6 | FileCheck %s
+; RUN: llc < %s -march=avr -mattr=avr6 -verify-machineinstrs | FileCheck %s
 
 ; TODO: test returning byval structs
 
Index: llvm/test/CodeGen/AVR/calling-conv/c/basic.ll
===================================================================
--- llvm/test/CodeGen/AVR/calling-conv/c/basic.ll
+++ llvm/test/CodeGen/AVR/calling-conv/c/basic.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; CHECK-LABEL: ret_void_args_i8
 define void @ret_void_args_i8(i8 %a) {
Index: llvm/test/CodeGen/AVR/calling-conv/c/basic_aggr.ll
===================================================================
--- llvm/test/CodeGen/AVR/calling-conv/c/basic_aggr.ll
+++ llvm/test/CodeGen/AVR/calling-conv/c/basic_aggr.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; CHECK-LABEL: ret_void_args_struct_i8_i32
 define void @ret_void_args_struct_i8_i32({ i8, i32 } %a) {
Index: llvm/test/CodeGen/AVR/calling-conv/c/call.ll
===================================================================
--- llvm/test/CodeGen/AVR/calling-conv/c/call.ll
+++ llvm/test/CodeGen/AVR/calling-conv/c/call.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 declare void @ret_void_args_i8(i8 %a)
 declare void @ret_void_args_i8_i32(i8 %a, i32 %b)
Index: llvm/test/CodeGen/AVR/calling-conv/c/call_aggr.ll
===================================================================
--- llvm/test/CodeGen/AVR/calling-conv/c/call_aggr.ll
+++ llvm/test/CodeGen/AVR/calling-conv/c/call_aggr.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 declare void @ret_void_args_struct_i8_i32({ i8, i32 } %a)
 declare void @ret_void_args_struct_i8_i8_i8_i8({ i8, i8, i8, i8 } %a)
Index: llvm/test/CodeGen/AVR/calling-conv/c/return.ll
===================================================================
--- llvm/test/CodeGen/AVR/calling-conv/c/return.ll
+++ llvm/test/CodeGen/AVR/calling-conv/c/return.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; CHECK-LABEL: ret_i8
 define i8 @ret_i8() {
Index: llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
===================================================================
--- llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
+++ llvm/test/CodeGen/AVR/calling-conv/c/return_aggr.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; CHECK-LABEL: ret_struct_i8_i16_i8
 define { i8, i16, i8 } @ret_struct_i8_i16_i8() {
Index: llvm/test/CodeGen/AVR/calling-conv/c/stack.ll
===================================================================
--- llvm/test/CodeGen/AVR/calling-conv/c/stack.ll
+++ llvm/test/CodeGen/AVR/calling-conv/c/stack.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; CHECK-LABEL: ret_void_args_i64_i64_i32
 define void @ret_void_args_i64_i64_i32(i64 %a, i64 %b, i32 %c) {
Index: llvm/test/CodeGen/AVR/clear-bss.ll
===================================================================
--- llvm/test/CodeGen/AVR/clear-bss.ll
+++ llvm/test/CodeGen/AVR/clear-bss.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; CHECK: .globl __do_clear_bss
 @zeroed = internal constant [3 x i8] zeroinitializer
Index: llvm/test/CodeGen/AVR/cmp.ll
===================================================================
--- llvm/test/CodeGen/AVR/cmp.ll
+++ llvm/test/CodeGen/AVR/cmp.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 declare void @f1(i8)
 declare void @f2(i8)
Index: llvm/test/CodeGen/AVR/com.ll
===================================================================
--- llvm/test/CodeGen/AVR/com.ll
+++ llvm/test/CodeGen/AVR/com.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr -verify-machineinstrs | FileCheck %s
 
 define i8 @com8(i8 %x) {
 ; CHECK-LABEL: com8:
Index: llvm/test/CodeGen/AVR/copy-data-to-ram.ll
===================================================================
--- llvm/test/CodeGen/AVR/copy-data-to-ram.ll
+++ llvm/test/CodeGen/AVR/copy-data-to-ram.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; CHECK: .globl __do_copy_data
 @str = internal global [3 x i8] c"foo"
Index: llvm/test/CodeGen/AVR/ctlz.ll
===================================================================
--- llvm/test/CodeGen/AVR/ctlz.ll
+++ llvm/test/CodeGen/AVR/ctlz.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 define i8 @count_leading_zeros(i8) unnamed_addr {
 entry-block:
Index: llvm/test/CodeGen/AVR/ctors.ll
===================================================================
--- llvm/test/CodeGen/AVR/ctors.ll
+++ llvm/test/CodeGen/AVR/ctors.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 define void @do_nothing() addrspace(1) #0 {
 ; CHECK-LABEL: do_nothing:
Index: llvm/test/CodeGen/AVR/ctpop.ll
===================================================================
--- llvm/test/CodeGen/AVR/ctpop.ll
+++ llvm/test/CodeGen/AVR/ctpop.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 define i8 @count_population(i8) unnamed_addr {
 entry-block:
Index: llvm/test/CodeGen/AVR/cttz.ll
===================================================================
--- llvm/test/CodeGen/AVR/cttz.ll
+++ llvm/test/CodeGen/AVR/cttz.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 define i8 @count_trailing_zeros(i8) unnamed_addr {
 entry-block:
Index: llvm/test/CodeGen/AVR/directmem.ll
===================================================================
--- llvm/test/CodeGen/AVR/directmem.ll
+++ llvm/test/CodeGen/AVR/directmem.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=sram,addsubiw < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=sram,addsubiw < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 @char = common global i8 0
 @char.array = common global [3 x i8] zeroinitializer
Index: llvm/test/CodeGen/AVR/div.ll
===================================================================
--- llvm/test/CodeGen/AVR/div.ll
+++ llvm/test/CodeGen/AVR/div.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=mul,movw < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=mul,movw < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; Unsigned 8-bit division
 define i8 @udiv8(i8 %a, i8 %b) {
Index: llvm/test/CodeGen/AVR/dynalloca.ll
===================================================================
--- llvm/test/CodeGen/AVR/dynalloca.ll
+++ llvm/test/CodeGen/AVR/dynalloca.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 declare void @foo(i16*, i16*, i8*)
 
Index: llvm/test/CodeGen/AVR/eor.ll
===================================================================
--- llvm/test/CodeGen/AVR/eor.ll
+++ llvm/test/CodeGen/AVR/eor.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; Tests for the exclusive OR operation.
 
Index: llvm/test/CodeGen/AVR/expand-integer-failure.ll
===================================================================
--- llvm/test/CodeGen/AVR/expand-integer-failure.ll
+++ llvm/test/CodeGen/AVR/expand-integer-failure.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; Causes an assertion error
 ; Assertion failed: (Lo.getValueType() == TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&
Index: llvm/test/CodeGen/AVR/features/avr-tiny.ll
===================================================================
--- llvm/test/CodeGen/AVR/features/avr-tiny.ll
+++ llvm/test/CodeGen/AVR/features/avr-tiny.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avrtiny -O0 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avrtiny -O0 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 define i16 @reg_copy16(i16, i16 %a) {
 ; CHECK-LABEL: reg_copy16
Index: llvm/test/CodeGen/AVR/features/avr25.ll
===================================================================
--- llvm/test/CodeGen/AVR/features/avr25.ll
+++ llvm/test/CodeGen/AVR/features/avr25.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr25 -O0 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr25 -O0 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; On most cores, the 16-bit 'MOVW' instruction can be used
 define i16 @reg_copy16(i16, i16 %a) {
Index: llvm/test/CodeGen/AVR/features/xmega_io.ll
===================================================================
--- llvm/test/CodeGen/AVR/features/xmega_io.ll
+++ llvm/test/CodeGen/AVR/features/xmega_io.ll
@@ -1,19 +1,19 @@
-; RUN: llc -O0 < %s -march=avr -mcpu avrxmega1 | FileCheck %s -check-prefix=XMEGA
-; RUN: llc -O0 < %s -march=avr -mcpu avrxmega2 | FileCheck %s -check-prefix=XMEGA
-; RUN: llc -O0 < %s -march=avr -mcpu avrxmega3 | FileCheck %s -check-prefix=XMEGA
-; RUN: llc -O0 < %s -march=avr -mcpu avrxmega4 | FileCheck %s -check-prefix=XMEGA
-; RUN: llc -O0 < %s -march=avr -mcpu avrxmega5 | FileCheck %s -check-prefix=XMEGA
-; RUN: llc -O0 < %s -march=avr -mcpu avrxmega6 | FileCheck %s -check-prefix=XMEGA
-; RUN: llc -O0 < %s -march=avr -mcpu avrxmega7 | FileCheck %s -check-prefix=XMEGA
-; RUN: llc -O0 < %s -march=avr -mcpu avr2 | FileCheck %s -check-prefix=AVR
-; RUN: llc -O0 < %s -march=avr -mcpu avr25 | FileCheck %s -check-prefix=AVR
-; RUN: llc -O0 < %s -march=avr -mcpu avr3 | FileCheck %s -check-prefix=AVR
-; RUN: llc -O0 < %s -march=avr -mcpu avr31 | FileCheck %s -check-prefix=AVR
-; RUN: llc -O0 < %s -march=avr -mcpu avr35 | FileCheck %s -check-prefix=AVR
-; RUN: llc -O0 < %s -march=avr -mcpu avr4 | FileCheck %s -check-prefix=AVR
-; RUN: llc -O0 < %s -march=avr -mcpu avr5 | FileCheck %s -check-prefix=AVR
-; RUN: llc -O0 < %s -march=avr -mcpu avr51 | FileCheck %s -check-prefix=AVR
-; RUN: llc -O0 < %s -march=avr -mcpu avr6 | FileCheck %s -check-prefix=AVR
+; RUN: llc -O0 < %s -march=avr -mcpu avrxmega1 -verify-machineinstrs | FileCheck %s -check-prefix=XMEGA
+; RUN: llc -O0 < %s -march=avr -mcpu avrxmega2 -verify-machineinstrs | FileCheck %s -check-prefix=XMEGA
+; RUN: llc -O0 < %s -march=avr -mcpu avrxmega3 -verify-machineinstrs | FileCheck %s -check-prefix=XMEGA
+; RUN: llc -O0 < %s -march=avr -mcpu avrxmega4 -verify-machineinstrs | FileCheck %s -check-prefix=XMEGA
+; RUN: llc -O0 < %s -march=avr -mcpu avrxmega5 -verify-machineinstrs | FileCheck %s -check-prefix=XMEGA
+; RUN: llc -O0 < %s -march=avr -mcpu avrxmega6 -verify-machineinstrs | FileCheck %s -check-prefix=XMEGA
+; RUN: llc -O0 < %s -march=avr -mcpu avrxmega7 -verify-machineinstrs | FileCheck %s -check-prefix=XMEGA
+; RUN: llc -O0 < %s -march=avr -mcpu avr2 -verify-machineinstrs | FileCheck %s -check-prefix=AVR
+; RUN: llc -O0 < %s -march=avr -mcpu avr25 -verify-machineinstrs | FileCheck %s -check-prefix=AVR
+; RUN: llc -O0 < %s -march=avr -mcpu avr3 -verify-machineinstrs | FileCheck %s -check-prefix=AVR
+; RUN: llc -O0 < %s -march=avr -mcpu avr31 -verify-machineinstrs | FileCheck %s -check-prefix=AVR
+; RUN: llc -O0 < %s -march=avr -mcpu avr35 -verify-machineinstrs | FileCheck %s -check-prefix=AVR
+; RUN: llc -O0 < %s -march=avr -mcpu avr4 -verify-machineinstrs | FileCheck %s -check-prefix=AVR
+; RUN: llc -O0 < %s -march=avr -mcpu avr5 -verify-machineinstrs | FileCheck %s -check-prefix=AVR
+; RUN: llc -O0 < %s -march=avr -mcpu avr51 -verify-machineinstrs | FileCheck %s -check-prefix=AVR
+; RUN: llc -O0 < %s -march=avr -mcpu avr6 -verify-machineinstrs | FileCheck %s -check-prefix=AVR
 
 define i8 @read8_low_io() {
 ; CHECK-LABEL: read8_low_io
Index: llvm/test/CodeGen/AVR/frame.ll
===================================================================
--- llvm/test/CodeGen/AVR/frame.ll
+++ llvm/test/CodeGen/AVR/frame.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=mul < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=mul < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 declare float @dsin(float)
 declare float @dcos(float)
Index: llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll
===================================================================
--- llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll
+++ llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mattr=avr6 | FileCheck %s
+; RUN: llc < %s -march=avr -mattr=avr6 -verify-machineinstrs | FileCheck %s
 
 %str_slice = type { i8*, i16 }
 %Machine = type { i16, [0 x i8], i16, [0 x i8], [16 x i8], [0 x i8] }
Index: llvm/test/CodeGen/AVR/hardware-mul.ll
===================================================================
--- llvm/test/CodeGen/AVR/hardware-mul.ll
+++ llvm/test/CodeGen/AVR/hardware-mul.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=mul,movw < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=mul,movw < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; Tests lowering of multiplication to hardware instructions.
 
Index: llvm/test/CodeGen/AVR/high-pressure-on-ptrregs.ll
===================================================================
--- llvm/test/CodeGen/AVR/high-pressure-on-ptrregs.ll
+++ llvm/test/CodeGen/AVR/high-pressure-on-ptrregs.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; This tests how LLVM handles IR which puts very high
 ; presure on the PTRREGS class for the register allocator.
Index: llvm/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll
===================================================================
--- llvm/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll
+++ llvm/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=lpm,lpmw < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=lpm,lpmw < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 @callbackPtr = common global void (i16) addrspace(1)* null, align 8
 @myValuePtr = common global i16* null, align 8
Index: llvm/test/CodeGen/AVR/impossible-reg-to-reg-copy.ll
===================================================================
--- llvm/test/CodeGen/AVR/impossible-reg-to-reg-copy.ll
+++ llvm/test/CodeGen/AVR/impossible-reg-to-reg-copy.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; Test case for an assertion error.
 ;
Index: llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
===================================================================
--- llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
+++ llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
@@ -1,4 +1,4 @@
-; RUN: not llc < %s -march=avr -no-integrated-as 2>&1 | FileCheck %s
+; RUN: not llc < %s -march=avr -no-integrated-as -verify-machineinstrs 2>&1 | FileCheck %s
 
 define void @foo(i16 %a) {
   ; CHECK: error: invalid operand in inline asm: 'jl ${0:l}'
Index: llvm/test/CodeGen/AVR/inline-asm/inline-asm.ll
===================================================================
--- llvm/test/CodeGen/AVR/inline-asm/inline-asm.ll
+++ llvm/test/CodeGen/AVR/inline-asm/inline-asm.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mattr=movw -no-integrated-as | FileCheck %s
+; RUN: llc < %s -march=avr -mattr=movw -no-integrated-as -verify-machineinstrs | FileCheck %s
 ; XFAIL: *
 
 ; CHECK-LABEL: no_operands:
Index: llvm/test/CodeGen/AVR/inline-asm/inline-asm2.ll
===================================================================
--- llvm/test/CodeGen/AVR/inline-asm/inline-asm2.ll
+++ llvm/test/CodeGen/AVR/inline-asm/inline-asm2.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -no-integrated-as | FileCheck %s
+; RUN: llc < %s -march=avr -no-integrated-as -verify-machineinstrs | FileCheck %s
 
 ; CHECK-LABEL: foo
 define void @foo(i16 %a) {
Index: llvm/test/CodeGen/AVR/inline-asm/inline-asm3.ll
===================================================================
--- llvm/test/CodeGen/AVR/inline-asm/inline-asm3.ll
+++ llvm/test/CodeGen/AVR/inline-asm/inline-asm3.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr -verify-machineinstrs | FileCheck %s
 
 define void @add_r_i8(i8 signext %0, i8 signext %1) {
 ; CHECK-LABEL: add_r_i8:
Index: llvm/test/CodeGen/AVR/integration/blink.ll
===================================================================
--- llvm/test/CodeGen/AVR/integration/blink.ll
+++ llvm/test/CodeGen/AVR/integration/blink.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mcpu=atmega328p | FileCheck %s
+; RUN: llc < %s -march=avr -mcpu=atmega328p -verify-machineinstrs | FileCheck %s
 
 ; This test checks a basic 'blinking led' program.
 ; It is written for the ATmega328P
Index: llvm/test/CodeGen/AVR/interrupts.ll
===================================================================
--- llvm/test/CodeGen/AVR/interrupts.ll
+++ llvm/test/CodeGen/AVR/interrupts.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 @count = global i8 0
 
Index: llvm/test/CodeGen/AVR/intrinsics/named-reg-alloc.ll
===================================================================
--- llvm/test/CodeGen/AVR/intrinsics/named-reg-alloc.ll
+++ llvm/test/CodeGen/AVR/intrinsics/named-reg-alloc.ll
@@ -1,4 +1,4 @@
-; RUN: not --crash llc -O0 < %s -march=avr 2>&1 | FileCheck %s
+; RUN: not --crash llc -O0 < %s -march=avr -verify-machineinstrs 2>&1 | FileCheck %s
 
 define void @foo() {
 entry:
Index: llvm/test/CodeGen/AVR/intrinsics/named-reg-special.ll
===================================================================
--- llvm/test/CodeGen/AVR/intrinsics/named-reg-special.ll
+++ llvm/test/CodeGen/AVR/intrinsics/named-reg-special.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 < %s -march=avr | FileCheck %s
+; RUN: llc -O0 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; CHECK-LABEL: read_sp:
 ; CHECK: in r24, 61
Index: llvm/test/CodeGen/AVR/intrinsics/stacksave-restore.ll
===================================================================
--- llvm/test/CodeGen/AVR/intrinsics/stacksave-restore.ll
+++ llvm/test/CodeGen/AVR/intrinsics/stacksave-restore.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 < %s -march=avr | FileCheck %s
+; RUN: llc -O0 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; CHECK-LABEL: foo
 define void @foo() {
Index: llvm/test/CodeGen/AVR/io.ll
===================================================================
--- llvm/test/CodeGen/AVR/io.ll
+++ llvm/test/CodeGen/AVR/io.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 define i8 @read8() {
 ; CHECK-LABEL: read8
Index: llvm/test/CodeGen/AVR/issue-cannot-select-bswap.ll
===================================================================
--- llvm/test/CodeGen/AVR/issue-cannot-select-bswap.ll
+++ llvm/test/CodeGen/AVR/issue-cannot-select-bswap.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 declare i16 @llvm.bswap.i16(i16)
 
Index: llvm/test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll
===================================================================
--- llvm/test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll
+++ llvm/test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mcpu=atmega328 | FileCheck %s
+; RUN: llc < %s -march=avr -mcpu=atmega328 -verify-machineinstrs | FileCheck %s
 
 ; This test case is designed to trigger a bug caused by the register
 ; allocator not handling the case where a target generates a load/store with
Index: llvm/test/CodeGen/AVR/jmp-long.ll
===================================================================
--- llvm/test/CodeGen/AVR/jmp-long.ll
+++ llvm/test/CodeGen/AVR/jmp-long.ll
@@ -1,4 +1,5 @@
-; RUN: llc -filetype=obj -march avr -mattr=jmpcall < %s | llvm-objdump -dr --mattr=jmpcall - | FileCheck %s
+; RUN: llc -filetype=obj -march avr -mattr=jmpcall < %s -verify-machineinstrs \
+; RUN:     | llvm-objdump -dr --mattr=jmpcall - | FileCheck %s
 
 ; Test the fix in https://reviews.llvm.org/D78459.
 ; Long branches (that use jmp instead of rjmp) were broken: the jump was to a
Index: llvm/test/CodeGen/AVR/large-return-size.ll
===================================================================
--- llvm/test/CodeGen/AVR/large-return-size.ll
+++ llvm/test/CodeGen/AVR/large-return-size.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 define void @call_more_than_64_bits() {
 ; CHECK-LABEL: call_more_than_64_bits
 entry-block:
Index: llvm/test/CodeGen/AVR/lower-formal-args-struct-return.ll
===================================================================
--- llvm/test/CodeGen/AVR/lower-formal-args-struct-return.ll
+++ llvm/test/CodeGen/AVR/lower-formal-args-struct-return.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; This test ensures that the backend can lower returns of struct values.
 ; It does not check how these are lowered.
Index: llvm/test/CodeGen/AVR/lower-formal-arguments-assertion.ll
===================================================================
--- llvm/test/CodeGen/AVR/lower-formal-arguments-assertion.ll
+++ llvm/test/CodeGen/AVR/lower-formal-arguments-assertion.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 define void @foo(i1) {
 ; CHECK-LABEL: foo:
Index: llvm/test/CodeGen/AVR/neg.ll
===================================================================
--- llvm/test/CodeGen/AVR/neg.ll
+++ llvm/test/CodeGen/AVR/neg.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=avr | FileCheck %s
+; RUN: llc < %s -mtriple=avr -verify-machineinstrs | FileCheck %s
 
 define i8 @neg8(i8 %x) {
 ; CHECK-LABEL: neg8:
Index: llvm/test/CodeGen/AVR/no-print-operand-twice.ll
===================================================================
--- llvm/test/CodeGen/AVR/no-print-operand-twice.ll
+++ llvm/test/CodeGen/AVR/no-print-operand-twice.ll
@@ -1,4 +1,4 @@
-; RUN: llc -no-integrated-as -march=avr < %s | FileCheck %s
+; RUN: llc -no-integrated-as -march=avr < %s -verify-machineinstrs | FileCheck %s
 
 define void @test() {
 entry:
Index: llvm/test/CodeGen/AVR/or.ll
===================================================================
--- llvm/test/CodeGen/AVR/or.ll
+++ llvm/test/CodeGen/AVR/or.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 define i8 @or8_reg_reg(i8 %a, i8 %b) {
 ; CHECK-LABEL: or8_reg_reg:
Index: llvm/test/CodeGen/AVR/pre-schedule.ll
===================================================================
--- llvm/test/CodeGen/AVR/pre-schedule.ll
+++ llvm/test/CodeGen/AVR/pre-schedule.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 target triple = "avr-unknown-unknown"
 
 ; The case illustrate DAG schedular may pre-schedule the node has
Index: llvm/test/CodeGen/AVR/progmem-extended.ll
===================================================================
--- llvm/test/CodeGen/AVR/progmem-extended.ll
+++ llvm/test/CodeGen/AVR/progmem-extended.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mattr=movw,lpmx | FileCheck %s
+; RUN: llc < %s -march=avr -mattr=movw,lpmx -verify-machineinstrs | FileCheck %s
 ; XFAIL: *
 
 # Wide LPM is currently unimplemented in the pseudo expansion pass.
Index: llvm/test/CodeGen/AVR/progmem.ll
===================================================================
--- llvm/test/CodeGen/AVR/progmem.ll
+++ llvm/test/CodeGen/AVR/progmem.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mattr=movw,lpm | FileCheck %s
+; RUN: llc < %s -march=avr -mattr=movw,lpm -verify-machineinstrs | FileCheck %s
 ; XFAIL: *
 
 ; Tests the standard LPM instruction
Index: llvm/test/CodeGen/AVR/rem.ll
===================================================================
--- llvm/test/CodeGen/AVR/rem.ll
+++ llvm/test/CodeGen/AVR/rem.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=mul,movw < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=mul,movw < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; Unsigned 8-bit remision
 define i8 @urem8(i8 %a, i8 %b) {
Index: llvm/test/CodeGen/AVR/return.ll
===================================================================
--- llvm/test/CodeGen/AVR/return.ll
+++ llvm/test/CodeGen/AVR/return.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6,sram < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6,sram < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ;TODO: test returning byval structs
 ; TODO: test naked functions
Index: llvm/test/CodeGen/AVR/rot.ll
===================================================================
--- llvm/test/CodeGen/AVR/rot.ll
+++ llvm/test/CodeGen/AVR/rot.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; Bit rotation tests.
 
Index: llvm/test/CodeGen/AVR/runtime-trig.ll
===================================================================
--- llvm/test/CodeGen/AVR/runtime-trig.ll
+++ llvm/test/CodeGen/AVR/runtime-trig.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; Checks that `sin` and `cos` nodes are expanded into calls to
 ; the `sin` and `cos` runtime library functions.
Index: llvm/test/CodeGen/AVR/rust-avr-bug-112.ll
===================================================================
--- llvm/test/CodeGen/AVR/rust-avr-bug-112.ll
+++ llvm/test/CodeGen/AVR/rust-avr-bug-112.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; The avr-rust bug can be found here:
 ; https://github.com/avr-rust/rust/issues/112
Index: llvm/test/CodeGen/AVR/rust-avr-bug-37.ll
===================================================================
--- llvm/test/CodeGen/AVR/rust-avr-bug-37.ll
+++ llvm/test/CodeGen/AVR/rust-avr-bug-37.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 %"fmt::Formatter" = type { i32, { i8*, void (i8*)** } }
 
Index: llvm/test/CodeGen/AVR/rust-avr-bug-95.ll
===================================================================
--- llvm/test/CodeGen/AVR/rust-avr-bug-95.ll
+++ llvm/test/CodeGen/AVR/rust-avr-bug-95.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 %"fmt::Formatter.1.77.153.229.305.381.1673" = type { [0 x i8], i32, [0 x i8], i32, [0 x i8], i8, [0 x i8], %"option::Option<usize>.0.76.152.228.304.380.1672", [0 x i8], %"option::Option<usize>.0.76.152.228.304.380.1672", [0 x i8], { {}*, {}* }, [0 x i8], { i8*, i8* }, [0 x i8], { [0 x { i8*, i8* }]*, i16 }, [0 x i8] }
 %"option::Option<usize>.0.76.152.228.304.380.1672" = type { [0 x i8], i8, [2 x i8] }
Index: llvm/test/CodeGen/AVR/rust-avr-bug-99.ll
===================================================================
--- llvm/test/CodeGen/AVR/rust-avr-bug-99.ll
+++ llvm/test/CodeGen/AVR/rust-avr-bug-99.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr -mcpu=avr5 | FileCheck %s
+; RUN: llc < %s -march=avr -mcpu=avr5 -verify-machineinstrs | FileCheck %s
 
 ; The original reason for this failure is that the BranchFolderPass disables liveness
 ; tracking unless you override the trackLivenessAfterRegAlloc function and return true.
Index: llvm/test/CodeGen/AVR/rust-trait-object.ll
===================================================================
--- llvm/test/CodeGen/AVR/rust-trait-object.ll
+++ llvm/test/CodeGen/AVR/rust-trait-object.ll
@@ -1,6 +1,7 @@
-; RUN: llc < %s -march=avr -filetype=asm | FileCheck %s -check-prefix=CHECK-ASM
-; RUN: llc < %s -march=avr -filetype=obj | llvm-objdump -Dr - \
-; RUN:                                   | FileCheck %s -check-prefix=CHECK-OBJ
+; RUN: llc < %s -march=avr -filetype=asm -verify-machineinstrs \
+; RUN:     | FileCheck %s -check-prefix=CHECK-ASM
+; RUN: llc < %s -march=avr -filetype=obj -verify-machineinstrs \
+; RUN:     | llvm-objdump -Dr - | FileCheck %s -check-prefix=CHECK-OBJ
 
 ; Somewhat pruned test case from rustc using trait objects
 
Index: llvm/test/CodeGen/AVR/sections.ll
===================================================================
--- llvm/test/CodeGen/AVR/sections.ll
+++ llvm/test/CodeGen/AVR/sections.ll
@@ -1,10 +1,10 @@
-; RUN: llc < %s -march=avr --mcpu=atxmega384d3 \
+; RUN: llc < %s -march=avr --mcpu=atxmega384d3 -verify-machineinstrs \
 ; RUN:     | FileCheck --check-prefixes=CHECK,NOSECTIONS %s
-; RUN: llc -function-sections -data-sections < %s -march=avr --mcpu=atxmega384d3 \
+; RUN: llc -function-sections -data-sections < %s -march=avr --mcpu=atxmega384d3 -verify-machineinstrs \
 ; RUN:     | FileCheck --check-prefixes=CHECK,SECTIONS %s
-; RUN: not llc -function-sections -data-sections < %s -march=avr --mcpu=at90s8515 2>&1 \
+; RUN: not llc -function-sections -data-sections < %s -march=avr --mcpu=at90s8515 -verify-machineinstrs 2>&1 \
 ; RUN:     | FileCheck --check-prefixes=CHECK-8515 %s
-; RUN: not llc -function-sections -data-sections < %s -march=avr --mcpu=attiny40 2>&1 \
+; RUN: not llc -function-sections -data-sections < %s -march=avr --mcpu=attiny40 -verify-machineinstrs 2>&1 \
 ; RUN:     | FileCheck --check-prefixes=CHECK-tiny40 %s
 
 ; Test that functions (in address space 1) are not considered .progmem data.
Index: llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll
===================================================================
--- llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll
+++ llvm/test/CodeGen/AVR/select-must-add-unconditional-jump.ll
@@ -1,4 +1,5 @@
-; RUN: llc -march=avr -print-after=finalize-isel -cgp-freq-ratio-to-skip-merge=10 < %s 2>&1 | FileCheck %s
+; RUN: llc -march=avr -print-after=finalize-isel -cgp-freq-ratio-to-skip-merge=10 < %s \
+; RUN:     2>&1 -verify-machineinstrs | FileCheck %s
 
 ; Because `switch` seems to trigger Machine Basic Blocks to be ordered
 ; in a different order than they were constructed, this exposes an
Index: llvm/test/CodeGen/AVR/sext.ll
===================================================================
--- llvm/test/CodeGen/AVR/sext.ll
+++ llvm/test/CodeGen/AVR/sext.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; sext R17:R16, R13
 ; mov r16, r13
Index: llvm/test/CodeGen/AVR/shift-expand.ll
===================================================================
--- llvm/test/CodeGen/AVR/shift-expand.ll
+++ llvm/test/CodeGen/AVR/shift-expand.ll
@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -avr-shift-expand -S %s -o - | FileCheck %s
+; RUN: opt -avr-shift-expand -S %s -verify-machineinstrs -o - | FileCheck %s
 
 ; The avr-shift-expand pass expands large shifts with a non-constant shift
 ; amount to a loop. These loops avoid generating a (non-existing) builtin such
Index: llvm/test/CodeGen/AVR/sign-extension.ll
===================================================================
--- llvm/test/CodeGen/AVR/sign-extension.ll
+++ llvm/test/CodeGen/AVR/sign-extension.ll
@@ -1,4 +1,4 @@
-; RUN: llc -march=avr < %s | FileCheck %s
+; RUN: llc -march=avr -verify-machineinstrs < %s | FileCheck %s
 
 define i8 @sign_extended_1_to_8(i1) {
 ; CHECK-LABEL: sign_extended_1_to_8
Index: llvm/test/CodeGen/AVR/smul-with-overflow.ll
===================================================================
--- llvm/test/CodeGen/AVR/smul-with-overflow.ll
+++ llvm/test/CodeGen/AVR/smul-with-overflow.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 define i1 @signed_multiplication_did_overflow(i8, i8) unnamed_addr {
 ; CHECK-LABEL: signed_multiplication_did_overflow:
Index: llvm/test/CodeGen/AVR/software-mul.ll
===================================================================
--- llvm/test/CodeGen/AVR/software-mul.ll
+++ llvm/test/CodeGen/AVR/software-mul.ll
@@ -1,8 +1,8 @@
-; RUN: llc -mattr=avr6,-mul < %s -march=avr | FileCheck %s
-; RUN: llc -mcpu=attiny85 < %s -march=avr | FileCheck %s
-; RUN: llc -mcpu=ata5272 < %s -march=avr | FileCheck %s
-; RUN: llc -mcpu=attiny861a < %s -march=avr | FileCheck %s
-; RUN: llc -mcpu=at90usb82 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6,-mul < %s -march=avr -verify-machineinstrs | FileCheck %s
+; RUN: llc -mcpu=attiny85 < %s -march=avr -verify-machineinstrs | FileCheck %s
+; RUN: llc -mcpu=ata5272 < %s -march=avr -verify-machineinstrs | FileCheck %s
+; RUN: llc -mcpu=attiny861a < %s -march=avr -verify-machineinstrs | FileCheck %s
+; RUN: llc -mcpu=at90usb82 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; Tests lowering of multiplication to compiler support routines.
 
Index: llvm/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
===================================================================
--- llvm/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
+++ llvm/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O0 < %s -march=avr | FileCheck %s
+; RUN: llc -O0 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 define i32 @std_ldd_overflow() {
   %src = alloca [4 x i8]
Index: llvm/test/CodeGen/AVR/store-undef.ll
===================================================================
--- llvm/test/CodeGen/AVR/store-undef.ll
+++ llvm/test/CodeGen/AVR/store-undef.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; This test checks that we can successfully lower a store
 ; to an undefined pointer.
Index: llvm/test/CodeGen/AVR/store.ll
===================================================================
--- llvm/test/CodeGen/AVR/store.ll
+++ llvm/test/CodeGen/AVR/store.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6,sram < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6,sram < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 define void @store8(i8* %x, i8 %y) {
 ; CHECK-LABEL: store8:
Index: llvm/test/CodeGen/AVR/struct.ll
===================================================================
--- llvm/test/CodeGen/AVR/struct.ll
+++ llvm/test/CodeGen/AVR/struct.ll
@@ -1,6 +1,8 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=avr < %s | FileCheck %s --check-prefix=CHECKA
-; RUN: llc -mtriple=avr -mattr=+movw < %s | FileCheck %s --check-prefix=CHECKB
+; RUN: llc -mtriple=avr < %s -verify-machineinstrs \
+; RUN:     | FileCheck %s --check-prefix=CHECKA
+; RUN: llc -mtriple=avr -mattr=+movw < %s -verify-machineinstrs \
+; RUN:     | FileCheck %s --check-prefix=CHECKB
 
 %struct.s10 = type { i16, i16, i16, i16, i16 }
 %struct.s06 = type { i16, i16, i16 }
Index: llvm/test/CodeGen/AVR/sub.ll
===================================================================
--- llvm/test/CodeGen/AVR/sub.ll
+++ llvm/test/CodeGen/AVR/sub.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 define i8 @sub8_reg_reg(i8 %a, i8 %b) {
 ; CHECK-LABEL: sub8_reg_reg:
Index: llvm/test/CodeGen/AVR/trunc.ll
===================================================================
--- llvm/test/CodeGen/AVR/trunc.ll
+++ llvm/test/CodeGen/AVR/trunc.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 define i8 @trunc8_loreg(i16 %x, i16 %y) {
 ; CHECK-LABEL: trunc8_loreg:
Index: llvm/test/CodeGen/AVR/umul-with-overflow.ll
===================================================================
--- llvm/test/CodeGen/AVR/umul-with-overflow.ll
+++ llvm/test/CodeGen/AVR/umul-with-overflow.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=avr6 < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=avr6 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 define i1 @unsigned_multiplication_did_overflow(i8, i8) unnamed_addr {
 ; CHECK-LABEL: unsigned_multiplication_did_overflow:
Index: llvm/test/CodeGen/AVR/umul.with.overflow.i16-bug.ll
===================================================================
--- llvm/test/CodeGen/AVR/umul.with.overflow.i16-bug.ll
+++ llvm/test/CodeGen/AVR/umul.with.overflow.i16-bug.ll
@@ -1,4 +1,4 @@
-; RUN: llc -O1 < %s -march=avr | FileCheck %s
+; RUN: llc -O1 < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.9"
Index: llvm/test/CodeGen/AVR/unaligned-atomic-loads.ll
===================================================================
--- llvm/test/CodeGen/AVR/unaligned-atomic-loads.ll
+++ llvm/test/CodeGen/AVR/unaligned-atomic-loads.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=addsubiw < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=addsubiw < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; This verifies that the middle end can handle an unaligned atomic load.
 ;
Index: llvm/test/CodeGen/AVR/varargs.ll
===================================================================
--- llvm/test/CodeGen/AVR/varargs.ll
+++ llvm/test/CodeGen/AVR/varargs.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mattr=sram,movw,addsubiw < %s -march=avr | FileCheck %s
+; RUN: llc -mattr=sram,movw,addsubiw < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 declare void @llvm.va_start(i8*)
 declare i16 @vsprintf(i8* nocapture, i8* nocapture, i8*)
Index: llvm/test/CodeGen/AVR/xor.ll
===================================================================
--- llvm/test/CodeGen/AVR/xor.ll
+++ llvm/test/CodeGen/AVR/xor.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 define i8 @xor8_reg_reg(i8 %a, i8 %b) {
 ; CHECK-LABEL: xor8_reg_reg:
Index: llvm/test/CodeGen/AVR/zext.ll
===================================================================
--- llvm/test/CodeGen/AVR/zext.ll
+++ llvm/test/CodeGen/AVR/zext.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=avr | FileCheck %s
+; RUN: llc < %s -march=avr -verify-machineinstrs | FileCheck %s
 
 ; zext R25:R24, R24
 ; eor R25, R25