diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -176,6 +176,7 @@
 
 // Floating point registers
 let RegAltNameIndices = [ABIRegAltName] in {
+  let CostPerUse = [0, 1] in {
   def F0_H  : RISCVReg16<0, "f0", ["ft0"]>, DwarfRegNum<[32]>;
   def F1_H  : RISCVReg16<1, "f1", ["ft1"]>, DwarfRegNum<[33]>;
   def F2_H  : RISCVReg16<2, "f2", ["ft2"]>, DwarfRegNum<[34]>;
@@ -184,6 +185,7 @@
   def F5_H  : RISCVReg16<5, "f5", ["ft5"]>, DwarfRegNum<[37]>;
   def F6_H  : RISCVReg16<6, "f6", ["ft6"]>, DwarfRegNum<[38]>;
   def F7_H  : RISCVReg16<7, "f7", ["ft7"]>, DwarfRegNum<[39]>;
+  }
   def F8_H  : RISCVReg16<8, "f8", ["fs0"]>, DwarfRegNum<[40]>;
   def F9_H  : RISCVReg16<9, "f9", ["fs1"]>, DwarfRegNum<[41]>;
   def F10_H : RISCVReg16<10,"f10", ["fa0"]>, DwarfRegNum<[42]>;
@@ -192,6 +194,7 @@
   def F13_H : RISCVReg16<13,"f13", ["fa3"]>, DwarfRegNum<[45]>;
   def F14_H : RISCVReg16<14,"f14", ["fa4"]>, DwarfRegNum<[46]>;
   def F15_H : RISCVReg16<15,"f15", ["fa5"]>, DwarfRegNum<[47]>;
+  let CostPerUse = [0, 1] in {
   def F16_H : RISCVReg16<16,"f16", ["fa6"]>, DwarfRegNum<[48]>;
   def F17_H : RISCVReg16<17,"f17", ["fa7"]>, DwarfRegNum<[49]>;
   def F18_H : RISCVReg16<18,"f18", ["fs2"]>, DwarfRegNum<[50]>;
@@ -208,16 +211,32 @@
   def F29_H : RISCVReg16<29,"f29", ["ft9"]>, DwarfRegNum<[61]>;
   def F30_H : RISCVReg16<30,"f30", ["ft10"]>, DwarfRegNum<[62]>;
   def F31_H : RISCVReg16<31,"f31", ["ft11"]>, DwarfRegNum<[63]>;
+  }
 
-  foreach Index = 0-31 in {
-    def F#Index#_F : RISCVReg32<!cast<RISCVReg16>("F"#Index#"_H")>,
-      DwarfRegNum<[!add(Index, 32)]>;
+  foreach Index = 0-7 in {
+    let CostPerUse = [0, 1] in {
+      def F#Index#_F : RISCVReg32<!cast<RISCVReg16>("F"#Index#"_H")>,
+        DwarfRegNum<[!add(Index, 32)]>;
+      def F#Index#_D : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_F")>,
+        DwarfRegNum<[!add(Index, 32)]>;
+    }
   }
 
-  foreach Index = 0-31 in {
+  foreach Index = 8-15 in {
+    def F#Index#_F : RISCVReg32<!cast<RISCVReg16>("F"#Index#"_H")>,
+      DwarfRegNum<[!add(Index, 32)]>;
     def F#Index#_D : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_F")>,
       DwarfRegNum<[!add(Index, 32)]>;
   }
+
+  foreach Index = 16-31 in {
+    let CostPerUse = [0, 1] in {
+      def F#Index#_F : RISCVReg32<!cast<RISCVReg16>("F"#Index#"_H")>,
+        DwarfRegNum<[!add(Index, 32)]>;
+      def F#Index#_D : RISCVReg64<!cast<RISCVReg32>("F"#Index#"_F")>,
+        DwarfRegNum<[!add(Index, 32)]>;
+    }
+  }
 }
 
 // The order of registers represents the preferred allocation sequence,
diff --git a/llvm/test/CodeGen/RISCV/machine-combiner.ll b/llvm/test/CodeGen/RISCV/machine-combiner.ll
--- a/llvm/test/CodeGen/RISCV/machine-combiner.ll
+++ b/llvm/test/CodeGen/RISCV/machine-combiner.ll
@@ -133,18 +133,18 @@
 define double @test_reassoc_big2(double %a0, double %a1, i32 %a2, double %a3, i32 %a4, double %a5) {
 ; CHECK-LABEL: test_reassoc_big2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    fadd.d fa5, fa0, fa1
-; CHECK-NEXT:    fsub.d fa4, fa3, fa2
+; CHECK-NEXT:    fadd.d ft0, fa0, fa1
+; CHECK-NEXT:    fsub.d ft1, fa3, fa2
 ; CHECK-NEXT:    fadd.d fa3, fa2, fa1
-; CHECK-NEXT:    fcvt.d.w ft0, a0
-; CHECK-NEXT:    fcvt.d.w ft1, a1
-; CHECK-NEXT:    fmul.d fa2, fa2, ft0
-; CHECK-NEXT:    fmul.d fa1, ft1, fa1
-; CHECK-NEXT:    fsub.d fa5, fa4, fa5
-; CHECK-NEXT:    fmul.d fa4, fa0, fa3
-; CHECK-NEXT:    fmul.d fa3, fa1, fa2
-; CHECK-NEXT:    fmul.d fa5, fa5, fa4
-; CHECK-NEXT:    fmul.d fa0, fa5, fa3
+; CHECK-NEXT:    fcvt.d.w fa5, a0
+; CHECK-NEXT:    fcvt.d.w fa4, a1
+; CHECK-NEXT:    fmul.d fa5, fa2, fa5
+; CHECK-NEXT:    fmul.d fa4, fa4, fa1
+; CHECK-NEXT:    fsub.d fa2, ft1, ft0
+; CHECK-NEXT:    fmul.d fa3, fa0, fa3
+; CHECK-NEXT:    fmul.d fa5, fa4, fa5
+; CHECK-NEXT:    fmul.d fa4, fa2, fa3
+; CHECK-NEXT:    fmul.d fa0, fa4, fa5
 ; CHECK-NEXT:    ret
   %cvt1 = sitofp i32 %a2 to double
   %cvt2 = sitofp i32 %a4 to double