Index: llvm/test/CodeGen/AVR/atomics/load16.ll
===================================================================
--- llvm/test/CodeGen/AVR/atomics/load16.ll
+++ llvm/test/CodeGen/AVR/atomics/load16.ll
@@ -29,12 +29,12 @@
 ; CHECK-LABEL: atomic_load_add16
 ; CHECK:      in r0, 63
 ; CHECK-NEXT: cli
-; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD:(X|Y|Z)]]
-; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD]]+1
-; CHECK-NEXT: add [[TMP1:r[0-9]+]], [[RR1]]
-; CHECK-NEXT: adc [[TMP2:r[0-9]+]], [[RR2]]
-; CHECK-NEXT: st [[RD]], [[TMP1]]
-; CHECK-NEXT: std [[RD]]+1, [[TMP2]]
+; CHECK-NEXT: ld [[RDL:r[0-9]+]], [[RR:(X|Y|Z)]]
+; CHECK-NEXT: ldd [[RDH:r[0-9]+]], [[RR]]+1
+; CHECK-NEXT: add [[RR1L:r[0-9]+]], [[RDL]]
+; CHECK-NEXT: adc [[RR1H:r[0-9]+]], [[RDH]]
+; CHECK-NEXT: st [[RR]], [[RR1L]]
+; CHECK-NEXT: std [[RR]]+1, [[RR1H]]
 ; CHECK-NEXT: out 63, r0
 define i16 @atomic_load_add16(i16* %foo) {
   %val = atomicrmw add i16* %foo, i16 13 seq_cst
@@ -44,13 +44,13 @@
 ; CHECK-LABEL: atomic_load_sub16
 ; CHECK:      in r0, 63
 ; CHECK-NEXT: cli
-; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD:(X|Y|Z)]]
-; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD]]+1
-; CHECK-NEXT: movw
-; CHECK-NEXT: sub [[TMP1:r[0-9]+]], [[IN1:r[0-9]+]]
-; CHECK-NEXT: sbc [[TMP2:r[0-9]+]], [[IN2:r[0-9]+]]
-; CHECK-NEXT: st [[RD]], [[TMP1]]
-; CHECK-NEXT: std [[RD]]+1, [[TMP2]]
+; CHECK-NEXT: ld [[RDL:r[0-9]+]], [[RR:(X|Y|Z)]]
+; CHECK-NEXT: ldd [[RDH:r[0-9]+]], [[RR]]+1
+; CHECK-NEXT: movw [[TMPL:r[0-9]+]], [[RDL]]
+; CHECK-NEXT: sub [[TMPL]],         [[RR1L:r[0-9]+]]
+; CHECK-NEXT: sbc [[TMPH:r[0-9]+]], [[RR1H:r[0-9]+]]
+; CHECK-NEXT: st [[RR]], [[TMPL]]
+; CHECK-NEXT: std [[RR]]+1, [[TMPH]]
 ; CHECK-NEXT: out 63, r0
 define i16 @atomic_load_sub16(i16* %foo) {
   %val = atomicrmw sub i16* %foo, i16 13 seq_cst
@@ -60,12 +60,12 @@
 ; CHECK-LABEL: atomic_load_and16
 ; CHECK:      in r0, 63
 ; CHECK-NEXT: cli
-; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD:(X|Y|Z)]]
-; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD]]+1
-; CHECK-NEXT: and [[TMP1:r[0-9]+]], [[RR1]]
-; CHECK-NEXT: and [[TMP2:r[0-9]+]], [[RR2]]
-; CHECK-NEXT: st [[RD]], [[TMP1]]
-; CHECK-NEXT: std [[RD]]+1, [[TMP2]]
+; CHECK-NEXT: ld [[RDL:r[0-9]+]], [[RR:(X|Y|Z)]]
+; CHECK-NEXT: ldd [[RDH:r[0-9]+]], [[RR]]+1
+; CHECK-NEXT: and [[RD1L:r[0-9]+]], [[RDL]]
+; CHECK-NEXT: and [[RD1H:r[0-9]+]], [[RDH]]
+; CHECK-NEXT: st [[RR]], [[RD1L]]
+; CHECK-NEXT: std [[RR]]+1, [[RD1H]]
 ; CHECK-NEXT: out 63, r0
 define i16 @atomic_load_and16(i16* %foo) {
   %val = atomicrmw and i16* %foo, i16 13 seq_cst
@@ -75,12 +75,12 @@
 ; CHECK-LABEL: atomic_load_or16
 ; CHECK:      in r0, 63
 ; CHECK-NEXT: cli
-; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD:(X|Y|Z)]]
-; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD]]+1
-; CHECK-NEXT: or [[TMP1:r[0-9]+]], [[RR1]]
-; CHECK-NEXT: or [[TMP2:r[0-9]+]], [[RR2]]
-; CHECK-NEXT: st [[RD]], [[TMP1]]
-; CHECK-NEXT: std [[RD]]+1, [[TMP2]]
+; CHECK-NEXT: ld [[RDL:r[0-9]+]], [[RR:(X|Y|Z)]]
+; CHECK-NEXT: ldd [[RDH:r[0-9]+]], [[RR]]+1
+; CHECK-NEXT: or [[RD1L:r[0-9]+]], [[RDL]]
+; CHECK-NEXT: or [[RD1H:r[0-9]+]], [[RDH]]
+; CHECK-NEXT: st [[RR]], [[RD1L]]
+; CHECK-NEXT: std [[RR]]+1, [[RD1H]]
 ; CHECK-NEXT: out 63, r0
 define i16 @atomic_load_or16(i16* %foo) {
   %val = atomicrmw or i16* %foo, i16 13 seq_cst
@@ -90,12 +90,12 @@
 ; CHECK-LABEL: atomic_load_xor16
 ; CHECK:      in r0, 63
 ; CHECK-NEXT: cli
-; CHECK-NEXT: ld [[RR1:r[0-9]+]], [[RD:(X|Y|Z)]]
-; CHECK-NEXT: ldd [[RR2:r[0-9]+]], [[RD]]+1
-; CHECK-NEXT: eor [[TMP1:r[0-9]+]], [[RR1]]
-; CHECK-NEXT: eor [[TMP2:r[0-9]+]], [[RR2]]
-; CHECK-NEXT: st [[RD]], [[TMP1]]
-; CHECK-NEXT: std [[RD]]+1, [[TMP2]]
+; CHECK-NEXT: ld [[RDL:r[0-9]+]], [[RR:(X|Y|Z)]]
+; CHECK-NEXT: ldd [[RDH:r[0-9]+]], [[RR]]+1
+; CHECK-NEXT: eor [[RD1L:r[0-9]+]], [[RDL]]
+; CHECK-NEXT: eor [[RD1H:r[0-9]+]], [[RDH]]
+; CHECK-NEXT: st [[RR]], [[RD1L]]
+; CHECK-NEXT: std [[RR]]+1, [[RD1H]]
 ; CHECK-NEXT: out 63, r0
 define i16 @atomic_load_xor16(i16* %foo) {
   %val = atomicrmw xor i16* %foo, i16 13 seq_cst