Index: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
===================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.h
@@ -69,6 +69,7 @@
   unsigned GetNullPtr() const;
   unsigned GetPtrAdduOp() const;
   unsigned GetPtrAddiuOp() const;
+  unsigned GetGPRMoveOp() const;
   inline bool ArePtrs64bit() const { return IsN64(); }
 
   unsigned GetEhDataReg(unsigned I) const;
Index: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
@@ -115,6 +115,10 @@
   return ArePtrs64bit() ? Mips::DADDiu : Mips::ADDiu;
 }
 
+unsigned MipsABIInfo::GetGPRMoveOp() const {
+  return ArePtrs64bit() ? Mips::OR64 : Mips::OR;
+}
+
 unsigned MipsABIInfo::GetEhDataReg(unsigned I) const {
   static const unsigned EhDataReg[] = {
     Mips::A0, Mips::A1, Mips::A2, Mips::A3
Index: llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
+++ llvm/trunk/lib/Target/Mips/MCTargetDesc/MipsTargetStreamer.cpp
@@ -766,7 +766,7 @@
   // Either store the old $gp in a register or on the stack
   if (IsReg) {
     // move $save, $gpreg
-    Inst.setOpcode(Mips::DADDu);
+    Inst.setOpcode(Mips::OR64);
     Inst.addOperand(MCOperand::createReg(RegOrOffset));
     Inst.addOperand(MCOperand::createReg(Mips::GP));
     Inst.addOperand(MCOperand::createReg(Mips::ZERO));
Index: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
@@ -548,6 +548,9 @@
 // Instruction aliases
 //===----------------------------------------------------------------------===//
 def : MipsInstAlias<"move $dst, $src",
+                    (OR64 GPR64Opnd:$dst,  GPR64Opnd:$src, ZERO_64), 1>,
+      GPR_64;
+def : MipsInstAlias<"move $dst, $src",
                     (DADDu GPR64Opnd:$dst,  GPR64Opnd:$src, ZERO_64), 1>,
       GPR_64;
 def : MipsInstAlias<"daddu $rs, $rt, $imm",
Index: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
+++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
@@ -1008,7 +1008,7 @@
   //
   // Mov $18, $31
 
-  EmitInstrRegRegReg(*STI, Mips::ADDu, Mips::S2, Mips::RA, Mips::ZERO);
+  EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);
 
   EmitSwapFPIntParams(*STI, Signature->ParamSig, LE, true);
 
Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
@@ -1570,7 +1570,12 @@
 // Instruction aliases
 //===----------------------------------------------------------------------===//
 def : MipsInstAlias<"move $dst, $src",
-                    (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
+                    (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
+      GPR_32 {
+  let AdditionalPredicates = [NotInMicroMips];
+}
+def : MipsInstAlias<"move $dst, $src",
+                    (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
       GPR_32 {
   let AdditionalPredicates = [NotInMicroMips];
 }
Index: llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp
+++ llvm/trunk/lib/Target/Mips/MipsSEFrameLowering.cpp
@@ -381,7 +381,7 @@
   unsigned SP = ABI.GetStackPtr();
   unsigned FP = ABI.GetFramePtr();
   unsigned ZERO = ABI.GetNullPtr();
-  unsigned ADDu = ABI.GetPtrAdduOp();
+  unsigned MOVE = ABI.GetGPRMoveOp();
   unsigned ADDiu = ABI.GetPtrAddiuOp();
   unsigned AND = ABI.IsN64() ? Mips::AND64 : Mips::AND;
 
@@ -491,7 +491,7 @@
   // if framepointer enabled, set it to point to the stack pointer.
   if (hasFP(MF)) {
     // Insert instruction "move $fp, $sp" at this location.
-    BuildMI(MBB, MBBI, dl, TII.get(ADDu), FP).addReg(SP).addReg(ZERO)
+    BuildMI(MBB, MBBI, dl, TII.get(MOVE), FP).addReg(SP).addReg(ZERO)
       .setMIFlag(MachineInstr::FrameSetup);
 
     // emit ".cfi_def_cfa_register $fp"
@@ -514,7 +514,7 @@
       if (hasBP(MF)) {
         // move $s7, $sp
         unsigned BP = STI.isABI_N64() ? Mips::S7_64 : Mips::S7;
-        BuildMI(MBB, MBBI, dl, TII.get(ADDu), BP)
+        BuildMI(MBB, MBBI, dl, TII.get(MOVE), BP)
           .addReg(SP)
           .addReg(ZERO);
       }
@@ -538,7 +538,7 @@
   unsigned SP = ABI.GetStackPtr();
   unsigned FP = ABI.GetFramePtr();
   unsigned ZERO = ABI.GetNullPtr();
-  unsigned ADDu = ABI.GetPtrAdduOp();
+  unsigned MOVE = ABI.GetGPRMoveOp();
 
   // if framepointer enabled, restore the stack pointer.
   if (hasFP(MF)) {
@@ -549,7 +549,7 @@
       --I;
 
     // Insert instruction "move $sp, $fp" at this location.
-    BuildMI(MBB, I, dl, TII.get(ADDu), SP).addReg(FP).addReg(ZERO);
+    BuildMI(MBB, I, dl, TII.get(MOVE), SP).addReg(FP).addReg(ZERO);
   }
 
   if (MipsFI->callsEhReturn()) {
Index: llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -88,7 +88,7 @@
       if (isMicroMips)
         Opc = Mips::MOVE16_MM;
       else
-        Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
+        Opc = Mips::OR, ZeroReg = Mips::ZERO;
     } else if (Mips::CCRRegClass.contains(SrcReg))
       Opc = Mips::CFC1;
     else if (Mips::FGR32RegClass.contains(SrcReg))
@@ -141,7 +141,7 @@
     Opc = Mips::FMOV_D64;
   else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
     if (Mips::GPR64RegClass.contains(SrcReg))
-      Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
+      Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
     else if (Mips::HI64RegClass.contains(SrcReg))
       Opc = Mips::MFHI64, SrcReg = 0;
     else if (Mips::LO64RegClass.contains(SrcReg))
Index: llvm/trunk/test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips1/valid-mips1-el.txt
@@ -58,6 +58,8 @@
 0x12 0x88 0x00 0x00 # CHECK: mflo $17
 0x06 0x75 0x20 0x46 # CHECK: mov.d $f20, $f14
 0x86 0xd8 0x00 0x46 # CHECK: mov.s $f2, $f27
+0x25 0xf0 0x80 0x00 # CHECK: move $fp, $4
+0x25 0xc8 0xc0 0x00 # CHECK: move $25, $6
 0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4
 0x21 0xc8 0xc0 0x00 # CHECK: move $25, $6
 0x00 0x48 0x9e 0x44 # CHECK: mtc1 $fp, $f9
Index: llvm/trunk/test/MC/Disassembler/Mips/mips1/valid-mips1.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips1/valid-mips1.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips1/valid-mips1.txt
@@ -16,11 +16,13 @@
 0x00 0x17 0x8b 0xc3 # CHECK: sra $17, $23, 15
 0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12
 0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4
+0x00 0x80 0xf0 0x25 # CHECK: move $fp, $4
 0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6
 0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
 0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
 0x00 0x9e 0x90 0x26 # CHECK: xor $18, $4, $fp
 0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6
+0x00 0xc0 0xc8 0x25 # CHECK: move $25, $6
 0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
 0x01 0x20 0x38 0x04 # CHECK: sllv $7, $zero, $9
 0x01 0x32 0x00 0x19 # CHECK: multu $9, $18
Index: llvm/trunk/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt
@@ -74,6 +74,8 @@
 0x86 0xd8 0x00 0x46 # CHECK: mov.s $f2, $f27
 0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4
 0x21 0xc8 0xc0 0x00 # CHECK: move $25, $6
+0x25 0xf0 0x80 0x00 # CHECK: move $fp, $4
+0x25 0xc8 0xc0 0x00 # CHECK: move $25, $6
 0x00 0x48 0x9e 0x44 # CHECK: mtc1 $fp, $f9
 0x11 0x00 0x20 0x02 # CHECK: mthi $17
 0x13 0x00 0xa0 0x03 # CHECK: mtlo $sp
Index: llvm/trunk/test/MC/Disassembler/Mips/mips2/valid-mips2.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips2/valid-mips2.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips2/valid-mips2.txt
@@ -19,6 +19,7 @@
 0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12
 0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133
 0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4
+0x00 0x80 0xf0 0x25 # CHECK: move $fp, $4
 0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6
 0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
 0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
@@ -26,6 +27,7 @@
 0x00 0xa7 0x9b 0x34 # CHECK: teq $5, $7, 620
 0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340
 0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6
+0x00 0xc0 0xc8 0x25 # CHECK: move $25, $6
 0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17
 0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885
 0x00 0xea 0x00 0x30 # CHECK: tge $7, $10
Index: llvm/trunk/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt
@@ -118,6 +118,8 @@
 0x86 0xd8 0x00 0x46 # CHECK: mov.s $f2, $f27
 0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4
 0x21 0xc8 0xc0 0x00 # CHECK: move $25, $6
+0x25 0xf0 0x80 0x00 # CHECK: move $fp, $4
+0x25 0xc8 0xc0 0x00 # CHECK: move $25, $6
 0x00 0x48 0x9e 0x44 # CHECK: mtc1 $fp, $f9
 0x11 0x00 0x20 0x02 # CHECK: mthi $17
 0x13 0x00 0xa0 0x03 # CHECK: mtlo $sp
Index: llvm/trunk/test/MC/Disassembler/Mips/mips3/valid-mips3.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips3/valid-mips3.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips3/valid-mips3.txt
@@ -35,6 +35,8 @@
 0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12
 0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133
 0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4
+0x00 0x80 0xf0 0x25 # CHECK: move $fp, $4
+0x00 0x80 0xf0 0x2d # CHECK: move $fp, $4
 0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6
 0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
 0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
@@ -44,6 +46,8 @@
 0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340
 0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26
 0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6
+0x00 0xc0 0xc8 0x25 # CHECK: move $25, $6
+0x00 0xc0 0xc8 0x2d # CHECK: move $25, $6
 0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17
 0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885
 0x00 0xea 0x00 0x30 # CHECK: tge $7, $10
Index: llvm/trunk/test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32/valid-mips32-el.txt
@@ -7,7 +7,9 @@
 0x67 0x45 0xc9 0x20 # CHECK: addi $9, $6, 17767
 0x67 0xc5 0xc9 0x24 # CHECK: addiu $9, $6, -15001
 0x21 0x48 0xc7 0x00 # CHECK: addu $9, $6, $7
+0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4
 0x24 0x48 0xc7 0x00 # CHECK: and $9, $6, $7
+0x25 0xf0 0x80 0x00 # CHECK: move $fp, $4
 0x67 0x45 0xc9 0x30 # CHECK: andi $9, $6, 17767
 0x4c 0x01 0x00 0x10 # CHECK: b 1332
 0x4c 0x01 0x00 0x45 # CHECK: bc1f 1332
Index: llvm/trunk/test/MC/Disassembler/Mips/mips32/valid-mips32.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32/valid-mips32.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32/valid-mips32.txt
@@ -15,6 +15,8 @@
 0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5
 0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
 0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5
+0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4
+0x00 0x80 0xf0 0x25 # CHECK: move $fp, $4
 0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
 0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
 0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5
Index: llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32_le.txt
@@ -273,7 +273,7 @@
 0x86 0x39 0x00 0x46
 
 # CHECK: move $7, $8
-0x21,0x38,0x00,0x01
+0x25,0x38,0x00,0x01
 
 # CHECK: move $3, $2
 0x25,0x18,0x40,0x00
Index: llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
@@ -17,6 +17,8 @@
 0x00 0x65 0x18 0x2a # CHECK: slt $3, $3, $5
 0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
 0x00 0x65 0x20 0x23 # CHECK: subu $4, $3, $5
+0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4
+0x00 0x80 0xf0 0x25 # CHECK: move $fp, $4
 0x00 0x80 0xfc 0x09 # CHECK: jalr.hb $4
 0x00 0xa0 0x24 0x09 # CHECK: jalr.hb $4, $5
 0x00 0xa3 0x10 0x04 # CHECK: sllv $2, $3, $5
Index: llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
@@ -126,6 +126,8 @@
 0xd1 0x2d 0x18 0x46 # CHECK: movf.s $f23, $f5, $fcc6
 0x21 0xf0 0x80 0x00 # CHECK: move $fp, $4
 0x21 0xc8 0xc0 0x00 # CHECK: move $25, $6
+0x25 0xf0 0x80 0x00 # CHECK: move $fp, $4
+0x25 0xc8 0xc0 0x00 # CHECK: move $25, $6
 0x0b 0x18 0x30 0x02 # CHECK: movn $3, $17, $16
 0xd3 0xae 0x3a 0x46 # CHECK: movn.d $f27, $f21, $26
 0x13 0x03 0x17 0x46 # CHECK: movn.s $f12, $f0, $23
Index: llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
@@ -35,6 +35,8 @@
 0x00 0x4c 0xb8 0x24 # CHECK: and $23, $2, $12
 0x00 0x53 0x21 0x72 # CHECK: tlt $2, $19, 133
 0x00 0x80 0xf0 0x21 # CHECK: move $fp, $4
+0x00 0x80 0xf0 0x25 # CHECK: move $fp, $4
+0x00 0x80 0xf0 0x2d # CHECK: move $fp, $4
 0x00 0x86 0x48 0x21 # CHECK: addu $9, $4, $6
 0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
 0x00 0x94 0xc8 0x06 # CHECK: srlv $25, $20, $4
@@ -44,6 +46,8 @@
 0x00 0xb3 0x55 0x30 # CHECK: tge $5, $19, 340
 0x00 0xba 0x28 0x2f # CHECK: dsubu $5, $5, $26
 0x00 0xc0 0xc8 0x21 # CHECK: move $25, $6
+0x00 0xc0 0xc8 0x25 # CHECK: move $25, $6
+0x00 0xc0 0xc8 0x2d # CHECK: move $25, $6
 0x00 0xd1 0x00 0x36 # CHECK: tne $6, $17
 0x00 0xe8 0xdd 0x76 # CHECK: tne $7, $8, 885
 0x00 0xea 0x00 0x30 # CHECK: tge $7, $10
Index: llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
@@ -148,6 +148,8 @@
 0x00 0x38 0x06 0x44 # CHECK: mfc1 $6, $f7
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
+0x25 0x78 0xe0 0x03 # CEHCK: move $15, $ra
+0x2d 0x78 0xe0 0x03 # CEHCK: move $15, $ra
 0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
Index: llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64/valid-mips64.txt
@@ -67,6 +67,8 @@
 0x03 0x56 0x00 0x1e # CHECK: ddiv $zero, $26, $22
 0x03 0x78 0xe0 0x2f # CHECK: dsubu $gp, $27, $24
 0x03 0xc1 0x08 0x17 # CHECK: dsrav $1, $1, $fp
+0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra
+0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra
 0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
 0x08 0x00 0x01 0x4c # CHECK: j 1328
Index: llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
@@ -168,6 +168,8 @@
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
+0x25 0x78 0xe0 0x03 # CHECK: move $15, $ra
+0x2d 0x78 0xe0 0x03 # CHECK: move $15, $ra
 0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
Index: llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
@@ -80,6 +80,8 @@
 0x03 0x56 0x00 0x1e # CHECK: ddiv $zero, $26, $22
 0x03 0x78 0xe0 0x2f # CHECK: dsubu $gp, $27, $24
 0x03 0xc1 0x08 0x17 # CHECK: dsrav $1, $1, $fp
+0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra
+0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra
 0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
 0x08 0x00 0x01 0x4c # CHECK: j 1328
Index: llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
@@ -165,6 +165,8 @@
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
+0x25 0x78 0xe0 0x03 # CEHCK: move $15, $ra
+0x2d 0x78 0xe0 0x03 # CEHCK: move $15, $ra
 0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
Index: llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
@@ -63,6 +63,8 @@
 0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
+0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra
+0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra
 0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
 0x08 0x00 0x01 0x4c # CHECK: j 1328
Index: llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
@@ -165,6 +165,8 @@
 0x10 0x28 0x00 0x00 # CHECK: mfhi $5
 0x00 0xc0 0x7e 0x44 # CHECK: mfhc1 $fp, $f24
 0x12 0x28 0x00 0x00 # CHECK: mflo $5
+0x25 0x78 0xe0 0x03 # CEHCK: move $15, $ra
+0x2d 0x78 0xe0 0x03 # CEHCK: move $15, $ra
 0x86 0x41 0x20 0x46 # CHECK: mov.d $f6, $f8
 0x86 0x39 0x00 0x46 # CHECK: mov.s $f6, $f7
 0x04 0x00 0xc7 0x70 # CHECK: msub $6, $7
Index: llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
@@ -63,6 +63,8 @@
 0x02 0xc8 0x38 0x2e # CHECK: dsub $7, $22, $8
 0x02 0xe9 0x00 0x1c # CHECK: dmult $23, $9
 0x03 0x53 0x00 0x1e # CHECK: ddiv $zero, $26, $19
+0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra
+0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra
 0x04 0xc1 0x01 0x4c # CHECK: bgez $6, 1332
 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332
 0x08 0x00 0x01 0x4c # CHECK: j 1328
Index: llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
@@ -128,6 +128,8 @@
 0x1e 0x10 0x04 0x46 # CHECK: mina.s $f0, $f2, $f4
 0xda 0x10 0x64 0x00 # CHECK: mod $2, $3, $4
 0xdb 0x10 0x64 0x00 # CHECK: modu $2, $3, $4
+0x25 0x78 0xe0 0x03 # CHECK: move $15, $ra
+0x2d 0x78 0xe0 0x03 # CHECK: move $15, $ra
 0x01 0x78 0x89 0x40 # CHECK: mtc0 $9, $15, 1
 0x99 0x18 0x24 0x46 # CHECK: msubf.d $f2, $f3, $f4
 0x99 0x18 0x04 0x46 # CHECK: msubf.s $f2, $f3, $f4
Index: llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
+++ llvm/trunk/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
@@ -45,6 +45,8 @@
 0x02 0xdc 0x00 0x31 # CHECK: tgeu $22, $gp
 0x03 0x20 0x80 0x52 # CHECK: dclz $16, $25
 0x03 0x80 0xe8 0x50 # CHECK: clz $sp, $gp
+0x03 0xe0 0x78 0x25 # CHECK: move $15, $ra
+0x03 0xe0 0x78 0x2d # CHECK: move $15, $ra
 0x04 0x11 0x14 0x9b # CHECK: bal 21104
 0x04 0x66 0x56 0x78 # CHECK: dahi $3, 22136
 0x04 0x7e 0xab 0xcd # CHECK: dati $3, -21555
Index: llvm/trunk/test/MC/Mips/mips-alu-instructions.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips-alu-instructions.s
+++ llvm/trunk/test/MC/Mips/mips-alu-instructions.s
@@ -91,7 +91,7 @@
 # CHECK:  addiu   $sp, $sp, -40  # encoding: [0xd8,0xff,0xbd,0x27]
 # CHECK:  neg     $6, $7         # encoding: [0x22,0x30,0x07,0x00]
 # CHECK:  negu    $6, $7         # encoding: [0x23,0x30,0x07,0x00]
-# CHECK:  move    $7, $8         # encoding: [0x21,0x38,0x00,0x01]
+# CHECK:  move    $7, $8         # encoding: [0x25,0x38,0x00,0x01]
 # CHECK:  .set    push
 # CHECK:  .set    mips32r2
 # CHECK:  rdhwr   $5, $29
Index: llvm/trunk/test/MC/Mips/mips1/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips1/valid.s
+++ llvm/trunk/test/MC/Mips/mips1/valid.s
@@ -64,8 +64,8 @@
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $s8,$a0
-        move      $25,$a2
+        move      $s8,$a0              # CHECK: move $fp, $4           # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6           # encoding: [0x00,0xc0,0xc8,0x25]
         mtc1      $s8,$f9
         mthi      $s1
         mtlo      $sp
Index: llvm/trunk/test/MC/Mips/mips2/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips2/valid.s
+++ llvm/trunk/test/MC/Mips/mips2/valid.s
@@ -84,8 +84,8 @@
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $s8,$a0
-        move      $25,$a2
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         mtc1      $s8,$f9
         mthi      $s1
         mtlo      $sp
Index: llvm/trunk/test/MC/Mips/mips3/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips3/valid.s
+++ llvm/trunk/test/MC/Mips/mips3/valid.s
@@ -142,10 +142,10 @@
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $a0,$a3
-        move      $s5,$a0
-        move      $s8,$a0
-        move      $25,$a2
+        move      $a0,$a3              # CHECK: move $4, $7              # encoding: [0x00,0xe0,0x20,0x25]
+        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         mtc1      $s8,$f9
         mthi      $s1
         mtlo      $sp
Index: llvm/trunk/test/MC/Mips/mips32/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips32/valid.s
+++ llvm/trunk/test/MC/Mips/mips32/valid.s
@@ -96,8 +96,8 @@
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $s8,$a0
-        move      $25,$a2
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6
Index: llvm/trunk/test/MC/Mips/mips32r2/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips32r2/valid.s
+++ llvm/trunk/test/MC/Mips/mips32r2/valid.s
@@ -111,8 +111,8 @@
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $s8,$a0
-        move      $25,$a2
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6
Index: llvm/trunk/test/MC/Mips/mips32r3/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips32r3/valid.s
+++ llvm/trunk/test/MC/Mips/mips32r3/valid.s
@@ -111,8 +111,8 @@
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $s8,$a0
-        move      $25,$a2
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6
Index: llvm/trunk/test/MC/Mips/mips32r5/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips32r5/valid.s
+++ llvm/trunk/test/MC/Mips/mips32r5/valid.s
@@ -112,8 +112,8 @@
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $s8,$a0
-        move      $25,$a2
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6
Index: llvm/trunk/test/MC/Mips/mips32r6/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips32r6/valid.s
+++ llvm/trunk/test/MC/Mips/mips32r6/valid.s
@@ -113,6 +113,10 @@
         mfc0    $8,$15,1         # CHECK: mfc0 $8, $15, 1  # encoding: [0x40,0x08,0x78,0x01]
         mod     $2,$3,$4         # CHECK: mod $2, $3, $4   # encoding: [0x00,0x64,0x10,0xda]
         modu    $2,$3,$4         # CHECK: modu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdb]
+        move    $a0,$a3          # CHECK: move $4, $7      # encoding: [0x00,0xe0,0x20,0x25]
+        move    $s5,$a0          # CHECK: move $21, $4     # encoding: [0x00,0x80,0xa8,0x25]
+        move    $s8,$a0          # CHECK: move $fp, $4     # encoding: [0x00,0x80,0xf0,0x25]
+        move    $25,$a2          # CHECK: move $25, $6     # encoding: [0x00,0xc0,0xc8,0x25]
         mtc0    $9,$15,1         # CHECK: mtc0 $9, $15, 1  # encoding: [0x40,0x89,0x78,0x01]
         mul     $2,$3,$4         # CHECK: mul $2, $3, $4   # encoding: [0x00,0x64,0x10,0x98]
         muh     $2,$3,$4         # CHECK: muh $2, $3, $4   # encoding: [0x00,0x64,0x10,0xd8]
Index: llvm/trunk/test/MC/Mips/mips4/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips4/valid.s
+++ llvm/trunk/test/MC/Mips/mips4/valid.s
@@ -150,10 +150,10 @@
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $a0,$a3
-        move      $s5,$a0
-        move      $s8,$a0
-        move      $25,$a2
+        move      $a0,$a3              # CHECK: move $4, $7              # encoding: [0x00,0xe0,0x20,0x25]
+        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6
Index: llvm/trunk/test/MC/Mips/mips5/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips5/valid.s
+++ llvm/trunk/test/MC/Mips/mips5/valid.s
@@ -151,10 +151,10 @@
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $a0,$a3
-        move      $s5,$a0
-        move      $s8,$a0
-        move      $25,$a2
+        move      $a0,$a3              # CHECK: move $4, $7              # encoding: [0x00,0xe0,0x20,0x25]
+        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6
Index: llvm/trunk/test/MC/Mips/mips64-alu-instructions.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips64-alu-instructions.s
+++ llvm/trunk/test/MC/Mips/mips64-alu-instructions.s
@@ -84,7 +84,7 @@
 # CHECK:  dsub    $9, $6, $7     # encoding: [0x2e,0x48,0xc7,0x00]
 # CHECK:  dsubu   $4, $3, $5     # encoding: [0x2f,0x20,0x65,0x00]
 # CHECK:  daddiu  $9, $6, -17767 # encoding: [0x99,0xba,0xc9,0x64]
-# CHECK:  move    $7, $8         # encoding: [0x2d,0x38,0x00,0x01]
+# CHECK:  move    $7, $8         # encoding: [0x25,0x38,0x00,0x01]
 # CHECK:  .set    push
 # CHECK:  .set    mips32r2
 # CHECK:  rdhwr   $5, $29
Index: llvm/trunk/test/MC/Mips/mips64/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips64/valid.s
+++ llvm/trunk/test/MC/Mips/mips64/valid.s
@@ -163,10 +163,10 @@
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $a0,$a3
-        move      $s5,$a0
-        move      $s8,$a0
-        move      $25,$a2
+        move      $a0,$a3              # CHECK: move $4, $7              # encoding: [0x00,0xe0,0x20,0x25]
+        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6
Index: llvm/trunk/test/MC/Mips/mips64r2/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips64r2/valid.s
+++ llvm/trunk/test/MC/Mips/mips64r2/valid.s
@@ -179,10 +179,10 @@
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $a0,$a3
-        move      $s5,$a0
-        move      $s8,$a0
-        move      $25,$a2
+        move      $a0,$a3              # CHECK: move $4, $7              # encoding: [0x00,0xe0,0x20,0x25]
+        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6
Index: llvm/trunk/test/MC/Mips/mips64r3/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips64r3/valid.s
+++ llvm/trunk/test/MC/Mips/mips64r3/valid.s
@@ -179,10 +179,10 @@
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $a0,$a3
-        move      $s5,$a0
-        move      $s8,$a0
-        move      $25,$a2
+        move      $a0,$a3              # CHECK: move $4, $7              # encoding: [0x00,0xe0,0x20,0x25]
+        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6
Index: llvm/trunk/test/MC/Mips/mips64r5/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips64r5/valid.s
+++ llvm/trunk/test/MC/Mips/mips64r5/valid.s
@@ -180,10 +180,10 @@
         mflo      $s1
         mov.d     $f20,$f14
         mov.s     $f2,$f27
-        move      $a0,$a3
-        move      $s5,$a0
-        move      $s8,$a0
-        move      $25,$a2
+        move      $a0,$a3              # CHECK: move $4, $7              # encoding: [0x00,0xe0,0x20,0x25]
+        move      $s5,$a0              # CHECK: move $21, $4             # encoding: [0x00,0x80,0xa8,0x25]
+        move      $s8,$a0              # CHECK: move $fp, $4             # encoding: [0x00,0x80,0xf0,0x25]
+        move      $25,$a2              # CHECK: move $25, $6             # encoding: [0x00,0xc0,0xc8,0x25]
         movf      $gp,$8,$fcc7
         movf.d    $f6,$f11,$fcc5
         movf.s    $f23,$f5,$fcc6
Index: llvm/trunk/test/MC/Mips/mips64r6/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips64r6/valid.s
+++ llvm/trunk/test/MC/Mips/mips64r6/valid.s
@@ -164,6 +164,10 @@
         mfc0    $8,$15,1         # CHECK: mfc0 $8, $15, 1      # encoding: [0x40,0x08,0x78,0x01]
         mod     $2,$3,$4         # CHECK: mod $2, $3, $4   # encoding: [0x00,0x64,0x10,0xda]
         modu    $2,$3,$4         # CHECK: modu $2, $3, $4  # encoding: [0x00,0x64,0x10,0xdb]
+        move    $a0,$a3          # CHECK: move $4, $7             # encoding: [0x00,0xe0,0x20,0x25]
+        move    $s5,$a0          # CHECK: move $21, $4            # encoding: [0x00,0x80,0xa8,0x25]
+        move    $s8,$a0          # CHECK: move $fp, $4            # encoding: [0x00,0x80,0xf0,0x25]
+        move    $25,$a2          # CHECK: move $25, $6            # encoding: [0x00,0xc0,0xc8,0x25]
         mtc0    $9,$15,1         # CHECK: mtc0 $9, $15, 1        # encoding: [0x40,0x89,0x78,0x01]
         msubf.d $f2,$f3,$f4      # CHECK: msubf.d $f2, $f3, $f4  # encoding: [0x46,0x24,0x18,0x99]
         msubf.s $f2,$f3,$f4      # CHECK: msubf.s $f2, $f3, $f4  # encoding: [0x46,0x04,0x18,0x99]