diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -609,10 +609,17 @@
       setOperationAction(ISD::SPLAT_VECTOR, VT, Legal);
       setOperationAction(ISD::SPLAT_VECTOR_PARTS, VT, Custom);
 
-      // Vectors implement MULHS/MULHU.
       setOperationAction(ISD::SMUL_LOHI, VT, Expand);
       setOperationAction(ISD::UMUL_LOHI, VT, Expand);
 
+      // Vectors implement MULHS/MULHU.
+      // nxvXi64 MULHS/MULHU requires the V extension instead of Zve64*.
+      if (VT.getVectorElementType() == MVT::i64 &&
+          !Subtarget.hasStdExtV()) {
+        setOperationAction(ISD::MULHU, VT, Expand);
+        setOperationAction(ISD::MULHS, VT, Expand);
+      }
+
       setOperationAction(ISD::SMIN, VT, Legal);
       setOperationAction(ISD::SMAX, VT, Legal);
       setOperationAction(ISD::UMIN, VT, Legal);
@@ -909,8 +916,12 @@
         setOperationAction(ISD::UMAX, VT, Custom);
         setOperationAction(ISD::ABS,  VT, Custom);
 
-        setOperationAction(ISD::MULHS, VT, Custom);
-        setOperationAction(ISD::MULHU, VT, Custom);
+        // nxvXi64 MULHS/MULHU requires the V extension instead of Zve64*.
+        if (VT.getVectorElementType() != MVT::i64 ||
+            Subtarget.hasStdExtV()) {
+          setOperationAction(ISD::MULHS, VT, Custom);
+          setOperationAction(ISD::MULHU, VT, Custom);
+        }
 
         setOperationAction(ISD::SADDSAT, VT, Custom);
         setOperationAction(ISD::UADDSAT, VT, Custom);
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -144,6 +144,7 @@
   bool hasStdExtF() const { return HasStdExtF; }
   bool hasStdExtD() const { return HasStdExtD; }
   bool hasStdExtC() const { return HasStdExtC; }
+  bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZba() const { return HasStdExtZba; }
   bool hasStdExtZbb() const { return HasStdExtZbb; }
   bool hasStdExtZbc() const { return HasStdExtZbc; }
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
rename from llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
rename to llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
@@ -1,6 +1,6 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --force-update
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVE64
 
 define <vscale x 1 x i8> @vdiv_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
 ; CHECK-LABEL: vdiv_vv_nxv1i8:
@@ -322,27 +322,16 @@
 }
 
 define <vscale x 1 x i16> @vdiv_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
-; RV32-LABEL: vdiv_vi_nxv1i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV32-NEXT:    vmulh.vx v8, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vsrl.vi v9, v8, 15
-; RV32-NEXT:    vadd.vv v8, v8, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv1i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vsrl.vi v9, v8, 15
-; RV64-NEXT:    vadd.vv v8, v8, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    vsra.vi v8, v8, 1
+; CHECK-NEXT:    vsrl.vi v9, v8, 15
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i16> %va, %splat
@@ -372,27 +361,16 @@
 }
 
 define <vscale x 2 x i16> @vdiv_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
-; RV32-LABEL: vdiv_vi_nxv2i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
-; RV32-NEXT:    vmulh.vx v8, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vsrl.vi v9, v8, 15
-; RV32-NEXT:    vadd.vv v8, v8, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv2i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vsrl.vi v9, v8, 15
-; RV64-NEXT:    vadd.vv v8, v8, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    vsra.vi v8, v8, 1
+; CHECK-NEXT:    vsrl.vi v9, v8, 15
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i16> %va, %splat
@@ -422,27 +400,16 @@
 }
 
 define <vscale x 4 x i16> @vdiv_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
-; RV32-LABEL: vdiv_vi_nxv4i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
-; RV32-NEXT:    vmulh.vx v8, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vsrl.vi v9, v8, 15
-; RV32-NEXT:    vadd.vv v8, v8, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv4i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vsrl.vi v9, v8, 15
-; RV64-NEXT:    vadd.vv v8, v8, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    vsra.vi v8, v8, 1
+; CHECK-NEXT:    vsrl.vi v9, v8, 15
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i16> %va, %splat
@@ -472,27 +439,16 @@
 }
 
 define <vscale x 8 x i16> @vdiv_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
-; RV32-LABEL: vdiv_vi_nxv8i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; RV32-NEXT:    vmulh.vx v8, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vsrl.vi v10, v8, 15
-; RV32-NEXT:    vadd.vv v8, v8, v10
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv8i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vsrl.vi v10, v8, 15
-; RV64-NEXT:    vadd.vv v8, v8, v10
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    vsra.vi v8, v8, 1
+; CHECK-NEXT:    vsrl.vi v10, v8, 15
+; CHECK-NEXT:    vadd.vv v8, v8, v10
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i16> %va, %splat
@@ -522,27 +478,16 @@
 }
 
 define <vscale x 16 x i16> @vdiv_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
-; RV32-LABEL: vdiv_vi_nxv16i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
-; RV32-NEXT:    vmulh.vx v8, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vsrl.vi v12, v8, 15
-; RV32-NEXT:    vadd.vv v8, v8, v12
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv16i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vsrl.vi v12, v8, 15
-; RV64-NEXT:    vadd.vv v8, v8, v12
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    vsra.vi v8, v8, 1
+; CHECK-NEXT:    vsrl.vi v12, v8, 15
+; CHECK-NEXT:    vadd.vv v8, v8, v12
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i16> %va, %splat
@@ -572,27 +517,16 @@
 }
 
 define <vscale x 32 x i16> @vdiv_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
-; RV32-LABEL: vdiv_vi_nxv32i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
-; RV32-NEXT:    vmulh.vx v8, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vsrl.vi v16, v8, 15
-; RV32-NEXT:    vadd.vv v8, v8, v16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv32i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vsrl.vi v16, v8, 15
-; RV64-NEXT:    vadd.vv v8, v8, v16
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    vsra.vi v8, v8, 1
+; CHECK-NEXT:    vsrl.vi v16, v8, 15
+; CHECK-NEXT:    vadd.vv v8, v8, v16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = sdiv <vscale x 32 x i16> %va, %splat
@@ -622,29 +556,17 @@
 }
 
 define <vscale x 1 x i32> @vdiv_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
-; RV32-LABEL: vdiv_vi_nxv1i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; RV32-NEXT:    vmulh.vx v9, v8, a0
-; RV32-NEXT:    vsub.vv v8, v9, v8
-; RV32-NEXT:    vsrl.vi v9, v8, 31
-; RV32-NEXT:    vsra.vi v8, v8, 2
-; RV32-NEXT:    vadd.vv v8, v8, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv1i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; RV64-NEXT:    vmulh.vx v9, v8, a0
-; RV64-NEXT:    vsub.vv v8, v9, v8
-; RV64-NEXT:    vsra.vi v8, v8, 2
-; RV64-NEXT:    vsrl.vi v9, v8, 31
-; RV64-NEXT:    vadd.vv v8, v8, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmulh.vx v9, v8, a0
+; CHECK-NEXT:    vsub.vv v8, v9, v8
+; CHECK-NEXT:    vsrl.vi v9, v8, 31
+; CHECK-NEXT:    vsra.vi v8, v8, 2
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i32> %va, %splat
@@ -674,29 +596,17 @@
 }
 
 define <vscale x 2 x i32> @vdiv_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
-; RV32-LABEL: vdiv_vi_nxv2i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; RV32-NEXT:    vmulh.vx v9, v8, a0
-; RV32-NEXT:    vsub.vv v8, v9, v8
-; RV32-NEXT:    vsrl.vi v9, v8, 31
-; RV32-NEXT:    vsra.vi v8, v8, 2
-; RV32-NEXT:    vadd.vv v8, v8, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv2i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; RV64-NEXT:    vmulh.vx v9, v8, a0
-; RV64-NEXT:    vsub.vv v8, v9, v8
-; RV64-NEXT:    vsra.vi v8, v8, 2
-; RV64-NEXT:    vsrl.vi v9, v8, 31
-; RV64-NEXT:    vadd.vv v8, v8, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmulh.vx v9, v8, a0
+; CHECK-NEXT:    vsub.vv v8, v9, v8
+; CHECK-NEXT:    vsrl.vi v9, v8, 31
+; CHECK-NEXT:    vsra.vi v8, v8, 2
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i32> %va, %splat
@@ -726,29 +636,17 @@
 }
 
 define <vscale x 4 x i32> @vdiv_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
-; RV32-LABEL: vdiv_vi_nxv4i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; RV32-NEXT:    vmulh.vx v10, v8, a0
-; RV32-NEXT:    vsub.vv v8, v10, v8
-; RV32-NEXT:    vsrl.vi v10, v8, 31
-; RV32-NEXT:    vsra.vi v8, v8, 2
-; RV32-NEXT:    vadd.vv v8, v8, v10
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv4i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; RV64-NEXT:    vmulh.vx v10, v8, a0
-; RV64-NEXT:    vsub.vv v8, v10, v8
-; RV64-NEXT:    vsra.vi v8, v8, 2
-; RV64-NEXT:    vsrl.vi v10, v8, 31
-; RV64-NEXT:    vadd.vv v8, v8, v10
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmulh.vx v10, v8, a0
+; CHECK-NEXT:    vsub.vv v8, v10, v8
+; CHECK-NEXT:    vsrl.vi v10, v8, 31
+; CHECK-NEXT:    vsra.vi v8, v8, 2
+; CHECK-NEXT:    vadd.vv v8, v8, v10
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i32> %va, %splat
@@ -778,29 +676,17 @@
 }
 
 define <vscale x 8 x i32> @vdiv_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; RV32-LABEL: vdiv_vi_nxv8i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT:    vmulh.vx v12, v8, a0
-; RV32-NEXT:    vsub.vv v8, v12, v8
-; RV32-NEXT:    vsrl.vi v12, v8, 31
-; RV32-NEXT:    vsra.vi v8, v8, 2
-; RV32-NEXT:    vadd.vv v8, v8, v12
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv8i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; RV64-NEXT:    vmulh.vx v12, v8, a0
-; RV64-NEXT:    vsub.vv v8, v12, v8
-; RV64-NEXT:    vsra.vi v8, v8, 2
-; RV64-NEXT:    vsrl.vi v12, v8, 31
-; RV64-NEXT:    vadd.vv v8, v8, v12
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulh.vx v12, v8, a0
+; CHECK-NEXT:    vsub.vv v8, v12, v8
+; CHECK-NEXT:    vsrl.vi v12, v8, 31
+; CHECK-NEXT:    vsra.vi v8, v8, 2
+; CHECK-NEXT:    vadd.vv v8, v8, v12
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i32> %va, %splat
@@ -830,29 +716,17 @@
 }
 
 define <vscale x 16 x i32> @vdiv_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
-; RV32-LABEL: vdiv_vi_nxv16i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
-; RV32-NEXT:    vmulh.vx v16, v8, a0
-; RV32-NEXT:    vsub.vv v8, v16, v8
-; RV32-NEXT:    vsrl.vi v16, v8, 31
-; RV32-NEXT:    vsra.vi v8, v8, 2
-; RV32-NEXT:    vadd.vv v8, v8, v16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv16i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
-; RV64-NEXT:    vmulh.vx v16, v8, a0
-; RV64-NEXT:    vsub.vv v8, v16, v8
-; RV64-NEXT:    vsra.vi v8, v8, 2
-; RV64-NEXT:    vsrl.vi v16, v8, 31
-; RV64-NEXT:    vadd.vv v8, v8, v16
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vsub.vv v8, v16, v8
+; CHECK-NEXT:    vsrl.vi v16, v8, 31
+; CHECK-NEXT:    vsra.vi v8, v8, 2
+; CHECK-NEXT:    vadd.vv v8, v8, v16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i32> %va, %splat
@@ -870,24 +744,18 @@
 }
 
 define <vscale x 1 x i64> @vdiv_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
-; RV32-LABEL: vdiv_vx_nxv1i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vdiv.vv v8, v8, v9
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vx_nxv1i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT:    vdiv.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vx_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT:    addi a0, sp, 8
+; CHECK-NEXT:    vlse64.v v9, (a0), zero
+; CHECK-NEXT:    vdiv.vv v8, v8, v9
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i64> %va, %splat
@@ -895,38 +763,33 @@
 }
 
 define <vscale x 1 x i64> @vdiv_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
-; RV32-LABEL: vdiv_vi_nxv1i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 748983
-; RV32-NEXT:    addi a0, a0, -586
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    lui a0, 898779
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vmulh.vv v8, v8, v9
-; RV32-NEXT:    li a0, 63
-; RV32-NEXT:    vsrl.vx v9, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vadd.vv v8, v8, v9
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vdiv_vi_nxv1i64_0:
+; V:       # %bb.0:
+; V-NEXT:    addi sp, sp, -16
+; V-NEXT:    .cfi_def_cfa_offset 16
+; V-NEXT:    lui a0, 748983
+; V-NEXT:    addi a0, a0, -586
+; V-NEXT:    sw a0, 12(sp)
+; V-NEXT:    lui a0, 898779
+; V-NEXT:    addi a0, a0, 1755
+; V-NEXT:    sw a0, 8(sp)
+; V-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; V-NEXT:    addi a0, sp, 8
+; V-NEXT:    vlse64.v v9, (a0), zero
+; V-NEXT:    vmulh.vv v8, v8, v9
+; V-NEXT:    li a0, 63
+; V-NEXT:    vsrl.vx v9, v8, a0
+; V-NEXT:    vsra.vi v8, v8, 1
+; V-NEXT:    vadd.vv v8, v8, v9
+; V-NEXT:    addi sp, sp, 16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vdiv_vi_nxv1i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, %hi(.LCPI58_0)
-; RV64-NEXT:    ld a0, %lo(.LCPI58_0)(a0)
-; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    li a0, 63
-; RV64-NEXT:    vsrl.vx v9, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vadd.vv v8, v8, v9
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vdiv_vi_nxv1i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; ZVE64-NEXT:    vdiv.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i64> %va, %splat
@@ -944,24 +807,18 @@
 }
 
 define <vscale x 2 x i64> @vdiv_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
-; RV32-LABEL: vdiv_vx_nxv2i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v10, (a0), zero
-; RV32-NEXT:    vdiv.vv v8, v8, v10
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vx_nxv2i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
-; RV64-NEXT:    vdiv.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vx_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT:    addi a0, sp, 8
+; CHECK-NEXT:    vlse64.v v10, (a0), zero
+; CHECK-NEXT:    vdiv.vv v8, v8, v10
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i64> %va, %splat
@@ -969,38 +826,33 @@
 }
 
 define <vscale x 2 x i64> @vdiv_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
-; RV32-LABEL: vdiv_vi_nxv2i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 748983
-; RV32-NEXT:    addi a0, a0, -586
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    lui a0, 898779
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v10, (a0), zero
-; RV32-NEXT:    vmulh.vv v8, v8, v10
-; RV32-NEXT:    li a0, 63
-; RV32-NEXT:    vsrl.vx v10, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vadd.vv v8, v8, v10
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vdiv_vi_nxv2i64_0:
+; V:       # %bb.0:
+; V-NEXT:    addi sp, sp, -16
+; V-NEXT:    .cfi_def_cfa_offset 16
+; V-NEXT:    lui a0, 748983
+; V-NEXT:    addi a0, a0, -586
+; V-NEXT:    sw a0, 12(sp)
+; V-NEXT:    lui a0, 898779
+; V-NEXT:    addi a0, a0, 1755
+; V-NEXT:    sw a0, 8(sp)
+; V-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
+; V-NEXT:    addi a0, sp, 8
+; V-NEXT:    vlse64.v v10, (a0), zero
+; V-NEXT:    vmulh.vv v8, v8, v10
+; V-NEXT:    li a0, 63
+; V-NEXT:    vsrl.vx v10, v8, a0
+; V-NEXT:    vsra.vi v8, v8, 1
+; V-NEXT:    vadd.vv v8, v8, v10
+; V-NEXT:    addi sp, sp, 16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vdiv_vi_nxv2i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, %hi(.LCPI61_0)
-; RV64-NEXT:    ld a0, %lo(.LCPI61_0)(a0)
-; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    li a0, 63
-; RV64-NEXT:    vsrl.vx v10, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vadd.vv v8, v8, v10
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vdiv_vi_nxv2i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; ZVE64-NEXT:    vdiv.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i64> %va, %splat
@@ -1018,24 +870,18 @@
 }
 
 define <vscale x 4 x i64> @vdiv_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
-; RV32-LABEL: vdiv_vx_nxv4i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v12, (a0), zero
-; RV32-NEXT:    vdiv.vv v8, v8, v12
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vx_nxv4i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
-; RV64-NEXT:    vdiv.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vx_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT:    addi a0, sp, 8
+; CHECK-NEXT:    vlse64.v v12, (a0), zero
+; CHECK-NEXT:    vdiv.vv v8, v8, v12
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i64> %va, %splat
@@ -1043,38 +889,33 @@
 }
 
 define <vscale x 4 x i64> @vdiv_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
-; RV32-LABEL: vdiv_vi_nxv4i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 748983
-; RV32-NEXT:    addi a0, a0, -586
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    lui a0, 898779
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v12, (a0), zero
-; RV32-NEXT:    vmulh.vv v8, v8, v12
-; RV32-NEXT:    li a0, 63
-; RV32-NEXT:    vsrl.vx v12, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vadd.vv v8, v8, v12
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vdiv_vi_nxv4i64_0:
+; V:       # %bb.0:
+; V-NEXT:    addi sp, sp, -16
+; V-NEXT:    .cfi_def_cfa_offset 16
+; V-NEXT:    lui a0, 748983
+; V-NEXT:    addi a0, a0, -586
+; V-NEXT:    sw a0, 12(sp)
+; V-NEXT:    lui a0, 898779
+; V-NEXT:    addi a0, a0, 1755
+; V-NEXT:    sw a0, 8(sp)
+; V-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
+; V-NEXT:    addi a0, sp, 8
+; V-NEXT:    vlse64.v v12, (a0), zero
+; V-NEXT:    vmulh.vv v8, v8, v12
+; V-NEXT:    li a0, 63
+; V-NEXT:    vsrl.vx v12, v8, a0
+; V-NEXT:    vsra.vi v8, v8, 1
+; V-NEXT:    vadd.vv v8, v8, v12
+; V-NEXT:    addi sp, sp, 16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vdiv_vi_nxv4i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, %hi(.LCPI64_0)
-; RV64-NEXT:    ld a0, %lo(.LCPI64_0)(a0)
-; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    li a0, 63
-; RV64-NEXT:    vsrl.vx v12, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vadd.vv v8, v8, v12
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vdiv_vi_nxv4i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; ZVE64-NEXT:    vdiv.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i64> %va, %splat
@@ -1092,24 +933,18 @@
 }
 
 define <vscale x 8 x i64> @vdiv_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; RV32-LABEL: vdiv_vx_nxv8i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vdiv.vv v8, v8, v16
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vx_nxv8i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vdiv.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT:    addi a0, sp, 8
+; CHECK-NEXT:    vlse64.v v16, (a0), zero
+; CHECK-NEXT:    vdiv.vv v8, v8, v16
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i64> %va, %splat
@@ -1117,41 +952,35 @@
 }
 
 define <vscale x 8 x i64> @vdiv_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
-; RV32-LABEL: vdiv_vi_nxv8i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 748983
-; RV32-NEXT:    addi a0, a0, -586
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    lui a0, 898779
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vmulh.vv v8, v8, v16
-; RV32-NEXT:    li a0, 63
-; RV32-NEXT:    vsrl.vx v16, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vadd.vv v8, v8, v16
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vdiv_vi_nxv8i64_0:
+; V:       # %bb.0:
+; V-NEXT:    addi sp, sp, -16
+; V-NEXT:    .cfi_def_cfa_offset 16
+; V-NEXT:    lui a0, 748983
+; V-NEXT:    addi a0, a0, -586
+; V-NEXT:    sw a0, 12(sp)
+; V-NEXT:    lui a0, 898779
+; V-NEXT:    addi a0, a0, 1755
+; V-NEXT:    sw a0, 8(sp)
+; V-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; V-NEXT:    addi a0, sp, 8
+; V-NEXT:    vlse64.v v16, (a0), zero
+; V-NEXT:    vmulh.vv v8, v8, v16
+; V-NEXT:    li a0, 63
+; V-NEXT:    vsrl.vx v16, v8, a0
+; V-NEXT:    vsra.vi v8, v8, 1
+; V-NEXT:    vadd.vv v8, v8, v16
+; V-NEXT:    addi sp, sp, 16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vdiv_vi_nxv8i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, %hi(.LCPI67_0)
-; RV64-NEXT:    ld a0, %lo(.LCPI67_0)(a0)
-; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    li a0, 63
-; RV64-NEXT:    vsrl.vx v16, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vadd.vv v8, v8, v16
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vdiv_vi_nxv8i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; ZVE64-NEXT:    vdiv.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
-
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
rename from llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
rename to llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll
@@ -1,6 +1,6 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --force-update
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVE64X
 
 define <vscale x 1 x i8> @vdiv_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
 ; CHECK-LABEL: vdiv_vv_nxv1i8:
@@ -322,27 +322,16 @@
 }
 
 define <vscale x 1 x i16> @vdiv_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
-; RV32-LABEL: vdiv_vi_nxv1i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV32-NEXT:    vmulh.vx v8, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vsrl.vi v9, v8, 15
-; RV32-NEXT:    vadd.vv v8, v8, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv1i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vsrl.vi v9, v8, 15
-; RV64-NEXT:    vadd.vv v8, v8, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    vsra.vi v8, v8, 1
+; CHECK-NEXT:    vsrl.vi v9, v8, 15
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i16> %va, %splat
@@ -372,27 +361,16 @@
 }
 
 define <vscale x 2 x i16> @vdiv_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
-; RV32-LABEL: vdiv_vi_nxv2i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
-; RV32-NEXT:    vmulh.vx v8, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vsrl.vi v9, v8, 15
-; RV32-NEXT:    vadd.vv v8, v8, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv2i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vsrl.vi v9, v8, 15
-; RV64-NEXT:    vadd.vv v8, v8, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    vsra.vi v8, v8, 1
+; CHECK-NEXT:    vsrl.vi v9, v8, 15
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i16> %va, %splat
@@ -422,27 +400,16 @@
 }
 
 define <vscale x 4 x i16> @vdiv_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
-; RV32-LABEL: vdiv_vi_nxv4i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
-; RV32-NEXT:    vmulh.vx v8, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vsrl.vi v9, v8, 15
-; RV32-NEXT:    vadd.vv v8, v8, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv4i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vsrl.vi v9, v8, 15
-; RV64-NEXT:    vadd.vv v8, v8, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    vsra.vi v8, v8, 1
+; CHECK-NEXT:    vsrl.vi v9, v8, 15
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i16> %va, %splat
@@ -472,27 +439,16 @@
 }
 
 define <vscale x 8 x i16> @vdiv_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
-; RV32-LABEL: vdiv_vi_nxv8i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; RV32-NEXT:    vmulh.vx v8, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vsrl.vi v10, v8, 15
-; RV32-NEXT:    vadd.vv v8, v8, v10
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv8i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vsrl.vi v10, v8, 15
-; RV64-NEXT:    vadd.vv v8, v8, v10
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    vsra.vi v8, v8, 1
+; CHECK-NEXT:    vsrl.vi v10, v8, 15
+; CHECK-NEXT:    vadd.vv v8, v8, v10
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i16> %va, %splat
@@ -522,27 +478,16 @@
 }
 
 define <vscale x 16 x i16> @vdiv_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
-; RV32-LABEL: vdiv_vi_nxv16i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
-; RV32-NEXT:    vmulh.vx v8, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vsrl.vi v12, v8, 15
-; RV32-NEXT:    vadd.vv v8, v8, v12
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv16i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vsrl.vi v12, v8, 15
-; RV64-NEXT:    vadd.vv v8, v8, v12
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    vsra.vi v8, v8, 1
+; CHECK-NEXT:    vsrl.vi v12, v8, 15
+; CHECK-NEXT:    vadd.vv v8, v8, v12
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i16> %va, %splat
@@ -572,27 +517,16 @@
 }
 
 define <vscale x 32 x i16> @vdiv_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
-; RV32-LABEL: vdiv_vi_nxv32i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
-; RV32-NEXT:    vmulh.vx v8, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vsrl.vi v16, v8, 15
-; RV32-NEXT:    vadd.vv v8, v8, v16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv32i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vsrl.vi v16, v8, 15
-; RV64-NEXT:    vadd.vv v8, v8, v16
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
+; CHECK-NEXT:    vmulh.vx v8, v8, a0
+; CHECK-NEXT:    vsra.vi v8, v8, 1
+; CHECK-NEXT:    vsrl.vi v16, v8, 15
+; CHECK-NEXT:    vadd.vv v8, v8, v16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = sdiv <vscale x 32 x i16> %va, %splat
@@ -622,29 +556,17 @@
 }
 
 define <vscale x 1 x i32> @vdiv_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
-; RV32-LABEL: vdiv_vi_nxv1i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; RV32-NEXT:    vmulh.vx v9, v8, a0
-; RV32-NEXT:    vsub.vv v8, v9, v8
-; RV32-NEXT:    vsrl.vi v9, v8, 31
-; RV32-NEXT:    vsra.vi v8, v8, 2
-; RV32-NEXT:    vadd.vv v8, v8, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv1i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; RV64-NEXT:    vmulh.vx v9, v8, a0
-; RV64-NEXT:    vsub.vv v8, v9, v8
-; RV64-NEXT:    vsra.vi v8, v8, 2
-; RV64-NEXT:    vsrl.vi v9, v8, 31
-; RV64-NEXT:    vadd.vv v8, v8, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmulh.vx v9, v8, a0
+; CHECK-NEXT:    vsub.vv v8, v9, v8
+; CHECK-NEXT:    vsra.vi v8, v8, 2
+; CHECK-NEXT:    vsrl.vi v9, v8, 31
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i32> %va, %splat
@@ -674,29 +596,17 @@
 }
 
 define <vscale x 2 x i32> @vdiv_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
-; RV32-LABEL: vdiv_vi_nxv2i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; RV32-NEXT:    vmulh.vx v9, v8, a0
-; RV32-NEXT:    vsub.vv v8, v9, v8
-; RV32-NEXT:    vsrl.vi v9, v8, 31
-; RV32-NEXT:    vsra.vi v8, v8, 2
-; RV32-NEXT:    vadd.vv v8, v8, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv2i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; RV64-NEXT:    vmulh.vx v9, v8, a0
-; RV64-NEXT:    vsub.vv v8, v9, v8
-; RV64-NEXT:    vsra.vi v8, v8, 2
-; RV64-NEXT:    vsrl.vi v9, v8, 31
-; RV64-NEXT:    vadd.vv v8, v8, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmulh.vx v9, v8, a0
+; CHECK-NEXT:    vsub.vv v8, v9, v8
+; CHECK-NEXT:    vsra.vi v8, v8, 2
+; CHECK-NEXT:    vsrl.vi v9, v8, 31
+; CHECK-NEXT:    vadd.vv v8, v8, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i32> %va, %splat
@@ -726,29 +636,17 @@
 }
 
 define <vscale x 4 x i32> @vdiv_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
-; RV32-LABEL: vdiv_vi_nxv4i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; RV32-NEXT:    vmulh.vx v10, v8, a0
-; RV32-NEXT:    vsub.vv v8, v10, v8
-; RV32-NEXT:    vsrl.vi v10, v8, 31
-; RV32-NEXT:    vsra.vi v8, v8, 2
-; RV32-NEXT:    vadd.vv v8, v8, v10
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv4i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; RV64-NEXT:    vmulh.vx v10, v8, a0
-; RV64-NEXT:    vsub.vv v8, v10, v8
-; RV64-NEXT:    vsra.vi v8, v8, 2
-; RV64-NEXT:    vsrl.vi v10, v8, 31
-; RV64-NEXT:    vadd.vv v8, v8, v10
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmulh.vx v10, v8, a0
+; CHECK-NEXT:    vsub.vv v8, v10, v8
+; CHECK-NEXT:    vsra.vi v8, v8, 2
+; CHECK-NEXT:    vsrl.vi v10, v8, 31
+; CHECK-NEXT:    vadd.vv v8, v8, v10
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i32> %va, %splat
@@ -778,29 +676,17 @@
 }
 
 define <vscale x 8 x i32> @vdiv_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; RV32-LABEL: vdiv_vi_nxv8i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT:    vmulh.vx v12, v8, a0
-; RV32-NEXT:    vsub.vv v8, v12, v8
-; RV32-NEXT:    vsrl.vi v12, v8, 31
-; RV32-NEXT:    vsra.vi v8, v8, 2
-; RV32-NEXT:    vadd.vv v8, v8, v12
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv8i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; RV64-NEXT:    vmulh.vx v12, v8, a0
-; RV64-NEXT:    vsub.vv v8, v12, v8
-; RV64-NEXT:    vsra.vi v8, v8, 2
-; RV64-NEXT:    vsrl.vi v12, v8, 31
-; RV64-NEXT:    vadd.vv v8, v8, v12
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulh.vx v12, v8, a0
+; CHECK-NEXT:    vsub.vv v8, v12, v8
+; CHECK-NEXT:    vsra.vi v8, v8, 2
+; CHECK-NEXT:    vsrl.vi v12, v8, 31
+; CHECK-NEXT:    vadd.vv v8, v8, v12
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i32> %va, %splat
@@ -830,29 +716,17 @@
 }
 
 define <vscale x 16 x i32> @vdiv_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
-; RV32-LABEL: vdiv_vi_nxv16i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
-; RV32-NEXT:    vmulh.vx v16, v8, a0
-; RV32-NEXT:    vsub.vv v8, v16, v8
-; RV32-NEXT:    vsrl.vi v16, v8, 31
-; RV32-NEXT:    vsra.vi v8, v8, 2
-; RV32-NEXT:    vadd.vv v8, v8, v16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vi_nxv16i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
-; RV64-NEXT:    vmulh.vx v16, v8, a0
-; RV64-NEXT:    vsub.vv v8, v16, v8
-; RV64-NEXT:    vsra.vi v8, v8, 2
-; RV64-NEXT:    vsrl.vi v16, v8, 31
-; RV64-NEXT:    vadd.vv v8, v8, v16
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vi_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vsub.vv v8, v16, v8
+; CHECK-NEXT:    vsra.vi v8, v8, 2
+; CHECK-NEXT:    vsrl.vi v16, v8, 31
+; CHECK-NEXT:    vadd.vv v8, v8, v16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = sdiv <vscale x 16 x i32> %va, %splat
@@ -870,24 +744,11 @@
 }
 
 define <vscale x 1 x i64> @vdiv_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
-; RV32-LABEL: vdiv_vx_nxv1i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vdiv.vv v8, v8, v9
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vx_nxv1i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT:    vdiv.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vx_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i64> %va, %splat
@@ -895,38 +756,24 @@
 }
 
 define <vscale x 1 x i64> @vdiv_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
-; RV32-LABEL: vdiv_vi_nxv1i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 748983
-; RV32-NEXT:    addi a0, a0, -586
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    lui a0, 898779
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vmulh.vv v8, v8, v9
-; RV32-NEXT:    li a0, 63
-; RV32-NEXT:    vsrl.vx v9, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vadd.vv v8, v8, v9
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vdiv_vi_nxv1i64_0:
+; V:       # %bb.0:
+; V-NEXT:    lui a0, %hi(.LCPI58_0)
+; V-NEXT:    ld a0, %lo(.LCPI58_0)(a0)
+; V-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; V-NEXT:    vmulh.vx v8, v8, a0
+; V-NEXT:    li a0, 63
+; V-NEXT:    vsrl.vx v9, v8, a0
+; V-NEXT:    vsra.vi v8, v8, 1
+; V-NEXT:    vadd.vv v8, v8, v9
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vdiv_vi_nxv1i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, %hi(.LCPI58_0)
-; RV64-NEXT:    ld a0, %lo(.LCPI58_0)(a0)
-; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    li a0, 63
-; RV64-NEXT:    vsrl.vx v9, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vadd.vv v8, v8, v9
-; RV64-NEXT:    ret
+; ZVE64X-LABEL: vdiv_vi_nxv1i64_0:
+; ZVE64X:       # %bb.0:
+; ZVE64X-NEXT:    li a0, -7
+; ZVE64X-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; ZVE64X-NEXT:    vdiv.vx v8, v8, a0
+; ZVE64X-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = sdiv <vscale x 1 x i64> %va, %splat
@@ -944,24 +791,11 @@
 }
 
 define <vscale x 2 x i64> @vdiv_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
-; RV32-LABEL: vdiv_vx_nxv2i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v10, (a0), zero
-; RV32-NEXT:    vdiv.vv v8, v8, v10
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vx_nxv2i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
-; RV64-NEXT:    vdiv.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vx_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i64> %va, %splat
@@ -969,38 +803,24 @@
 }
 
 define <vscale x 2 x i64> @vdiv_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
-; RV32-LABEL: vdiv_vi_nxv2i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 748983
-; RV32-NEXT:    addi a0, a0, -586
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    lui a0, 898779
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v10, (a0), zero
-; RV32-NEXT:    vmulh.vv v8, v8, v10
-; RV32-NEXT:    li a0, 63
-; RV32-NEXT:    vsrl.vx v10, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vadd.vv v8, v8, v10
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vdiv_vi_nxv2i64_0:
+; V:       # %bb.0:
+; V-NEXT:    lui a0, %hi(.LCPI61_0)
+; V-NEXT:    ld a0, %lo(.LCPI61_0)(a0)
+; V-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; V-NEXT:    vmulh.vx v8, v8, a0
+; V-NEXT:    li a0, 63
+; V-NEXT:    vsrl.vx v10, v8, a0
+; V-NEXT:    vsra.vi v8, v8, 1
+; V-NEXT:    vadd.vv v8, v8, v10
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vdiv_vi_nxv2i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, %hi(.LCPI61_0)
-; RV64-NEXT:    ld a0, %lo(.LCPI61_0)(a0)
-; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    li a0, 63
-; RV64-NEXT:    vsrl.vx v10, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vadd.vv v8, v8, v10
-; RV64-NEXT:    ret
+; ZVE64X-LABEL: vdiv_vi_nxv2i64_0:
+; ZVE64X:       # %bb.0:
+; ZVE64X-NEXT:    li a0, -7
+; ZVE64X-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; ZVE64X-NEXT:    vdiv.vx v8, v8, a0
+; ZVE64X-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = sdiv <vscale x 2 x i64> %va, %splat
@@ -1018,24 +838,11 @@
 }
 
 define <vscale x 4 x i64> @vdiv_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
-; RV32-LABEL: vdiv_vx_nxv4i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v12, (a0), zero
-; RV32-NEXT:    vdiv.vv v8, v8, v12
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vx_nxv4i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
-; RV64-NEXT:    vdiv.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vx_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i64> %va, %splat
@@ -1043,38 +850,24 @@
 }
 
 define <vscale x 4 x i64> @vdiv_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
-; RV32-LABEL: vdiv_vi_nxv4i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 748983
-; RV32-NEXT:    addi a0, a0, -586
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    lui a0, 898779
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v12, (a0), zero
-; RV32-NEXT:    vmulh.vv v8, v8, v12
-; RV32-NEXT:    li a0, 63
-; RV32-NEXT:    vsrl.vx v12, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vadd.vv v8, v8, v12
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vdiv_vi_nxv4i64_0:
+; V:       # %bb.0:
+; V-NEXT:    lui a0, %hi(.LCPI64_0)
+; V-NEXT:    ld a0, %lo(.LCPI64_0)(a0)
+; V-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; V-NEXT:    vmulh.vx v8, v8, a0
+; V-NEXT:    li a0, 63
+; V-NEXT:    vsrl.vx v12, v8, a0
+; V-NEXT:    vsra.vi v8, v8, 1
+; V-NEXT:    vadd.vv v8, v8, v12
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vdiv_vi_nxv4i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, %hi(.LCPI64_0)
-; RV64-NEXT:    ld a0, %lo(.LCPI64_0)(a0)
-; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    li a0, 63
-; RV64-NEXT:    vsrl.vx v12, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vadd.vv v8, v8, v12
-; RV64-NEXT:    ret
+; ZVE64X-LABEL: vdiv_vi_nxv4i64_0:
+; ZVE64X:       # %bb.0:
+; ZVE64X-NEXT:    li a0, -7
+; ZVE64X-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; ZVE64X-NEXT:    vdiv.vx v8, v8, a0
+; ZVE64X-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = sdiv <vscale x 4 x i64> %va, %splat
@@ -1092,24 +885,11 @@
 }
 
 define <vscale x 8 x i64> @vdiv_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; RV32-LABEL: vdiv_vx_nxv8i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vdiv.vv v8, v8, v16
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdiv_vx_nxv8i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vdiv.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdiv_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; CHECK-NEXT:    vdiv.vx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i64> %va, %splat
@@ -1117,41 +897,26 @@
 }
 
 define <vscale x 8 x i64> @vdiv_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
-; RV32-LABEL: vdiv_vi_nxv8i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 748983
-; RV32-NEXT:    addi a0, a0, -586
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    lui a0, 898779
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vmulh.vv v8, v8, v16
-; RV32-NEXT:    li a0, 63
-; RV32-NEXT:    vsrl.vx v16, v8, a0
-; RV32-NEXT:    vsra.vi v8, v8, 1
-; RV32-NEXT:    vadd.vv v8, v8, v16
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vdiv_vi_nxv8i64_0:
+; V:       # %bb.0:
+; V-NEXT:    lui a0, %hi(.LCPI67_0)
+; V-NEXT:    ld a0, %lo(.LCPI67_0)(a0)
+; V-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; V-NEXT:    vmulh.vx v8, v8, a0
+; V-NEXT:    li a0, 63
+; V-NEXT:    vsrl.vx v16, v8, a0
+; V-NEXT:    vsra.vi v8, v8, 1
+; V-NEXT:    vadd.vv v8, v8, v16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vdiv_vi_nxv8i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, %hi(.LCPI67_0)
-; RV64-NEXT:    ld a0, %lo(.LCPI67_0)(a0)
-; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vmulh.vx v8, v8, a0
-; RV64-NEXT:    li a0, 63
-; RV64-NEXT:    vsrl.vx v16, v8, a0
-; RV64-NEXT:    vsra.vi v8, v8, 1
-; RV64-NEXT:    vadd.vv v8, v8, v16
-; RV64-NEXT:    ret
+; ZVE64X-LABEL: vdiv_vi_nxv8i64_0:
+; ZVE64X:       # %bb.0:
+; ZVE64X-NEXT:    li a0, -7
+; ZVE64X-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; ZVE64X-NEXT:    vdiv.vx v8, v8, a0
+; ZVE64X-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = sdiv <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
-
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
rename from llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
rename to llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
@@ -1,6 +1,6 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --force-update
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVE64
 
 define <vscale x 1 x i8> @vdivu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
 ; CHECK-LABEL: vdivu_vv_nxv1i8:
@@ -301,23 +301,14 @@
 }
 
 define <vscale x 1 x i16> @vdivu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
-; RV32-LABEL: vdivu_vi_nxv1i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 13
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv1i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 13
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 13
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i16> %va, %splat
@@ -347,23 +338,14 @@
 }
 
 define <vscale x 2 x i16> @vdivu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
-; RV32-LABEL: vdivu_vi_nxv2i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 13
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv2i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 13
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 13
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i16> %va, %splat
@@ -393,23 +375,14 @@
 }
 
 define <vscale x 4 x i16> @vdivu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
-; RV32-LABEL: vdivu_vi_nxv4i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 13
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv4i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 13
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 13
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i16> %va, %splat
@@ -439,23 +412,14 @@
 }
 
 define <vscale x 8 x i16> @vdivu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
-; RV32-LABEL: vdivu_vi_nxv8i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 13
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv8i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 13
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 13
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i16> %va, %splat
@@ -485,23 +449,14 @@
 }
 
 define <vscale x 16 x i16> @vdivu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
-; RV32-LABEL: vdivu_vi_nxv16i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 13
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv16i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 13
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 13
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i16> %va, %splat
@@ -531,23 +486,14 @@
 }
 
 define <vscale x 32 x i16> @vdivu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
-; RV32-LABEL: vdivu_vi_nxv32i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 13
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv32i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 13
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 13
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = udiv <vscale x 32 x i16> %va, %splat
@@ -577,23 +523,14 @@
 }
 
 define <vscale x 1 x i32> @vdivu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
-; RV32-LABEL: vdivu_vi_nxv1i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 29
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv1i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 29
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 29
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i32> %va, %splat
@@ -623,23 +560,14 @@
 }
 
 define <vscale x 2 x i32> @vdivu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
-; RV32-LABEL: vdivu_vi_nxv2i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 29
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv2i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 29
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 29
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i32> %va, %splat
@@ -669,23 +597,14 @@
 }
 
 define <vscale x 4 x i32> @vdivu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
-; RV32-LABEL: vdivu_vi_nxv4i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 29
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv4i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 29
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 29
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i32> %va, %splat
@@ -715,23 +634,14 @@
 }
 
 define <vscale x 8 x i32> @vdivu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; RV32-LABEL: vdivu_vi_nxv8i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 29
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv8i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 29
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 29
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i32> %va, %splat
@@ -761,23 +671,14 @@
 }
 
 define <vscale x 16 x i32> @vdivu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
-; RV32-LABEL: vdivu_vi_nxv16i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 29
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv16i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 29
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 29
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i32> %va, %splat
@@ -795,24 +696,18 @@
 }
 
 define <vscale x 1 x i64> @vdivu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
-; RV32-LABEL: vdivu_vx_nxv1i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vdivu.vv v8, v8, v9
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vx_nxv1i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT:    vdivu.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vx_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT:    addi a0, sp, 8
+; CHECK-NEXT:    vlse64.v v9, (a0), zero
+; CHECK-NEXT:    vdivu.vv v8, v8, v9
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i64> %va, %splat
@@ -820,33 +715,29 @@
 }
 
 define <vscale x 1 x i64> @vdivu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
-; RV32-LABEL: vdivu_vi_nxv1i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    li a0, 1
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vmulhu.vv v8, v8, v9
-; RV32-NEXT:    li a0, 61
-; RV32-NEXT:    vsrl.vx v8, v8, a0
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vdivu_vi_nxv1i64_0:
+; V:       # %bb.0:
+; V-NEXT:    addi sp, sp, -16
+; V-NEXT:    .cfi_def_cfa_offset 16
+; V-NEXT:    lui a0, 131072
+; V-NEXT:    sw a0, 12(sp)
+; V-NEXT:    li a0, 1
+; V-NEXT:    sw a0, 8(sp)
+; V-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; V-NEXT:    addi a0, sp, 8
+; V-NEXT:    vlse64.v v9, (a0), zero
+; V-NEXT:    vmulhu.vv v8, v8, v9
+; V-NEXT:    li a0, 61
+; V-NEXT:    vsrl.vx v8, v8, a0
+; V-NEXT:    addi sp, sp, 16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vdivu_vi_nxv1i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a0, 1
-; RV64-NEXT:    slli a0, a0, 61
-; RV64-NEXT:    addi a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    li a0, 61
-; RV64-NEXT:    vsrl.vx v8, v8, a0
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vdivu_vi_nxv1i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; ZVE64-NEXT:    vdivu.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i64> %va, %splat
@@ -891,24 +782,18 @@
 }
 
 define <vscale x 2 x i64> @vdivu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
-; RV32-LABEL: vdivu_vx_nxv2i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v10, (a0), zero
-; RV32-NEXT:    vdivu.vv v8, v8, v10
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vx_nxv2i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
-; RV64-NEXT:    vdivu.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vx_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT:    addi a0, sp, 8
+; CHECK-NEXT:    vlse64.v v10, (a0), zero
+; CHECK-NEXT:    vdivu.vv v8, v8, v10
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i64> %va, %splat
@@ -916,33 +801,29 @@
 }
 
 define <vscale x 2 x i64> @vdivu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
-; RV32-LABEL: vdivu_vi_nxv2i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    li a0, 1
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v10, (a0), zero
-; RV32-NEXT:    vmulhu.vv v8, v8, v10
-; RV32-NEXT:    li a0, 61
-; RV32-NEXT:    vsrl.vx v8, v8, a0
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vdivu_vi_nxv2i64_0:
+; V:       # %bb.0:
+; V-NEXT:    addi sp, sp, -16
+; V-NEXT:    .cfi_def_cfa_offset 16
+; V-NEXT:    lui a0, 131072
+; V-NEXT:    sw a0, 12(sp)
+; V-NEXT:    li a0, 1
+; V-NEXT:    sw a0, 8(sp)
+; V-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
+; V-NEXT:    addi a0, sp, 8
+; V-NEXT:    vlse64.v v10, (a0), zero
+; V-NEXT:    vmulhu.vv v8, v8, v10
+; V-NEXT:    li a0, 61
+; V-NEXT:    vsrl.vx v8, v8, a0
+; V-NEXT:    addi sp, sp, 16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vdivu_vi_nxv2i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a0, 1
-; RV64-NEXT:    slli a0, a0, 61
-; RV64-NEXT:    addi a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    li a0, 61
-; RV64-NEXT:    vsrl.vx v8, v8, a0
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vdivu_vi_nxv2i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; ZVE64-NEXT:    vdivu.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i64> %va, %splat
@@ -987,24 +868,18 @@
 }
 
 define <vscale x 4 x i64> @vdivu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
-; RV32-LABEL: vdivu_vx_nxv4i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v12, (a0), zero
-; RV32-NEXT:    vdivu.vv v8, v8, v12
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vx_nxv4i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
-; RV64-NEXT:    vdivu.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vx_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT:    addi a0, sp, 8
+; CHECK-NEXT:    vlse64.v v12, (a0), zero
+; CHECK-NEXT:    vdivu.vv v8, v8, v12
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i64> %va, %splat
@@ -1012,33 +887,29 @@
 }
 
 define <vscale x 4 x i64> @vdivu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
-; RV32-LABEL: vdivu_vi_nxv4i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    li a0, 1
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v12, (a0), zero
-; RV32-NEXT:    vmulhu.vv v8, v8, v12
-; RV32-NEXT:    li a0, 61
-; RV32-NEXT:    vsrl.vx v8, v8, a0
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vdivu_vi_nxv4i64_0:
+; V:       # %bb.0:
+; V-NEXT:    addi sp, sp, -16
+; V-NEXT:    .cfi_def_cfa_offset 16
+; V-NEXT:    lui a0, 131072
+; V-NEXT:    sw a0, 12(sp)
+; V-NEXT:    li a0, 1
+; V-NEXT:    sw a0, 8(sp)
+; V-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
+; V-NEXT:    addi a0, sp, 8
+; V-NEXT:    vlse64.v v12, (a0), zero
+; V-NEXT:    vmulhu.vv v8, v8, v12
+; V-NEXT:    li a0, 61
+; V-NEXT:    vsrl.vx v8, v8, a0
+; V-NEXT:    addi sp, sp, 16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vdivu_vi_nxv4i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a0, 1
-; RV64-NEXT:    slli a0, a0, 61
-; RV64-NEXT:    addi a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    li a0, 61
-; RV64-NEXT:    vsrl.vx v8, v8, a0
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vdivu_vi_nxv4i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; ZVE64-NEXT:    vdivu.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i64> %va, %splat
@@ -1083,24 +954,18 @@
 }
 
 define <vscale x 8 x i64> @vdivu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; RV32-LABEL: vdivu_vx_nxv8i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vdivu.vv v8, v8, v16
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vx_nxv8i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vdivu.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT:    addi a0, sp, 8
+; CHECK-NEXT:    vlse64.v v16, (a0), zero
+; CHECK-NEXT:    vdivu.vv v8, v8, v16
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i64> %va, %splat
@@ -1108,33 +973,29 @@
 }
 
 define <vscale x 8 x i64> @vdivu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
-; RV32-LABEL: vdivu_vi_nxv8i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    li a0, 1
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vmulhu.vv v8, v8, v16
-; RV32-NEXT:    li a0, 61
-; RV32-NEXT:    vsrl.vx v8, v8, a0
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vdivu_vi_nxv8i64_0:
+; V:       # %bb.0:
+; V-NEXT:    addi sp, sp, -16
+; V-NEXT:    .cfi_def_cfa_offset 16
+; V-NEXT:    lui a0, 131072
+; V-NEXT:    sw a0, 12(sp)
+; V-NEXT:    li a0, 1
+; V-NEXT:    sw a0, 8(sp)
+; V-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; V-NEXT:    addi a0, sp, 8
+; V-NEXT:    vlse64.v v16, (a0), zero
+; V-NEXT:    vmulhu.vv v8, v8, v16
+; V-NEXT:    li a0, 61
+; V-NEXT:    vsrl.vx v8, v8, a0
+; V-NEXT:    addi sp, sp, 16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vdivu_vi_nxv8i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a0, 1
-; RV64-NEXT:    slli a0, a0, 61
-; RV64-NEXT:    addi a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    li a0, 61
-; RV64-NEXT:    vsrl.vx v8, v8, a0
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vdivu_vi_nxv8i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; ZVE64-NEXT:    vdivu.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i64> %va, %splat
diff --git a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
rename from llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
rename to llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll
@@ -1,6 +1,6 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --force-update
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVE64
 
 define <vscale x 1 x i8> @vdivu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
 ; CHECK-LABEL: vdivu_vv_nxv1i8:
@@ -301,23 +301,14 @@
 }
 
 define <vscale x 1 x i16> @vdivu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
-; RV32-LABEL: vdivu_vi_nxv1i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 13
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv1i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 13
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 13
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i16> %va, %splat
@@ -347,23 +338,14 @@
 }
 
 define <vscale x 2 x i16> @vdivu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
-; RV32-LABEL: vdivu_vi_nxv2i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 13
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv2i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 13
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 13
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i16> %va, %splat
@@ -393,23 +375,14 @@
 }
 
 define <vscale x 4 x i16> @vdivu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
-; RV32-LABEL: vdivu_vi_nxv4i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 13
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv4i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 13
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 13
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i16> %va, %splat
@@ -439,23 +412,14 @@
 }
 
 define <vscale x 8 x i16> @vdivu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
-; RV32-LABEL: vdivu_vi_nxv8i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 13
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv8i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 13
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 13
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i16> %va, %splat
@@ -485,23 +449,14 @@
 }
 
 define <vscale x 16 x i16> @vdivu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
-; RV32-LABEL: vdivu_vi_nxv16i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 13
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv16i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 13
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 13
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i16> %va, %splat
@@ -531,23 +486,14 @@
 }
 
 define <vscale x 32 x i16> @vdivu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
-; RV32-LABEL: vdivu_vi_nxv32i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 13
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv32i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 13
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 13
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = udiv <vscale x 32 x i16> %va, %splat
@@ -577,23 +523,14 @@
 }
 
 define <vscale x 1 x i32> @vdivu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
-; RV32-LABEL: vdivu_vi_nxv1i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 29
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv1i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 29
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 29
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i32> %va, %splat
@@ -623,23 +560,14 @@
 }
 
 define <vscale x 2 x i32> @vdivu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
-; RV32-LABEL: vdivu_vi_nxv2i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 29
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv2i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 29
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 29
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i32> %va, %splat
@@ -669,23 +597,14 @@
 }
 
 define <vscale x 4 x i32> @vdivu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
-; RV32-LABEL: vdivu_vi_nxv4i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 29
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv4i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 29
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 29
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i32> %va, %splat
@@ -715,23 +634,14 @@
 }
 
 define <vscale x 8 x i32> @vdivu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; RV32-LABEL: vdivu_vi_nxv8i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 29
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv8i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 29
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 29
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i32> %va, %splat
@@ -761,23 +671,14 @@
 }
 
 define <vscale x 16 x i32> @vdivu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
-; RV32-LABEL: vdivu_vi_nxv16i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
-; RV32-NEXT:    vmulhu.vx v8, v8, a0
-; RV32-NEXT:    vsrl.vi v8, v8, 29
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vi_nxv16i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    vsrl.vi v8, v8, 29
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vi_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
+; CHECK-NEXT:    vmulhu.vx v8, v8, a0
+; CHECK-NEXT:    vsrl.vi v8, v8, 29
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = udiv <vscale x 16 x i32> %va, %splat
@@ -795,24 +696,11 @@
 }
 
 define <vscale x 1 x i64> @vdivu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
-; RV32-LABEL: vdivu_vx_nxv1i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vdivu.vv v8, v8, v9
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vx_nxv1i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT:    vdivu.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vx_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i64> %va, %splat
@@ -820,33 +708,23 @@
 }
 
 define <vscale x 1 x i64> @vdivu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
-; RV32-LABEL: vdivu_vi_nxv1i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    li a0, 1
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vmulhu.vv v8, v8, v9
-; RV32-NEXT:    li a0, 61
-; RV32-NEXT:    vsrl.vx v8, v8, a0
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vdivu_vi_nxv1i64_0:
+; V:       # %bb.0:
+; V-NEXT:    li a0, 1
+; V-NEXT:    slli a0, a0, 61
+; V-NEXT:    addi a0, a0, 1
+; V-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; V-NEXT:    vmulhu.vx v8, v8, a0
+; V-NEXT:    li a0, 61
+; V-NEXT:    vsrl.vx v8, v8, a0
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vdivu_vi_nxv1i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a0, 1
-; RV64-NEXT:    slli a0, a0, 61
-; RV64-NEXT:    addi a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    li a0, 61
-; RV64-NEXT:    vsrl.vx v8, v8, a0
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vdivu_vi_nxv1i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; ZVE64-NEXT:    vdivu.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = udiv <vscale x 1 x i64> %va, %splat
@@ -891,24 +769,11 @@
 }
 
 define <vscale x 2 x i64> @vdivu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
-; RV32-LABEL: vdivu_vx_nxv2i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v10, (a0), zero
-; RV32-NEXT:    vdivu.vv v8, v8, v10
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vx_nxv2i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
-; RV64-NEXT:    vdivu.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vx_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i64> %va, %splat
@@ -916,33 +781,23 @@
 }
 
 define <vscale x 2 x i64> @vdivu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
-; RV32-LABEL: vdivu_vi_nxv2i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    li a0, 1
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v10, (a0), zero
-; RV32-NEXT:    vmulhu.vv v8, v8, v10
-; RV32-NEXT:    li a0, 61
-; RV32-NEXT:    vsrl.vx v8, v8, a0
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vdivu_vi_nxv2i64_0:
+; V:       # %bb.0:
+; V-NEXT:    li a0, 1
+; V-NEXT:    slli a0, a0, 61
+; V-NEXT:    addi a0, a0, 1
+; V-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; V-NEXT:    vmulhu.vx v8, v8, a0
+; V-NEXT:    li a0, 61
+; V-NEXT:    vsrl.vx v8, v8, a0
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vdivu_vi_nxv2i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a0, 1
-; RV64-NEXT:    slli a0, a0, 61
-; RV64-NEXT:    addi a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    li a0, 61
-; RV64-NEXT:    vsrl.vx v8, v8, a0
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vdivu_vi_nxv2i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; ZVE64-NEXT:    vdivu.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = udiv <vscale x 2 x i64> %va, %splat
@@ -987,24 +842,11 @@
 }
 
 define <vscale x 4 x i64> @vdivu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
-; RV32-LABEL: vdivu_vx_nxv4i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v12, (a0), zero
-; RV32-NEXT:    vdivu.vv v8, v8, v12
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vx_nxv4i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
-; RV64-NEXT:    vdivu.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vx_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i64> %va, %splat
@@ -1012,33 +854,23 @@
 }
 
 define <vscale x 4 x i64> @vdivu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
-; RV32-LABEL: vdivu_vi_nxv4i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    li a0, 1
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v12, (a0), zero
-; RV32-NEXT:    vmulhu.vv v8, v8, v12
-; RV32-NEXT:    li a0, 61
-; RV32-NEXT:    vsrl.vx v8, v8, a0
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vdivu_vi_nxv4i64_0:
+; V:       # %bb.0:
+; V-NEXT:    li a0, 1
+; V-NEXT:    slli a0, a0, 61
+; V-NEXT:    addi a0, a0, 1
+; V-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; V-NEXT:    vmulhu.vx v8, v8, a0
+; V-NEXT:    li a0, 61
+; V-NEXT:    vsrl.vx v8, v8, a0
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vdivu_vi_nxv4i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a0, 1
-; RV64-NEXT:    slli a0, a0, 61
-; RV64-NEXT:    addi a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    li a0, 61
-; RV64-NEXT:    vsrl.vx v8, v8, a0
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vdivu_vi_nxv4i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; ZVE64-NEXT:    vdivu.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = udiv <vscale x 4 x i64> %va, %splat
@@ -1083,24 +915,11 @@
 }
 
 define <vscale x 8 x i64> @vdivu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; RV32-LABEL: vdivu_vx_nxv8i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vdivu.vv v8, v8, v16
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vdivu_vx_nxv8i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vdivu.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vdivu_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; CHECK-NEXT:    vdivu.vx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i64> %va, %splat
@@ -1108,33 +927,23 @@
 }
 
 define <vscale x 8 x i64> @vdivu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
-; RV32-LABEL: vdivu_vi_nxv8i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    li a0, 1
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vmulhu.vv v8, v8, v16
-; RV32-NEXT:    li a0, 61
-; RV32-NEXT:    vsrl.vx v8, v8, a0
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vdivu_vi_nxv8i64_0:
+; V:       # %bb.0:
+; V-NEXT:    li a0, 1
+; V-NEXT:    slli a0, a0, 61
+; V-NEXT:    addi a0, a0, 1
+; V-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; V-NEXT:    vmulhu.vx v8, v8, a0
+; V-NEXT:    li a0, 61
+; V-NEXT:    vsrl.vx v8, v8, a0
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vdivu_vi_nxv8i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a0, 1
-; RV64-NEXT:    slli a0, a0, 61
-; RV64-NEXT:    addi a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vmulhu.vx v8, v8, a0
-; RV64-NEXT:    li a0, 61
-; RV64-NEXT:    vsrl.vx v8, v8, a0
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vdivu_vi_nxv8i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; ZVE64-NEXT:    vdivu.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = udiv <vscale x 8 x i64> %va, %splat
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll
rename from llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
rename to llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll
@@ -1,6 +1,6 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --force-update
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVE64
 
 define <vscale x 1 x i8> @vrem_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
 ; CHECK-LABEL: vrem_vv_nxv1i8:
@@ -312,31 +312,18 @@
 }
 
 define <vscale x 1 x i16> @vrem_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
-; RV32-LABEL: vrem_vi_nxv1i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV32-NEXT:    vmulh.vx v9, v8, a0
-; RV32-NEXT:    vsra.vi v9, v9, 1
-; RV32-NEXT:    vsrl.vi v10, v9, 15
-; RV32-NEXT:    vadd.vv v9, v9, v10
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv1i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV64-NEXT:    vmulh.vx v9, v8, a0
-; RV64-NEXT:    vsra.vi v9, v9, 1
-; RV64-NEXT:    vsrl.vi v10, v9, 15
-; RV64-NEXT:    vadd.vv v9, v9, v10
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vmulh.vx v9, v8, a0
+; CHECK-NEXT:    vsra.vi v9, v9, 1
+; CHECK-NEXT:    vsrl.vi v10, v9, 15
+; CHECK-NEXT:    vadd.vv v9, v9, v10
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i16> %va, %splat
@@ -366,31 +353,18 @@
 }
 
 define <vscale x 2 x i16> @vrem_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
-; RV32-LABEL: vrem_vi_nxv2i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
-; RV32-NEXT:    vmulh.vx v9, v8, a0
-; RV32-NEXT:    vsra.vi v9, v9, 1
-; RV32-NEXT:    vsrl.vi v10, v9, 15
-; RV32-NEXT:    vadd.vv v9, v9, v10
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv2i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
-; RV64-NEXT:    vmulh.vx v9, v8, a0
-; RV64-NEXT:    vsra.vi v9, v9, 1
-; RV64-NEXT:    vsrl.vi v10, v9, 15
-; RV64-NEXT:    vadd.vv v9, v9, v10
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vmulh.vx v9, v8, a0
+; CHECK-NEXT:    vsra.vi v9, v9, 1
+; CHECK-NEXT:    vsrl.vi v10, v9, 15
+; CHECK-NEXT:    vadd.vv v9, v9, v10
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i16> %va, %splat
@@ -420,31 +394,18 @@
 }
 
 define <vscale x 4 x i16> @vrem_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
-; RV32-LABEL: vrem_vi_nxv4i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
-; RV32-NEXT:    vmulh.vx v9, v8, a0
-; RV32-NEXT:    vsra.vi v9, v9, 1
-; RV32-NEXT:    vsrl.vi v10, v9, 15
-; RV32-NEXT:    vadd.vv v9, v9, v10
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv4i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
-; RV64-NEXT:    vmulh.vx v9, v8, a0
-; RV64-NEXT:    vsra.vi v9, v9, 1
-; RV64-NEXT:    vsrl.vi v10, v9, 15
-; RV64-NEXT:    vadd.vv v9, v9, v10
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vmulh.vx v9, v8, a0
+; CHECK-NEXT:    vsra.vi v9, v9, 1
+; CHECK-NEXT:    vsrl.vi v10, v9, 15
+; CHECK-NEXT:    vadd.vv v9, v9, v10
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i16> %va, %splat
@@ -474,31 +435,18 @@
 }
 
 define <vscale x 8 x i16> @vrem_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
-; RV32-LABEL: vrem_vi_nxv8i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; RV32-NEXT:    vmulh.vx v10, v8, a0
-; RV32-NEXT:    vsra.vi v10, v10, 1
-; RV32-NEXT:    vsrl.vi v12, v10, 15
-; RV32-NEXT:    vadd.vv v10, v10, v12
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v10
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv8i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; RV64-NEXT:    vmulh.vx v10, v8, a0
-; RV64-NEXT:    vsra.vi v10, v10, 1
-; RV64-NEXT:    vsrl.vi v12, v10, 15
-; RV64-NEXT:    vadd.vv v10, v10, v12
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v10
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vmulh.vx v10, v8, a0
+; CHECK-NEXT:    vsra.vi v10, v10, 1
+; CHECK-NEXT:    vsrl.vi v12, v10, 15
+; CHECK-NEXT:    vadd.vv v10, v10, v12
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v10
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i16> %va, %splat
@@ -528,31 +476,18 @@
 }
 
 define <vscale x 16 x i16> @vrem_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
-; RV32-LABEL: vrem_vi_nxv16i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
-; RV32-NEXT:    vmulh.vx v12, v8, a0
-; RV32-NEXT:    vsra.vi v12, v12, 1
-; RV32-NEXT:    vsrl.vi v16, v12, 15
-; RV32-NEXT:    vadd.vv v12, v12, v16
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v12
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv16i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
-; RV64-NEXT:    vmulh.vx v12, v8, a0
-; RV64-NEXT:    vsra.vi v12, v12, 1
-; RV64-NEXT:    vsrl.vi v16, v12, 15
-; RV64-NEXT:    vadd.vv v12, v12, v16
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v12
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vmulh.vx v12, v8, a0
+; CHECK-NEXT:    vsra.vi v12, v12, 1
+; CHECK-NEXT:    vsrl.vi v16, v12, 15
+; CHECK-NEXT:    vadd.vv v12, v12, v16
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v12
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i16> %va, %splat
@@ -582,31 +517,18 @@
 }
 
 define <vscale x 32 x i16> @vrem_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
-; RV32-LABEL: vrem_vi_nxv32i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
-; RV32-NEXT:    vmulh.vx v16, v8, a0
-; RV32-NEXT:    vsra.vi v16, v16, 1
-; RV32-NEXT:    vsrl.vi v24, v16, 15
-; RV32-NEXT:    vadd.vv v16, v16, v24
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv32i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
-; RV64-NEXT:    vmulh.vx v16, v8, a0
-; RV64-NEXT:    vsra.vi v16, v16, 1
-; RV64-NEXT:    vsrl.vi v24, v16, 15
-; RV64-NEXT:    vadd.vv v16, v16, v24
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v16
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addi a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vsra.vi v16, v16, 1
+; CHECK-NEXT:    vsrl.vi v24, v16, 15
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i16> %va, %splat
@@ -636,33 +558,19 @@
 }
 
 define <vscale x 1 x i32> @vrem_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv1i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; RV32-NEXT:    vmulh.vx v9, v8, a0
-; RV32-NEXT:    vsub.vv v9, v9, v8
-; RV32-NEXT:    vsrl.vi v10, v9, 31
-; RV32-NEXT:    vsra.vi v9, v9, 2
-; RV32-NEXT:    vadd.vv v9, v9, v10
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv1i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; RV64-NEXT:    vmulh.vx v9, v8, a0
-; RV64-NEXT:    vsub.vv v9, v9, v8
-; RV64-NEXT:    vsra.vi v9, v9, 2
-; RV64-NEXT:    vsrl.vi v10, v9, 31
-; RV64-NEXT:    vadd.vv v9, v9, v10
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmulh.vx v9, v8, a0
+; CHECK-NEXT:    vsub.vv v9, v9, v8
+; CHECK-NEXT:    vsrl.vi v10, v9, 31
+; CHECK-NEXT:    vsra.vi v9, v9, 2
+; CHECK-NEXT:    vadd.vv v9, v9, v10
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i32> %va, %splat
@@ -692,33 +600,19 @@
 }
 
 define <vscale x 2 x i32> @vrem_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv2i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; RV32-NEXT:    vmulh.vx v9, v8, a0
-; RV32-NEXT:    vsub.vv v9, v9, v8
-; RV32-NEXT:    vsrl.vi v10, v9, 31
-; RV32-NEXT:    vsra.vi v9, v9, 2
-; RV32-NEXT:    vadd.vv v9, v9, v10
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv2i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; RV64-NEXT:    vmulh.vx v9, v8, a0
-; RV64-NEXT:    vsub.vv v9, v9, v8
-; RV64-NEXT:    vsra.vi v9, v9, 2
-; RV64-NEXT:    vsrl.vi v10, v9, 31
-; RV64-NEXT:    vadd.vv v9, v9, v10
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmulh.vx v9, v8, a0
+; CHECK-NEXT:    vsub.vv v9, v9, v8
+; CHECK-NEXT:    vsrl.vi v10, v9, 31
+; CHECK-NEXT:    vsra.vi v9, v9, 2
+; CHECK-NEXT:    vadd.vv v9, v9, v10
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i32> %va, %splat
@@ -748,33 +642,19 @@
 }
 
 define <vscale x 4 x i32> @vrem_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv4i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; RV32-NEXT:    vmulh.vx v10, v8, a0
-; RV32-NEXT:    vsub.vv v10, v10, v8
-; RV32-NEXT:    vsrl.vi v12, v10, 31
-; RV32-NEXT:    vsra.vi v10, v10, 2
-; RV32-NEXT:    vadd.vv v10, v10, v12
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v10
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv4i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; RV64-NEXT:    vmulh.vx v10, v8, a0
-; RV64-NEXT:    vsub.vv v10, v10, v8
-; RV64-NEXT:    vsra.vi v10, v10, 2
-; RV64-NEXT:    vsrl.vi v12, v10, 31
-; RV64-NEXT:    vadd.vv v10, v10, v12
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v10
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmulh.vx v10, v8, a0
+; CHECK-NEXT:    vsub.vv v10, v10, v8
+; CHECK-NEXT:    vsrl.vi v12, v10, 31
+; CHECK-NEXT:    vsra.vi v10, v10, 2
+; CHECK-NEXT:    vadd.vv v10, v10, v12
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v10
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i32> %va, %splat
@@ -804,33 +684,19 @@
 }
 
 define <vscale x 8 x i32> @vrem_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv8i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT:    vmulh.vx v12, v8, a0
-; RV32-NEXT:    vsub.vv v12, v12, v8
-; RV32-NEXT:    vsrl.vi v16, v12, 31
-; RV32-NEXT:    vsra.vi v12, v12, 2
-; RV32-NEXT:    vadd.vv v12, v12, v16
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v12
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv8i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; RV64-NEXT:    vmulh.vx v12, v8, a0
-; RV64-NEXT:    vsub.vv v12, v12, v8
-; RV64-NEXT:    vsra.vi v12, v12, 2
-; RV64-NEXT:    vsrl.vi v16, v12, 31
-; RV64-NEXT:    vadd.vv v12, v12, v16
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v12
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulh.vx v12, v8, a0
+; CHECK-NEXT:    vsub.vv v12, v12, v8
+; CHECK-NEXT:    vsrl.vi v16, v12, 31
+; CHECK-NEXT:    vsra.vi v12, v12, 2
+; CHECK-NEXT:    vadd.vv v12, v12, v16
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v12
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i32> %va, %splat
@@ -860,33 +726,19 @@
 }
 
 define <vscale x 16 x i32> @vrem_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv16i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
-; RV32-NEXT:    vmulh.vx v16, v8, a0
-; RV32-NEXT:    vsub.vv v16, v16, v8
-; RV32-NEXT:    vsrl.vi v24, v16, 31
-; RV32-NEXT:    vsra.vi v16, v16, 2
-; RV32-NEXT:    vadd.vv v16, v16, v24
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv16i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
-; RV64-NEXT:    vmulh.vx v16, v8, a0
-; RV64-NEXT:    vsub.vv v16, v16, v8
-; RV64-NEXT:    vsra.vi v16, v16, 2
-; RV64-NEXT:    vsrl.vi v24, v16, 31
-; RV64-NEXT:    vadd.vv v16, v16, v24
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v16
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addi a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vsub.vv v16, v16, v8
+; CHECK-NEXT:    vsrl.vi v24, v16, 31
+; CHECK-NEXT:    vsra.vi v16, v16, 2
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i32> %va, %splat
@@ -904,24 +756,18 @@
 }
 
 define <vscale x 1 x i64> @vrem_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
-; RV32-LABEL: vrem_vx_nxv1i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vrem.vv v8, v8, v9
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vx_nxv1i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT:    vrem.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vx_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT:    addi a0, sp, 8
+; CHECK-NEXT:    vlse64.v v9, (a0), zero
+; CHECK-NEXT:    vrem.vv v8, v8, v9
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i64> %va, %splat
@@ -929,42 +775,35 @@
 }
 
 define <vscale x 1 x i64> @vrem_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
-; RV32-LABEL: vrem_vi_nxv1i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 748983
-; RV32-NEXT:    addi a0, a0, -586
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    lui a0, 898779
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vmulh.vv v9, v8, v9
-; RV32-NEXT:    li a0, 63
-; RV32-NEXT:    vsrl.vx v10, v9, a0
-; RV32-NEXT:    vsra.vi v9, v9, 1
-; RV32-NEXT:    vadd.vv v9, v9, v10
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vrem_vi_nxv1i64_0:
+; V:       # %bb.0:
+; V-NEXT:    addi sp, sp, -16
+; V-NEXT:    .cfi_def_cfa_offset 16
+; V-NEXT:    lui a0, 748983
+; V-NEXT:    addi a0, a0, -586
+; V-NEXT:    sw a0, 12(sp)
+; V-NEXT:    lui a0, 898779
+; V-NEXT:    addi a0, a0, 1755
+; V-NEXT:    sw a0, 8(sp)
+; V-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; V-NEXT:    addi a0, sp, 8
+; V-NEXT:    vlse64.v v9, (a0), zero
+; V-NEXT:    vmulh.vv v9, v8, v9
+; V-NEXT:    li a0, 63
+; V-NEXT:    vsrl.vx v10, v9, a0
+; V-NEXT:    vsra.vi v9, v9, 1
+; V-NEXT:    vadd.vv v9, v9, v10
+; V-NEXT:    li a0, -7
+; V-NEXT:    vnmsac.vx v8, a0, v9
+; V-NEXT:    addi sp, sp, 16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vrem_vi_nxv1i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, %hi(.LCPI56_0)
-; RV64-NEXT:    ld a0, %lo(.LCPI56_0)(a0)
-; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT:    vmulh.vx v9, v8, a0
-; RV64-NEXT:    li a0, 63
-; RV64-NEXT:    vsrl.vx v10, v9, a0
-; RV64-NEXT:    vsra.vi v9, v9, 1
-; RV64-NEXT:    vadd.vv v9, v9, v10
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vrem_vi_nxv1i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; ZVE64-NEXT:    vrem.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i64> %va, %splat
@@ -982,24 +821,18 @@
 }
 
 define <vscale x 2 x i64> @vrem_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
-; RV32-LABEL: vrem_vx_nxv2i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v10, (a0), zero
-; RV32-NEXT:    vrem.vv v8, v8, v10
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vx_nxv2i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
-; RV64-NEXT:    vrem.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vx_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT:    addi a0, sp, 8
+; CHECK-NEXT:    vlse64.v v10, (a0), zero
+; CHECK-NEXT:    vrem.vv v8, v8, v10
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i64> %va, %splat
@@ -1007,42 +840,35 @@
 }
 
 define <vscale x 2 x i64> @vrem_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
-; RV32-LABEL: vrem_vi_nxv2i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 748983
-; RV32-NEXT:    addi a0, a0, -586
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    lui a0, 898779
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v10, (a0), zero
-; RV32-NEXT:    vmulh.vv v10, v8, v10
-; RV32-NEXT:    li a0, 63
-; RV32-NEXT:    vsrl.vx v12, v10, a0
-; RV32-NEXT:    vsra.vi v10, v10, 1
-; RV32-NEXT:    vadd.vv v10, v10, v12
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v10
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vrem_vi_nxv2i64_0:
+; V:       # %bb.0:
+; V-NEXT:    addi sp, sp, -16
+; V-NEXT:    .cfi_def_cfa_offset 16
+; V-NEXT:    lui a0, 748983
+; V-NEXT:    addi a0, a0, -586
+; V-NEXT:    sw a0, 12(sp)
+; V-NEXT:    lui a0, 898779
+; V-NEXT:    addi a0, a0, 1755
+; V-NEXT:    sw a0, 8(sp)
+; V-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
+; V-NEXT:    addi a0, sp, 8
+; V-NEXT:    vlse64.v v10, (a0), zero
+; V-NEXT:    vmulh.vv v10, v8, v10
+; V-NEXT:    li a0, 63
+; V-NEXT:    vsrl.vx v12, v10, a0
+; V-NEXT:    vsra.vi v10, v10, 1
+; V-NEXT:    vadd.vv v10, v10, v12
+; V-NEXT:    li a0, -7
+; V-NEXT:    vnmsac.vx v8, a0, v10
+; V-NEXT:    addi sp, sp, 16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vrem_vi_nxv2i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, %hi(.LCPI59_0)
-; RV64-NEXT:    ld a0, %lo(.LCPI59_0)(a0)
-; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
-; RV64-NEXT:    vmulh.vx v10, v8, a0
-; RV64-NEXT:    li a0, 63
-; RV64-NEXT:    vsrl.vx v12, v10, a0
-; RV64-NEXT:    vsra.vi v10, v10, 1
-; RV64-NEXT:    vadd.vv v10, v10, v12
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v10
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vrem_vi_nxv2i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; ZVE64-NEXT:    vrem.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i64> %va, %splat
@@ -1060,24 +886,18 @@
 }
 
 define <vscale x 4 x i64> @vrem_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
-; RV32-LABEL: vrem_vx_nxv4i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v12, (a0), zero
-; RV32-NEXT:    vrem.vv v8, v8, v12
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vx_nxv4i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
-; RV64-NEXT:    vrem.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vx_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT:    addi a0, sp, 8
+; CHECK-NEXT:    vlse64.v v12, (a0), zero
+; CHECK-NEXT:    vrem.vv v8, v8, v12
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i64> %va, %splat
@@ -1085,42 +905,35 @@
 }
 
 define <vscale x 4 x i64> @vrem_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
-; RV32-LABEL: vrem_vi_nxv4i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 748983
-; RV32-NEXT:    addi a0, a0, -586
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    lui a0, 898779
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v12, (a0), zero
-; RV32-NEXT:    vmulh.vv v12, v8, v12
-; RV32-NEXT:    li a0, 63
-; RV32-NEXT:    vsrl.vx v16, v12, a0
-; RV32-NEXT:    vsra.vi v12, v12, 1
-; RV32-NEXT:    vadd.vv v12, v12, v16
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v12
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vrem_vi_nxv4i64_0:
+; V:       # %bb.0:
+; V-NEXT:    addi sp, sp, -16
+; V-NEXT:    .cfi_def_cfa_offset 16
+; V-NEXT:    lui a0, 748983
+; V-NEXT:    addi a0, a0, -586
+; V-NEXT:    sw a0, 12(sp)
+; V-NEXT:    lui a0, 898779
+; V-NEXT:    addi a0, a0, 1755
+; V-NEXT:    sw a0, 8(sp)
+; V-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
+; V-NEXT:    addi a0, sp, 8
+; V-NEXT:    vlse64.v v12, (a0), zero
+; V-NEXT:    vmulh.vv v12, v8, v12
+; V-NEXT:    li a0, 63
+; V-NEXT:    vsrl.vx v16, v12, a0
+; V-NEXT:    vsra.vi v12, v12, 1
+; V-NEXT:    vadd.vv v12, v12, v16
+; V-NEXT:    li a0, -7
+; V-NEXT:    vnmsac.vx v8, a0, v12
+; V-NEXT:    addi sp, sp, 16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vrem_vi_nxv4i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, %hi(.LCPI62_0)
-; RV64-NEXT:    ld a0, %lo(.LCPI62_0)(a0)
-; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
-; RV64-NEXT:    vmulh.vx v12, v8, a0
-; RV64-NEXT:    li a0, 63
-; RV64-NEXT:    vsrl.vx v16, v12, a0
-; RV64-NEXT:    vsra.vi v12, v12, 1
-; RV64-NEXT:    vadd.vv v12, v12, v16
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v12
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vrem_vi_nxv4i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; ZVE64-NEXT:    vrem.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i64> %va, %splat
@@ -1138,24 +951,18 @@
 }
 
 define <vscale x 8 x i64> @vrem_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; RV32-LABEL: vrem_vx_nxv8i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vrem.vv v8, v8, v16
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vx_nxv8i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vrem.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT:    addi a0, sp, 8
+; CHECK-NEXT:    vlse64.v v16, (a0), zero
+; CHECK-NEXT:    vrem.vv v8, v8, v16
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i64> %va, %splat
@@ -1163,42 +970,35 @@
 }
 
 define <vscale x 8 x i64> @vrem_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
-; RV32-LABEL: vrem_vi_nxv8i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 748983
-; RV32-NEXT:    addi a0, a0, -586
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    lui a0, 898779
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vmulh.vv v16, v8, v16
-; RV32-NEXT:    li a0, 63
-; RV32-NEXT:    vsrl.vx v24, v16, a0
-; RV32-NEXT:    vsra.vi v16, v16, 1
-; RV32-NEXT:    vadd.vv v16, v16, v24
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v16
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vrem_vi_nxv8i64_0:
+; V:       # %bb.0:
+; V-NEXT:    addi sp, sp, -16
+; V-NEXT:    .cfi_def_cfa_offset 16
+; V-NEXT:    lui a0, 748983
+; V-NEXT:    addi a0, a0, -586
+; V-NEXT:    sw a0, 12(sp)
+; V-NEXT:    lui a0, 898779
+; V-NEXT:    addi a0, a0, 1755
+; V-NEXT:    sw a0, 8(sp)
+; V-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; V-NEXT:    addi a0, sp, 8
+; V-NEXT:    vlse64.v v16, (a0), zero
+; V-NEXT:    vmulh.vv v16, v8, v16
+; V-NEXT:    li a0, 63
+; V-NEXT:    vsrl.vx v24, v16, a0
+; V-NEXT:    vsra.vi v16, v16, 1
+; V-NEXT:    vadd.vv v16, v16, v24
+; V-NEXT:    li a0, -7
+; V-NEXT:    vnmsac.vx v8, a0, v16
+; V-NEXT:    addi sp, sp, 16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vrem_vi_nxv8i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, %hi(.LCPI65_0)
-; RV64-NEXT:    ld a0, %lo(.LCPI65_0)(a0)
-; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vmulh.vx v16, v8, a0
-; RV64-NEXT:    li a0, 63
-; RV64-NEXT:    vsrl.vx v24, v16, a0
-; RV64-NEXT:    vsra.vi v16, v16, 1
-; RV64-NEXT:    vadd.vv v16, v16, v24
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v16
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vrem_vi_nxv8i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; ZVE64-NEXT:    vrem.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i64> %va, %splat
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll
rename from llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
rename to llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll
@@ -1,6 +1,6 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --force-update
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVE64
 
 define <vscale x 1 x i8> @vrem_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
 ; CHECK-LABEL: vrem_vv_nxv1i8:
@@ -312,31 +312,18 @@
 }
 
 define <vscale x 1 x i16> @vrem_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
-; RV32-LABEL: vrem_vi_nxv1i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV32-NEXT:    vmulh.vx v9, v8, a0
-; RV32-NEXT:    vsra.vi v9, v9, 1
-; RV32-NEXT:    vsrl.vi v10, v9, 15
-; RV32-NEXT:    vadd.vv v9, v9, v10
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv1i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV64-NEXT:    vmulh.vx v9, v8, a0
-; RV64-NEXT:    vsra.vi v9, v9, 1
-; RV64-NEXT:    vsrl.vi v10, v9, 15
-; RV64-NEXT:    vadd.vv v9, v9, v10
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vmulh.vx v9, v8, a0
+; CHECK-NEXT:    vsra.vi v9, v9, 1
+; CHECK-NEXT:    vsrl.vi v10, v9, 15
+; CHECK-NEXT:    vadd.vv v9, v9, v10
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i16> %va, %splat
@@ -366,31 +353,18 @@
 }
 
 define <vscale x 2 x i16> @vrem_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
-; RV32-LABEL: vrem_vi_nxv2i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
-; RV32-NEXT:    vmulh.vx v9, v8, a0
-; RV32-NEXT:    vsra.vi v9, v9, 1
-; RV32-NEXT:    vsrl.vi v10, v9, 15
-; RV32-NEXT:    vadd.vv v9, v9, v10
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv2i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
-; RV64-NEXT:    vmulh.vx v9, v8, a0
-; RV64-NEXT:    vsra.vi v9, v9, 1
-; RV64-NEXT:    vsrl.vi v10, v9, 15
-; RV64-NEXT:    vadd.vv v9, v9, v10
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vmulh.vx v9, v8, a0
+; CHECK-NEXT:    vsra.vi v9, v9, 1
+; CHECK-NEXT:    vsrl.vi v10, v9, 15
+; CHECK-NEXT:    vadd.vv v9, v9, v10
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i16> %va, %splat
@@ -420,31 +394,18 @@
 }
 
 define <vscale x 4 x i16> @vrem_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
-; RV32-LABEL: vrem_vi_nxv4i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
-; RV32-NEXT:    vmulh.vx v9, v8, a0
-; RV32-NEXT:    vsra.vi v9, v9, 1
-; RV32-NEXT:    vsrl.vi v10, v9, 15
-; RV32-NEXT:    vadd.vv v9, v9, v10
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv4i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
-; RV64-NEXT:    vmulh.vx v9, v8, a0
-; RV64-NEXT:    vsra.vi v9, v9, 1
-; RV64-NEXT:    vsrl.vi v10, v9, 15
-; RV64-NEXT:    vadd.vv v9, v9, v10
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vmulh.vx v9, v8, a0
+; CHECK-NEXT:    vsra.vi v9, v9, 1
+; CHECK-NEXT:    vsrl.vi v10, v9, 15
+; CHECK-NEXT:    vadd.vv v9, v9, v10
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i16> %va, %splat
@@ -474,31 +435,18 @@
 }
 
 define <vscale x 8 x i16> @vrem_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
-; RV32-LABEL: vrem_vi_nxv8i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; RV32-NEXT:    vmulh.vx v10, v8, a0
-; RV32-NEXT:    vsra.vi v10, v10, 1
-; RV32-NEXT:    vsrl.vi v12, v10, 15
-; RV32-NEXT:    vadd.vv v10, v10, v12
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v10
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv8i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; RV64-NEXT:    vmulh.vx v10, v8, a0
-; RV64-NEXT:    vsra.vi v10, v10, 1
-; RV64-NEXT:    vsrl.vi v12, v10, 15
-; RV64-NEXT:    vadd.vv v10, v10, v12
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v10
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vmulh.vx v10, v8, a0
+; CHECK-NEXT:    vsra.vi v10, v10, 1
+; CHECK-NEXT:    vsrl.vi v12, v10, 15
+; CHECK-NEXT:    vadd.vv v10, v10, v12
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v10
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i16> %va, %splat
@@ -528,31 +476,18 @@
 }
 
 define <vscale x 16 x i16> @vrem_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
-; RV32-LABEL: vrem_vi_nxv16i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
-; RV32-NEXT:    vmulh.vx v12, v8, a0
-; RV32-NEXT:    vsra.vi v12, v12, 1
-; RV32-NEXT:    vsrl.vi v16, v12, 15
-; RV32-NEXT:    vadd.vv v12, v12, v16
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v12
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv16i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
-; RV64-NEXT:    vmulh.vx v12, v8, a0
-; RV64-NEXT:    vsra.vi v12, v12, 1
-; RV64-NEXT:    vsrl.vi v16, v12, 15
-; RV64-NEXT:    vadd.vv v12, v12, v16
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v12
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vmulh.vx v12, v8, a0
+; CHECK-NEXT:    vsra.vi v12, v12, 1
+; CHECK-NEXT:    vsrl.vi v16, v12, 15
+; CHECK-NEXT:    vadd.vv v12, v12, v16
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v12
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i16> %va, %splat
@@ -582,31 +517,18 @@
 }
 
 define <vscale x 32 x i16> @vrem_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
-; RV32-LABEL: vrem_vi_nxv32i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 1048571
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
-; RV32-NEXT:    vmulh.vx v16, v8, a0
-; RV32-NEXT:    vsra.vi v16, v16, 1
-; RV32-NEXT:    vsrl.vi v24, v16, 15
-; RV32-NEXT:    vadd.vv v16, v16, v24
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv32i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 1048571
-; RV64-NEXT:    addiw a0, a0, 1755
-; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
-; RV64-NEXT:    vmulh.vx v16, v8, a0
-; RV64-NEXT:    vsra.vi v16, v16, 1
-; RV64-NEXT:    vsrl.vi v24, v16, 15
-; RV64-NEXT:    vadd.vv v16, v16, v24
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v16
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 1048571
+; CHECK-NEXT:    addiw a0, a0, 1755
+; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vsra.vi v16, v16, 1
+; CHECK-NEXT:    vsrl.vi v24, v16, 15
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = srem <vscale x 32 x i16> %va, %splat
@@ -636,33 +558,19 @@
 }
 
 define <vscale x 1 x i32> @vrem_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv1i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; RV32-NEXT:    vmulh.vx v9, v8, a0
-; RV32-NEXT:    vsub.vv v9, v9, v8
-; RV32-NEXT:    vsrl.vi v10, v9, 31
-; RV32-NEXT:    vsra.vi v9, v9, 2
-; RV32-NEXT:    vadd.vv v9, v9, v10
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv1i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; RV64-NEXT:    vmulh.vx v9, v8, a0
-; RV64-NEXT:    vsub.vv v9, v9, v8
-; RV64-NEXT:    vsra.vi v9, v9, 2
-; RV64-NEXT:    vsrl.vi v10, v9, 31
-; RV64-NEXT:    vadd.vv v9, v9, v10
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmulh.vx v9, v8, a0
+; CHECK-NEXT:    vsub.vv v9, v9, v8
+; CHECK-NEXT:    vsra.vi v9, v9, 2
+; CHECK-NEXT:    vsrl.vi v10, v9, 31
+; CHECK-NEXT:    vadd.vv v9, v9, v10
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i32> %va, %splat
@@ -692,33 +600,19 @@
 }
 
 define <vscale x 2 x i32> @vrem_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv2i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; RV32-NEXT:    vmulh.vx v9, v8, a0
-; RV32-NEXT:    vsub.vv v9, v9, v8
-; RV32-NEXT:    vsrl.vi v10, v9, 31
-; RV32-NEXT:    vsra.vi v9, v9, 2
-; RV32-NEXT:    vadd.vv v9, v9, v10
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv2i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; RV64-NEXT:    vmulh.vx v9, v8, a0
-; RV64-NEXT:    vsub.vv v9, v9, v8
-; RV64-NEXT:    vsra.vi v9, v9, 2
-; RV64-NEXT:    vsrl.vi v10, v9, 31
-; RV64-NEXT:    vadd.vv v9, v9, v10
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmulh.vx v9, v8, a0
+; CHECK-NEXT:    vsub.vv v9, v9, v8
+; CHECK-NEXT:    vsra.vi v9, v9, 2
+; CHECK-NEXT:    vsrl.vi v10, v9, 31
+; CHECK-NEXT:    vadd.vv v9, v9, v10
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i32> %va, %splat
@@ -748,33 +642,19 @@
 }
 
 define <vscale x 4 x i32> @vrem_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv4i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; RV32-NEXT:    vmulh.vx v10, v8, a0
-; RV32-NEXT:    vsub.vv v10, v10, v8
-; RV32-NEXT:    vsrl.vi v12, v10, 31
-; RV32-NEXT:    vsra.vi v10, v10, 2
-; RV32-NEXT:    vadd.vv v10, v10, v12
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v10
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv4i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; RV64-NEXT:    vmulh.vx v10, v8, a0
-; RV64-NEXT:    vsub.vv v10, v10, v8
-; RV64-NEXT:    vsra.vi v10, v10, 2
-; RV64-NEXT:    vsrl.vi v12, v10, 31
-; RV64-NEXT:    vadd.vv v10, v10, v12
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v10
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmulh.vx v10, v8, a0
+; CHECK-NEXT:    vsub.vv v10, v10, v8
+; CHECK-NEXT:    vsra.vi v10, v10, 2
+; CHECK-NEXT:    vsrl.vi v12, v10, 31
+; CHECK-NEXT:    vadd.vv v10, v10, v12
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v10
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i32> %va, %splat
@@ -804,33 +684,19 @@
 }
 
 define <vscale x 8 x i32> @vrem_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv8i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT:    vmulh.vx v12, v8, a0
-; RV32-NEXT:    vsub.vv v12, v12, v8
-; RV32-NEXT:    vsrl.vi v16, v12, 31
-; RV32-NEXT:    vsra.vi v12, v12, 2
-; RV32-NEXT:    vadd.vv v12, v12, v16
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v12
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv8i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; RV64-NEXT:    vmulh.vx v12, v8, a0
-; RV64-NEXT:    vsub.vv v12, v12, v8
-; RV64-NEXT:    vsra.vi v12, v12, 2
-; RV64-NEXT:    vsrl.vi v16, v12, 31
-; RV64-NEXT:    vadd.vv v12, v12, v16
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v12
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulh.vx v12, v8, a0
+; CHECK-NEXT:    vsub.vv v12, v12, v8
+; CHECK-NEXT:    vsra.vi v12, v12, 2
+; CHECK-NEXT:    vsrl.vi v16, v12, 31
+; CHECK-NEXT:    vadd.vv v12, v12, v16
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v12
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i32> %va, %splat
@@ -860,33 +726,19 @@
 }
 
 define <vscale x 16 x i32> @vrem_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
-; RV32-LABEL: vrem_vi_nxv16i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 449390
-; RV32-NEXT:    addi a0, a0, -1171
-; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
-; RV32-NEXT:    vmulh.vx v16, v8, a0
-; RV32-NEXT:    vsub.vv v16, v16, v8
-; RV32-NEXT:    vsrl.vi v24, v16, 31
-; RV32-NEXT:    vsra.vi v16, v16, 2
-; RV32-NEXT:    vadd.vv v16, v16, v24
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vi_nxv16i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 449390
-; RV64-NEXT:    addiw a0, a0, -1171
-; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
-; RV64-NEXT:    vmulh.vx v16, v8, a0
-; RV64-NEXT:    vsub.vv v16, v16, v8
-; RV64-NEXT:    vsra.vi v16, v16, 2
-; RV64-NEXT:    vsrl.vi v24, v16, 31
-; RV64-NEXT:    vadd.vv v16, v16, v24
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v16
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vi_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 449390
+; CHECK-NEXT:    addiw a0, a0, -1171
+; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
+; CHECK-NEXT:    vmulh.vx v16, v8, a0
+; CHECK-NEXT:    vsub.vv v16, v16, v8
+; CHECK-NEXT:    vsra.vi v16, v16, 2
+; CHECK-NEXT:    vsrl.vi v24, v16, 31
+; CHECK-NEXT:    vadd.vv v16, v16, v24
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = srem <vscale x 16 x i32> %va, %splat
@@ -904,24 +756,11 @@
 }
 
 define <vscale x 1 x i64> @vrem_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
-; RV32-LABEL: vrem_vx_nxv1i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vrem.vv v8, v8, v9
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vx_nxv1i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT:    vrem.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vx_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i64> %va, %splat
@@ -929,42 +768,26 @@
 }
 
 define <vscale x 1 x i64> @vrem_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
-; RV32-LABEL: vrem_vi_nxv1i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 748983
-; RV32-NEXT:    addi a0, a0, -586
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    lui a0, 898779
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vmulh.vv v9, v8, v9
-; RV32-NEXT:    li a0, 63
-; RV32-NEXT:    vsrl.vx v10, v9, a0
-; RV32-NEXT:    vsra.vi v9, v9, 1
-; RV32-NEXT:    vadd.vv v9, v9, v10
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vrem_vi_nxv1i64_0:
+; V:       # %bb.0:
+; V-NEXT:    lui a0, %hi(.LCPI56_0)
+; V-NEXT:    ld a0, %lo(.LCPI56_0)(a0)
+; V-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; V-NEXT:    vmulh.vx v9, v8, a0
+; V-NEXT:    li a0, 63
+; V-NEXT:    vsrl.vx v10, v9, a0
+; V-NEXT:    vsra.vi v9, v9, 1
+; V-NEXT:    vadd.vv v9, v9, v10
+; V-NEXT:    li a0, -7
+; V-NEXT:    vnmsac.vx v8, a0, v9
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vrem_vi_nxv1i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, %hi(.LCPI56_0)
-; RV64-NEXT:    ld a0, %lo(.LCPI56_0)(a0)
-; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT:    vmulh.vx v9, v8, a0
-; RV64-NEXT:    li a0, 63
-; RV64-NEXT:    vsrl.vx v10, v9, a0
-; RV64-NEXT:    vsra.vi v9, v9, 1
-; RV64-NEXT:    vadd.vv v9, v9, v10
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vrem_vi_nxv1i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; ZVE64-NEXT:    vrem.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = srem <vscale x 1 x i64> %va, %splat
@@ -982,24 +805,11 @@
 }
 
 define <vscale x 2 x i64> @vrem_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
-; RV32-LABEL: vrem_vx_nxv2i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v10, (a0), zero
-; RV32-NEXT:    vrem.vv v8, v8, v10
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vx_nxv2i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
-; RV64-NEXT:    vrem.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vx_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i64> %va, %splat
@@ -1007,42 +817,26 @@
 }
 
 define <vscale x 2 x i64> @vrem_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
-; RV32-LABEL: vrem_vi_nxv2i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 748983
-; RV32-NEXT:    addi a0, a0, -586
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    lui a0, 898779
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v10, (a0), zero
-; RV32-NEXT:    vmulh.vv v10, v8, v10
-; RV32-NEXT:    li a0, 63
-; RV32-NEXT:    vsrl.vx v12, v10, a0
-; RV32-NEXT:    vsra.vi v10, v10, 1
-; RV32-NEXT:    vadd.vv v10, v10, v12
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v10
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vrem_vi_nxv2i64_0:
+; V:       # %bb.0:
+; V-NEXT:    lui a0, %hi(.LCPI59_0)
+; V-NEXT:    ld a0, %lo(.LCPI59_0)(a0)
+; V-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; V-NEXT:    vmulh.vx v10, v8, a0
+; V-NEXT:    li a0, 63
+; V-NEXT:    vsrl.vx v12, v10, a0
+; V-NEXT:    vsra.vi v10, v10, 1
+; V-NEXT:    vadd.vv v10, v10, v12
+; V-NEXT:    li a0, -7
+; V-NEXT:    vnmsac.vx v8, a0, v10
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vrem_vi_nxv2i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, %hi(.LCPI59_0)
-; RV64-NEXT:    ld a0, %lo(.LCPI59_0)(a0)
-; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
-; RV64-NEXT:    vmulh.vx v10, v8, a0
-; RV64-NEXT:    li a0, 63
-; RV64-NEXT:    vsrl.vx v12, v10, a0
-; RV64-NEXT:    vsra.vi v10, v10, 1
-; RV64-NEXT:    vadd.vv v10, v10, v12
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v10
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vrem_vi_nxv2i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; ZVE64-NEXT:    vrem.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = srem <vscale x 2 x i64> %va, %splat
@@ -1060,24 +854,11 @@
 }
 
 define <vscale x 4 x i64> @vrem_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
-; RV32-LABEL: vrem_vx_nxv4i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v12, (a0), zero
-; RV32-NEXT:    vrem.vv v8, v8, v12
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vx_nxv4i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
-; RV64-NEXT:    vrem.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vx_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i64> %va, %splat
@@ -1085,42 +866,26 @@
 }
 
 define <vscale x 4 x i64> @vrem_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
-; RV32-LABEL: vrem_vi_nxv4i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 748983
-; RV32-NEXT:    addi a0, a0, -586
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    lui a0, 898779
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v12, (a0), zero
-; RV32-NEXT:    vmulh.vv v12, v8, v12
-; RV32-NEXT:    li a0, 63
-; RV32-NEXT:    vsrl.vx v16, v12, a0
-; RV32-NEXT:    vsra.vi v12, v12, 1
-; RV32-NEXT:    vadd.vv v12, v12, v16
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v12
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vrem_vi_nxv4i64_0:
+; V:       # %bb.0:
+; V-NEXT:    lui a0, %hi(.LCPI62_0)
+; V-NEXT:    ld a0, %lo(.LCPI62_0)(a0)
+; V-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; V-NEXT:    vmulh.vx v12, v8, a0
+; V-NEXT:    li a0, 63
+; V-NEXT:    vsrl.vx v16, v12, a0
+; V-NEXT:    vsra.vi v12, v12, 1
+; V-NEXT:    vadd.vv v12, v12, v16
+; V-NEXT:    li a0, -7
+; V-NEXT:    vnmsac.vx v8, a0, v12
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vrem_vi_nxv4i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, %hi(.LCPI62_0)
-; RV64-NEXT:    ld a0, %lo(.LCPI62_0)(a0)
-; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
-; RV64-NEXT:    vmulh.vx v12, v8, a0
-; RV64-NEXT:    li a0, 63
-; RV64-NEXT:    vsrl.vx v16, v12, a0
-; RV64-NEXT:    vsra.vi v12, v12, 1
-; RV64-NEXT:    vadd.vv v12, v12, v16
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v12
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vrem_vi_nxv4i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; ZVE64-NEXT:    vrem.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = srem <vscale x 4 x i64> %va, %splat
@@ -1138,24 +903,11 @@
 }
 
 define <vscale x 8 x i64> @vrem_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; RV32-LABEL: vrem_vx_nxv8i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vrem.vv v8, v8, v16
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vrem_vx_nxv8i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vrem.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vrem_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; CHECK-NEXT:    vrem.vx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i64> %va, %splat
@@ -1163,42 +915,26 @@
 }
 
 define <vscale x 8 x i64> @vrem_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
-; RV32-LABEL: vrem_vi_nxv8i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 748983
-; RV32-NEXT:    addi a0, a0, -586
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    lui a0, 898779
-; RV32-NEXT:    addi a0, a0, 1755
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vmulh.vv v16, v8, v16
-; RV32-NEXT:    li a0, 63
-; RV32-NEXT:    vsrl.vx v24, v16, a0
-; RV32-NEXT:    vsra.vi v16, v16, 1
-; RV32-NEXT:    vadd.vv v16, v16, v24
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v16
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vrem_vi_nxv8i64_0:
+; V:       # %bb.0:
+; V-NEXT:    lui a0, %hi(.LCPI65_0)
+; V-NEXT:    ld a0, %lo(.LCPI65_0)(a0)
+; V-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; V-NEXT:    vmulh.vx v16, v8, a0
+; V-NEXT:    li a0, 63
+; V-NEXT:    vsrl.vx v24, v16, a0
+; V-NEXT:    vsra.vi v16, v16, 1
+; V-NEXT:    vadd.vv v16, v16, v24
+; V-NEXT:    li a0, -7
+; V-NEXT:    vnmsac.vx v8, a0, v16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vrem_vi_nxv8i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, %hi(.LCPI65_0)
-; RV64-NEXT:    ld a0, %lo(.LCPI65_0)(a0)
-; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vmulh.vx v16, v8, a0
-; RV64-NEXT:    li a0, 63
-; RV64-NEXT:    vsrl.vx v24, v16, a0
-; RV64-NEXT:    vsra.vi v16, v16, 1
-; RV64-NEXT:    vadd.vv v16, v16, v24
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v16
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vrem_vi_nxv8i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; ZVE64-NEXT:    vrem.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = srem <vscale x 8 x i64> %va, %splat
diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
rename from llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
rename to llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
@@ -1,6 +1,6 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --force-update
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVE64
 
 define <vscale x 1 x i8> @vremu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
 ; CHECK-LABEL: vremu_vv_nxv1i8:
@@ -291,27 +291,16 @@
 }
 
 define <vscale x 1 x i16> @vremu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
-; RV32-LABEL: vremu_vi_nxv1i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV32-NEXT:    vmulhu.vx v9, v8, a0
-; RV32-NEXT:    vsrl.vi v9, v9, 13
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv1i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV64-NEXT:    vmulhu.vx v9, v8, a0
-; RV64-NEXT:    vsrl.vi v9, v9, 13
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vmulhu.vx v9, v8, a0
+; CHECK-NEXT:    vsrl.vi v9, v9, 13
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i16> %va, %splat
@@ -341,27 +330,16 @@
 }
 
 define <vscale x 2 x i16> @vremu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
-; RV32-LABEL: vremu_vi_nxv2i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
-; RV32-NEXT:    vmulhu.vx v9, v8, a0
-; RV32-NEXT:    vsrl.vi v9, v9, 13
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv2i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
-; RV64-NEXT:    vmulhu.vx v9, v8, a0
-; RV64-NEXT:    vsrl.vi v9, v9, 13
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v9, v8, a0
+; CHECK-NEXT:    vsrl.vi v9, v9, 13
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i16> %va, %splat
@@ -391,27 +369,16 @@
 }
 
 define <vscale x 4 x i16> @vremu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
-; RV32-LABEL: vremu_vi_nxv4i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
-; RV32-NEXT:    vmulhu.vx v9, v8, a0
-; RV32-NEXT:    vsrl.vi v9, v9, 13
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv4i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
-; RV64-NEXT:    vmulhu.vx v9, v8, a0
-; RV64-NEXT:    vsrl.vi v9, v9, 13
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vmulhu.vx v9, v8, a0
+; CHECK-NEXT:    vsrl.vi v9, v9, 13
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i16> %va, %splat
@@ -441,27 +408,16 @@
 }
 
 define <vscale x 8 x i16> @vremu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
-; RV32-LABEL: vremu_vi_nxv8i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; RV32-NEXT:    vmulhu.vx v10, v8, a0
-; RV32-NEXT:    vsrl.vi v10, v10, 13
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v10
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv8i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; RV64-NEXT:    vmulhu.vx v10, v8, a0
-; RV64-NEXT:    vsrl.vi v10, v10, 13
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v10
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v10, v8, a0
+; CHECK-NEXT:    vsrl.vi v10, v10, 13
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v10
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i16> %va, %splat
@@ -491,27 +447,16 @@
 }
 
 define <vscale x 16 x i16> @vremu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
-; RV32-LABEL: vremu_vi_nxv16i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
-; RV32-NEXT:    vmulhu.vx v12, v8, a0
-; RV32-NEXT:    vsrl.vi v12, v12, 13
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v12
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv16i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
-; RV64-NEXT:    vmulhu.vx v12, v8, a0
-; RV64-NEXT:    vsrl.vi v12, v12, 13
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v12
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vx v12, v8, a0
+; CHECK-NEXT:    vsrl.vi v12, v12, 13
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v12
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i16> %va, %splat
@@ -541,27 +486,16 @@
 }
 
 define <vscale x 32 x i16> @vremu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
-; RV32-LABEL: vremu_vi_nxv32i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
-; RV32-NEXT:    vmulhu.vx v16, v8, a0
-; RV32-NEXT:    vsrl.vi v16, v16, 13
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv32i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
-; RV64-NEXT:    vmulhu.vx v16, v8, a0
-; RV64-NEXT:    vsrl.vi v16, v16, 13
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v16
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 13
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = urem <vscale x 32 x i16> %va, %splat
@@ -591,27 +525,16 @@
 }
 
 define <vscale x 1 x i32> @vremu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
-; RV32-LABEL: vremu_vi_nxv1i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; RV32-NEXT:    vmulhu.vx v9, v8, a0
-; RV32-NEXT:    vsrl.vi v9, v9, 29
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv1i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; RV64-NEXT:    vmulhu.vx v9, v8, a0
-; RV64-NEXT:    vsrl.vi v9, v9, 29
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v9, v8, a0
+; CHECK-NEXT:    vsrl.vi v9, v9, 29
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i32> %va, %splat
@@ -641,27 +564,16 @@
 }
 
 define <vscale x 2 x i32> @vremu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
-; RV32-LABEL: vremu_vi_nxv2i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; RV32-NEXT:    vmulhu.vx v9, v8, a0
-; RV32-NEXT:    vsrl.vi v9, v9, 29
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv2i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; RV64-NEXT:    vmulhu.vx v9, v8, a0
-; RV64-NEXT:    vsrl.vi v9, v9, 29
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmulhu.vx v9, v8, a0
+; CHECK-NEXT:    vsrl.vi v9, v9, 29
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i32> %va, %splat
@@ -691,27 +603,16 @@
 }
 
 define <vscale x 4 x i32> @vremu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
-; RV32-LABEL: vremu_vi_nxv4i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; RV32-NEXT:    vmulhu.vx v10, v8, a0
-; RV32-NEXT:    vsrl.vi v10, v10, 29
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v10
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv4i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; RV64-NEXT:    vmulhu.vx v10, v8, a0
-; RV64-NEXT:    vsrl.vi v10, v10, 29
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v10
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v10, v8, a0
+; CHECK-NEXT:    vsrl.vi v10, v10, 29
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v10
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i32> %va, %splat
@@ -741,27 +642,16 @@
 }
 
 define <vscale x 8 x i32> @vremu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; RV32-LABEL: vremu_vi_nxv8i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT:    vmulhu.vx v12, v8, a0
-; RV32-NEXT:    vsrl.vi v12, v12, 29
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v12
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv8i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; RV64-NEXT:    vmulhu.vx v12, v8, a0
-; RV64-NEXT:    vsrl.vi v12, v12, 29
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v12
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vx v12, v8, a0
+; CHECK-NEXT:    vsrl.vi v12, v12, 29
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v12
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i32> %va, %splat
@@ -791,27 +681,16 @@
 }
 
 define <vscale x 16 x i32> @vremu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
-; RV32-LABEL: vremu_vi_nxv16i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
-; RV32-NEXT:    vmulhu.vx v16, v8, a0
-; RV32-NEXT:    vsrl.vi v16, v16, 29
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv16i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
-; RV64-NEXT:    vmulhu.vx v16, v8, a0
-; RV64-NEXT:    vsrl.vi v16, v16, 29
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v16
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addi a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 29
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i32> %va, %splat
@@ -829,24 +708,18 @@
 }
 
 define <vscale x 1 x i64> @vremu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
-; RV32-LABEL: vremu_vx_nxv1i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vremu.vv v8, v8, v9
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vx_nxv1i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT:    vremu.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vx_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; CHECK-NEXT:    addi a0, sp, 8
+; CHECK-NEXT:    vlse64.v v9, (a0), zero
+; CHECK-NEXT:    vremu.vv v8, v8, v9
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i64> %va, %splat
@@ -854,37 +727,31 @@
 }
 
 define <vscale x 1 x i64> @vremu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
-; RV32-LABEL: vremu_vi_nxv1i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    li a0, 1
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vmulhu.vv v9, v8, v9
-; RV32-NEXT:    li a0, 61
-; RV32-NEXT:    vsrl.vx v9, v9, a0
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vremu_vi_nxv1i64_0:
+; V:       # %bb.0:
+; V-NEXT:    addi sp, sp, -16
+; V-NEXT:    .cfi_def_cfa_offset 16
+; V-NEXT:    lui a0, 131072
+; V-NEXT:    sw a0, 12(sp)
+; V-NEXT:    li a0, 1
+; V-NEXT:    sw a0, 8(sp)
+; V-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
+; V-NEXT:    addi a0, sp, 8
+; V-NEXT:    vlse64.v v9, (a0), zero
+; V-NEXT:    vmulhu.vv v9, v8, v9
+; V-NEXT:    li a0, 61
+; V-NEXT:    vsrl.vx v9, v9, a0
+; V-NEXT:    li a0, -7
+; V-NEXT:    vnmsac.vx v8, a0, v9
+; V-NEXT:    addi sp, sp, 16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vremu_vi_nxv1i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a0, 1
-; RV64-NEXT:    slli a0, a0, 61
-; RV64-NEXT:    addi a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT:    vmulhu.vx v9, v8, a0
-; RV64-NEXT:    li a0, 61
-; RV64-NEXT:    vsrl.vx v9, v9, a0
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vremu_vi_nxv1i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; ZVE64-NEXT:    vremu.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i64> %va, %splat
@@ -933,24 +800,18 @@
 }
 
 define <vscale x 2 x i64> @vremu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
-; RV32-LABEL: vremu_vx_nxv2i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v10, (a0), zero
-; RV32-NEXT:    vremu.vv v8, v8, v10
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vx_nxv2i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
-; RV64-NEXT:    vremu.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vx_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
+; CHECK-NEXT:    addi a0, sp, 8
+; CHECK-NEXT:    vlse64.v v10, (a0), zero
+; CHECK-NEXT:    vremu.vv v8, v8, v10
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i64> %va, %splat
@@ -958,37 +819,31 @@
 }
 
 define <vscale x 2 x i64> @vremu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
-; RV32-LABEL: vremu_vi_nxv2i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    li a0, 1
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v10, (a0), zero
-; RV32-NEXT:    vmulhu.vv v10, v8, v10
-; RV32-NEXT:    li a0, 61
-; RV32-NEXT:    vsrl.vx v10, v10, a0
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v10
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vremu_vi_nxv2i64_0:
+; V:       # %bb.0:
+; V-NEXT:    addi sp, sp, -16
+; V-NEXT:    .cfi_def_cfa_offset 16
+; V-NEXT:    lui a0, 131072
+; V-NEXT:    sw a0, 12(sp)
+; V-NEXT:    li a0, 1
+; V-NEXT:    sw a0, 8(sp)
+; V-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
+; V-NEXT:    addi a0, sp, 8
+; V-NEXT:    vlse64.v v10, (a0), zero
+; V-NEXT:    vmulhu.vv v10, v8, v10
+; V-NEXT:    li a0, 61
+; V-NEXT:    vsrl.vx v10, v10, a0
+; V-NEXT:    li a0, -7
+; V-NEXT:    vnmsac.vx v8, a0, v10
+; V-NEXT:    addi sp, sp, 16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vremu_vi_nxv2i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a0, 1
-; RV64-NEXT:    slli a0, a0, 61
-; RV64-NEXT:    addi a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
-; RV64-NEXT:    vmulhu.vx v10, v8, a0
-; RV64-NEXT:    li a0, 61
-; RV64-NEXT:    vsrl.vx v10, v10, a0
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v10
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vremu_vi_nxv2i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; ZVE64-NEXT:    vremu.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i64> %va, %splat
@@ -1037,24 +892,18 @@
 }
 
 define <vscale x 4 x i64> @vremu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
-; RV32-LABEL: vremu_vx_nxv4i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v12, (a0), zero
-; RV32-NEXT:    vremu.vv v8, v8, v12
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vx_nxv4i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
-; RV64-NEXT:    vremu.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vx_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
+; CHECK-NEXT:    addi a0, sp, 8
+; CHECK-NEXT:    vlse64.v v12, (a0), zero
+; CHECK-NEXT:    vremu.vv v8, v8, v12
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i64> %va, %splat
@@ -1062,37 +911,31 @@
 }
 
 define <vscale x 4 x i64> @vremu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
-; RV32-LABEL: vremu_vi_nxv4i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    li a0, 1
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v12, (a0), zero
-; RV32-NEXT:    vmulhu.vv v12, v8, v12
-; RV32-NEXT:    li a0, 61
-; RV32-NEXT:    vsrl.vx v12, v12, a0
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v12
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vremu_vi_nxv4i64_0:
+; V:       # %bb.0:
+; V-NEXT:    addi sp, sp, -16
+; V-NEXT:    .cfi_def_cfa_offset 16
+; V-NEXT:    lui a0, 131072
+; V-NEXT:    sw a0, 12(sp)
+; V-NEXT:    li a0, 1
+; V-NEXT:    sw a0, 8(sp)
+; V-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
+; V-NEXT:    addi a0, sp, 8
+; V-NEXT:    vlse64.v v12, (a0), zero
+; V-NEXT:    vmulhu.vv v12, v8, v12
+; V-NEXT:    li a0, 61
+; V-NEXT:    vsrl.vx v12, v12, a0
+; V-NEXT:    li a0, -7
+; V-NEXT:    vnmsac.vx v8, a0, v12
+; V-NEXT:    addi sp, sp, 16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vremu_vi_nxv4i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a0, 1
-; RV64-NEXT:    slli a0, a0, 61
-; RV64-NEXT:    addi a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
-; RV64-NEXT:    vmulhu.vx v12, v8, a0
-; RV64-NEXT:    li a0, 61
-; RV64-NEXT:    vsrl.vx v12, v12, a0
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v12
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vremu_vi_nxv4i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; ZVE64-NEXT:    vremu.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i64> %va, %splat
@@ -1141,24 +984,18 @@
 }
 
 define <vscale x 8 x i64> @vremu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; RV32-LABEL: vremu_vx_nxv8i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vremu.vv v8, v8, v16
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vx_nxv8i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vremu.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    addi sp, sp, -16
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    sw a1, 12(sp)
+; CHECK-NEXT:    sw a0, 8(sp)
+; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; CHECK-NEXT:    addi a0, sp, 8
+; CHECK-NEXT:    vlse64.v v16, (a0), zero
+; CHECK-NEXT:    vremu.vv v8, v8, v16
+; CHECK-NEXT:    addi sp, sp, 16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i64> %va, %splat
@@ -1166,37 +1003,31 @@
 }
 
 define <vscale x 8 x i64> @vremu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
-; RV32-LABEL: vremu_vi_nxv8i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    li a0, 1
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vmulhu.vv v16, v8, v16
-; RV32-NEXT:    li a0, 61
-; RV32-NEXT:    vsrl.vx v16, v16, a0
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v16
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vremu_vi_nxv8i64_0:
+; V:       # %bb.0:
+; V-NEXT:    addi sp, sp, -16
+; V-NEXT:    .cfi_def_cfa_offset 16
+; V-NEXT:    lui a0, 131072
+; V-NEXT:    sw a0, 12(sp)
+; V-NEXT:    li a0, 1
+; V-NEXT:    sw a0, 8(sp)
+; V-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
+; V-NEXT:    addi a0, sp, 8
+; V-NEXT:    vlse64.v v16, (a0), zero
+; V-NEXT:    vmulhu.vv v16, v8, v16
+; V-NEXT:    li a0, 61
+; V-NEXT:    vsrl.vx v16, v16, a0
+; V-NEXT:    li a0, -7
+; V-NEXT:    vnmsac.vx v8, a0, v16
+; V-NEXT:    addi sp, sp, 16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vremu_vi_nxv8i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a0, 1
-; RV64-NEXT:    slli a0, a0, 61
-; RV64-NEXT:    addi a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vmulhu.vx v16, v8, a0
-; RV64-NEXT:    li a0, 61
-; RV64-NEXT:    vsrl.vx v16, v16, a0
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v16
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vremu_vi_nxv8i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; ZVE64-NEXT:    vremu.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i64> %va, %splat
diff --git a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll
rename from llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
rename to llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll
--- a/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll
@@ -1,6 +1,6 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --force-update
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,V
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-zve64x -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVE64
 
 define <vscale x 1 x i8> @vremu_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
 ; CHECK-LABEL: vremu_vv_nxv1i8:
@@ -291,27 +291,16 @@
 }
 
 define <vscale x 1 x i16> @vremu_vi_nxv1i16_0(<vscale x 1 x i16> %va) {
-; RV32-LABEL: vremu_vi_nxv1i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV32-NEXT:    vmulhu.vx v9, v8, a0
-; RV32-NEXT:    vsrl.vi v9, v9, 13
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv1i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
-; RV64-NEXT:    vmulhu.vx v9, v8, a0
-; RV64-NEXT:    vsrl.vi v9, v9, 13
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv1i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf4, ta, mu
+; CHECK-NEXT:    vmulhu.vx v9, v8, a0
+; CHECK-NEXT:    vsrl.vi v9, v9, 13
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i16> %va, %splat
@@ -341,27 +330,16 @@
 }
 
 define <vscale x 2 x i16> @vremu_vi_nxv2i16_0(<vscale x 2 x i16> %va) {
-; RV32-LABEL: vremu_vi_nxv2i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
-; RV32-NEXT:    vmulhu.vx v9, v8, a0
-; RV32-NEXT:    vsrl.vi v9, v9, 13
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv2i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
-; RV64-NEXT:    vmulhu.vx v9, v8, a0
-; RV64-NEXT:    vsrl.vi v9, v9, 13
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv2i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, mf2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v9, v8, a0
+; CHECK-NEXT:    vsrl.vi v9, v9, 13
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i16> %va, %splat
@@ -391,27 +369,16 @@
 }
 
 define <vscale x 4 x i16> @vremu_vi_nxv4i16_0(<vscale x 4 x i16> %va) {
-; RV32-LABEL: vremu_vi_nxv4i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
-; RV32-NEXT:    vmulhu.vx v9, v8, a0
-; RV32-NEXT:    vsrl.vi v9, v9, 13
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv4i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
-; RV64-NEXT:    vmulhu.vx v9, v8, a0
-; RV64-NEXT:    vsrl.vi v9, v9, 13
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv4i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, m1, ta, mu
+; CHECK-NEXT:    vmulhu.vx v9, v8, a0
+; CHECK-NEXT:    vsrl.vi v9, v9, 13
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i16> %va, %splat
@@ -441,27 +408,16 @@
 }
 
 define <vscale x 8 x i16> @vremu_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
-; RV32-LABEL: vremu_vi_nxv8i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; RV32-NEXT:    vmulhu.vx v10, v8, a0
-; RV32-NEXT:    vsrl.vi v10, v10, 13
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v10
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv8i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
-; RV64-NEXT:    vmulhu.vx v10, v8, a0
-; RV64-NEXT:    vsrl.vi v10, v10, 13
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v10
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv8i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v10, v8, a0
+; CHECK-NEXT:    vsrl.vi v10, v10, 13
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v10
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i16> %va, %splat
@@ -491,27 +447,16 @@
 }
 
 define <vscale x 16 x i16> @vremu_vi_nxv16i16_0(<vscale x 16 x i16> %va) {
-; RV32-LABEL: vremu_vi_nxv16i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
-; RV32-NEXT:    vmulhu.vx v12, v8, a0
-; RV32-NEXT:    vsrl.vi v12, v12, 13
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v12
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv16i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
-; RV64-NEXT:    vmulhu.vx v12, v8, a0
-; RV64-NEXT:    vsrl.vi v12, v12, 13
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v12
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv16i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vx v12, v8, a0
+; CHECK-NEXT:    vsrl.vi v12, v12, 13
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v12
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 16 x i16> %head, <vscale x 16 x i16> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i16> %va, %splat
@@ -541,27 +486,16 @@
 }
 
 define <vscale x 32 x i16> @vremu_vi_nxv32i16_0(<vscale x 32 x i16> %va) {
-; RV32-LABEL: vremu_vi_nxv32i16_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 2
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
-; RV32-NEXT:    vmulhu.vx v16, v8, a0
-; RV32-NEXT:    vsrl.vi v16, v16, 13
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv32i16_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 2
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
-; RV64-NEXT:    vmulhu.vx v16, v8, a0
-; RV64-NEXT:    vsrl.vi v16, v16, 13
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v16
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv32i16_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 2
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e16, m8, ta, mu
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 13
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 32 x i16> undef, i16 -7, i32 0
   %splat = shufflevector <vscale x 32 x i16> %head, <vscale x 32 x i16> undef, <vscale x 32 x i32> zeroinitializer
   %vc = urem <vscale x 32 x i16> %va, %splat
@@ -591,27 +525,16 @@
 }
 
 define <vscale x 1 x i32> @vremu_vi_nxv1i32_0(<vscale x 1 x i32> %va) {
-; RV32-LABEL: vremu_vi_nxv1i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; RV32-NEXT:    vmulhu.vx v9, v8, a0
-; RV32-NEXT:    vsrl.vi v9, v9, 29
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv1i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
-; RV64-NEXT:    vmulhu.vx v9, v8, a0
-; RV64-NEXT:    vsrl.vi v9, v9, 29
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv1i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v9, v8, a0
+; CHECK-NEXT:    vsrl.vi v9, v9, 29
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i32> %va, %splat
@@ -641,27 +564,16 @@
 }
 
 define <vscale x 2 x i32> @vremu_vi_nxv2i32_0(<vscale x 2 x i32> %va) {
-; RV32-LABEL: vremu_vi_nxv2i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; RV32-NEXT:    vmulhu.vx v9, v8, a0
-; RV32-NEXT:    vsrl.vi v9, v9, 29
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv2i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
-; RV64-NEXT:    vmulhu.vx v9, v8, a0
-; RV64-NEXT:    vsrl.vi v9, v9, 29
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv2i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vmulhu.vx v9, v8, a0
+; CHECK-NEXT:    vsrl.vi v9, v9, 29
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v9
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i32> %va, %splat
@@ -691,27 +603,16 @@
 }
 
 define <vscale x 4 x i32> @vremu_vi_nxv4i32_0(<vscale x 4 x i32> %va) {
-; RV32-LABEL: vremu_vi_nxv4i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; RV32-NEXT:    vmulhu.vx v10, v8, a0
-; RV32-NEXT:    vsrl.vi v10, v10, 29
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v10
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv4i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
-; RV64-NEXT:    vmulhu.vx v10, v8, a0
-; RV64-NEXT:    vsrl.vi v10, v10, 29
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v10
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv4i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, mu
+; CHECK-NEXT:    vmulhu.vx v10, v8, a0
+; CHECK-NEXT:    vsrl.vi v10, v10, 29
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v10
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i32> %va, %splat
@@ -741,27 +642,16 @@
 }
 
 define <vscale x 8 x i32> @vremu_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
-; RV32-LABEL: vremu_vi_nxv8i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; RV32-NEXT:    vmulhu.vx v12, v8, a0
-; RV32-NEXT:    vsrl.vi v12, v12, 29
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v12
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv8i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
-; RV64-NEXT:    vmulhu.vx v12, v8, a0
-; RV64-NEXT:    vsrl.vi v12, v12, 29
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v12
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv8i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
+; CHECK-NEXT:    vmulhu.vx v12, v8, a0
+; CHECK-NEXT:    vsrl.vi v12, v12, 29
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v12
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i32> %va, %splat
@@ -791,27 +681,16 @@
 }
 
 define <vscale x 16 x i32> @vremu_vi_nxv16i32_0(<vscale x 16 x i32> %va) {
-; RV32-LABEL: vremu_vi_nxv16i32_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    addi a0, a0, 1
-; RV32-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
-; RV32-NEXT:    vmulhu.vx v16, v8, a0
-; RV32-NEXT:    vsrl.vi v16, v16, 29
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vi_nxv16i32_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    lui a0, 131072
-; RV64-NEXT:    addiw a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
-; RV64-NEXT:    vmulhu.vx v16, v8, a0
-; RV64-NEXT:    vsrl.vi v16, v16, 29
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v16
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vi_nxv16i32_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    lui a0, 131072
+; CHECK-NEXT:    addiw a0, a0, 1
+; CHECK-NEXT:    vsetvli a1, zero, e32, m8, ta, mu
+; CHECK-NEXT:    vmulhu.vx v16, v8, a0
+; CHECK-NEXT:    vsrl.vi v16, v16, 29
+; CHECK-NEXT:    li a0, -7
+; CHECK-NEXT:    vnmsac.vx v8, a0, v16
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 16 x i32> undef, i32 -7, i32 0
   %splat = shufflevector <vscale x 16 x i32> %head, <vscale x 16 x i32> undef, <vscale x 16 x i32> zeroinitializer
   %vc = urem <vscale x 16 x i32> %va, %splat
@@ -829,24 +708,11 @@
 }
 
 define <vscale x 1 x i64> @vremu_vx_nxv1i64(<vscale x 1 x i64> %va, i64 %b) {
-; RV32-LABEL: vremu_vx_nxv1i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vremu.vv v8, v8, v9
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vx_nxv1i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT:    vremu.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vx_nxv1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i64> %va, %splat
@@ -854,37 +720,25 @@
 }
 
 define <vscale x 1 x i64> @vremu_vi_nxv1i64_0(<vscale x 1 x i64> %va) {
-; RV32-LABEL: vremu_vi_nxv1i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    li a0, 1
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m1, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v9, (a0), zero
-; RV32-NEXT:    vmulhu.vv v9, v8, v9
-; RV32-NEXT:    li a0, 61
-; RV32-NEXT:    vsrl.vx v9, v9, a0
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v9
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vremu_vi_nxv1i64_0:
+; V:       # %bb.0:
+; V-NEXT:    li a0, 1
+; V-NEXT:    slli a0, a0, 61
+; V-NEXT:    addi a0, a0, 1
+; V-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; V-NEXT:    vmulhu.vx v9, v8, a0
+; V-NEXT:    li a0, 61
+; V-NEXT:    vsrl.vx v9, v9, a0
+; V-NEXT:    li a0, -7
+; V-NEXT:    vnmsac.vx v8, a0, v9
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vremu_vi_nxv1i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a0, 1
-; RV64-NEXT:    slli a0, a0, 61
-; RV64-NEXT:    addi a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
-; RV64-NEXT:    vmulhu.vx v9, v8, a0
-; RV64-NEXT:    li a0, 61
-; RV64-NEXT:    vsrl.vx v9, v9, a0
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v9
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vremu_vi_nxv1i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m1, ta, mu
+; ZVE64-NEXT:    vremu.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 1 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> undef, <vscale x 1 x i32> zeroinitializer
   %vc = urem <vscale x 1 x i64> %va, %splat
@@ -933,24 +787,11 @@
 }
 
 define <vscale x 2 x i64> @vremu_vx_nxv2i64(<vscale x 2 x i64> %va, i64 %b) {
-; RV32-LABEL: vremu_vx_nxv2i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v10, (a0), zero
-; RV32-NEXT:    vremu.vv v8, v8, v10
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vx_nxv2i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
-; RV64-NEXT:    vremu.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vx_nxv2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i64> %va, %splat
@@ -958,37 +799,25 @@
 }
 
 define <vscale x 2 x i64> @vremu_vi_nxv2i64_0(<vscale x 2 x i64> %va) {
-; RV32-LABEL: vremu_vi_nxv2i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    li a0, 1
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m2, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v10, (a0), zero
-; RV32-NEXT:    vmulhu.vv v10, v8, v10
-; RV32-NEXT:    li a0, 61
-; RV32-NEXT:    vsrl.vx v10, v10, a0
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v10
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vremu_vi_nxv2i64_0:
+; V:       # %bb.0:
+; V-NEXT:    li a0, 1
+; V-NEXT:    slli a0, a0, 61
+; V-NEXT:    addi a0, a0, 1
+; V-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; V-NEXT:    vmulhu.vx v10, v8, a0
+; V-NEXT:    li a0, 61
+; V-NEXT:    vsrl.vx v10, v10, a0
+; V-NEXT:    li a0, -7
+; V-NEXT:    vnmsac.vx v8, a0, v10
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vremu_vi_nxv2i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a0, 1
-; RV64-NEXT:    slli a0, a0, 61
-; RV64-NEXT:    addi a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
-; RV64-NEXT:    vmulhu.vx v10, v8, a0
-; RV64-NEXT:    li a0, 61
-; RV64-NEXT:    vsrl.vx v10, v10, a0
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v10
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vremu_vi_nxv2i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m2, ta, mu
+; ZVE64-NEXT:    vremu.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 2 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer
   %vc = urem <vscale x 2 x i64> %va, %splat
@@ -1037,24 +866,11 @@
 }
 
 define <vscale x 4 x i64> @vremu_vx_nxv4i64(<vscale x 4 x i64> %va, i64 %b) {
-; RV32-LABEL: vremu_vx_nxv4i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v12, (a0), zero
-; RV32-NEXT:    vremu.vv v8, v8, v12
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vx_nxv4i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
-; RV64-NEXT:    vremu.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vx_nxv4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i64> %va, %splat
@@ -1062,37 +878,25 @@
 }
 
 define <vscale x 4 x i64> @vremu_vi_nxv4i64_0(<vscale x 4 x i64> %va) {
-; RV32-LABEL: vremu_vi_nxv4i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    li a0, 1
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m4, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v12, (a0), zero
-; RV32-NEXT:    vmulhu.vv v12, v8, v12
-; RV32-NEXT:    li a0, 61
-; RV32-NEXT:    vsrl.vx v12, v12, a0
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v12
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vremu_vi_nxv4i64_0:
+; V:       # %bb.0:
+; V-NEXT:    li a0, 1
+; V-NEXT:    slli a0, a0, 61
+; V-NEXT:    addi a0, a0, 1
+; V-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; V-NEXT:    vmulhu.vx v12, v8, a0
+; V-NEXT:    li a0, 61
+; V-NEXT:    vsrl.vx v12, v12, a0
+; V-NEXT:    li a0, -7
+; V-NEXT:    vnmsac.vx v8, a0, v12
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vremu_vi_nxv4i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a0, 1
-; RV64-NEXT:    slli a0, a0, 61
-; RV64-NEXT:    addi a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
-; RV64-NEXT:    vmulhu.vx v12, v8, a0
-; RV64-NEXT:    li a0, 61
-; RV64-NEXT:    vsrl.vx v12, v12, a0
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v12
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vremu_vi_nxv4i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m4, ta, mu
+; ZVE64-NEXT:    vremu.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 4 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> undef, <vscale x 4 x i32> zeroinitializer
   %vc = urem <vscale x 4 x i64> %va, %splat
@@ -1141,24 +945,11 @@
 }
 
 define <vscale x 8 x i64> @vremu_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
-; RV32-LABEL: vremu_vx_nxv8i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    sw a1, 12(sp)
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vremu.vv v8, v8, v16
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: vremu_vx_nxv8i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vremu.vx v8, v8, a0
-; RV64-NEXT:    ret
+; CHECK-LABEL: vremu_vx_nxv8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; CHECK-NEXT:    vremu.vx v8, v8, a0
+; CHECK-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 %b, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i64> %va, %splat
@@ -1166,37 +957,25 @@
 }
 
 define <vscale x 8 x i64> @vremu_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
-; RV32-LABEL: vremu_vi_nxv8i64_0:
-; RV32:       # %bb.0:
-; RV32-NEXT:    addi sp, sp, -16
-; RV32-NEXT:    .cfi_def_cfa_offset 16
-; RV32-NEXT:    lui a0, 131072
-; RV32-NEXT:    sw a0, 12(sp)
-; RV32-NEXT:    li a0, 1
-; RV32-NEXT:    sw a0, 8(sp)
-; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
-; RV32-NEXT:    addi a0, sp, 8
-; RV32-NEXT:    vlse64.v v16, (a0), zero
-; RV32-NEXT:    vmulhu.vv v16, v8, v16
-; RV32-NEXT:    li a0, 61
-; RV32-NEXT:    vsrl.vx v16, v16, a0
-; RV32-NEXT:    li a0, -7
-; RV32-NEXT:    vnmsac.vx v8, a0, v16
-; RV32-NEXT:    addi sp, sp, 16
-; RV32-NEXT:    ret
+; V-LABEL: vremu_vi_nxv8i64_0:
+; V:       # %bb.0:
+; V-NEXT:    li a0, 1
+; V-NEXT:    slli a0, a0, 61
+; V-NEXT:    addi a0, a0, 1
+; V-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; V-NEXT:    vmulhu.vx v16, v8, a0
+; V-NEXT:    li a0, 61
+; V-NEXT:    vsrl.vx v16, v16, a0
+; V-NEXT:    li a0, -7
+; V-NEXT:    vnmsac.vx v8, a0, v16
+; V-NEXT:    ret
 ;
-; RV64-LABEL: vremu_vi_nxv8i64_0:
-; RV64:       # %bb.0:
-; RV64-NEXT:    li a0, 1
-; RV64-NEXT:    slli a0, a0, 61
-; RV64-NEXT:    addi a0, a0, 1
-; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
-; RV64-NEXT:    vmulhu.vx v16, v8, a0
-; RV64-NEXT:    li a0, 61
-; RV64-NEXT:    vsrl.vx v16, v16, a0
-; RV64-NEXT:    li a0, -7
-; RV64-NEXT:    vnmsac.vx v8, a0, v16
-; RV64-NEXT:    ret
+; ZVE64-LABEL: vremu_vi_nxv8i64_0:
+; ZVE64:       # %bb.0:
+; ZVE64-NEXT:    li a0, -7
+; ZVE64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
+; ZVE64-NEXT:    vremu.vx v8, v8, a0
+; ZVE64-NEXT:    ret
   %head = insertelement <vscale x 8 x i64> undef, i64 -7, i32 0
   %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer
   %vc = urem <vscale x 8 x i64> %va, %splat