diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -231,6 +231,11 @@ "'V' (Vector Extension for Application Processors), 'Zve32f', " "'Zve64f' or 'Zve64d' (Vector Extensions for Embedded Processors)">; +def HasVInstructionMULHSMUL : Predicate<"Subtarget->hasVInstructionMULHSMUL()">, + AssemblerPredicate< + (any_of FeatureStdExtV), + "'V' (Vector Extension for Application Processors)">; + def Feature64Bit : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; def IsRV64 : Predicate<"Subtarget->is64Bit()">, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -1045,9 +1045,6 @@ // Vector Single-Width Integer Multiply Instructions defm VMUL_V : VMUL_MV_V_X<"vmul", 0b100101>; -defm VMULH_V : VMUL_MV_V_X<"vmulh", 0b100111>; -defm VMULHU_V : VMUL_MV_V_X<"vmulhu", 0b100100>; -defm VMULHSU_V : VMUL_MV_V_X<"vmulhsu", 0b100110>; // Vector Integer Divide Instructions defm VDIVU_V : VDIV_MV_V_X<"vdivu", 0b100000>; @@ -1108,9 +1105,6 @@ defm VASUBU_V : VAALU_MV_V_X<"vasubu", 0b001010>; defm VASUB_V : VAALU_MV_V_X<"vasub", 0b001011>; -// Vector Single-Width Fractional Multiply with Rounding and Saturation -defm VSMUL_V : VSMUL_IV_V_X<"vsmul", 0b100111>; - // Vector Single-Width Scaling Shift Instructions defm VSSRL_V : VSSHF_IV_V_X_I<"vssrl", 0b101010, uimm5>; defm VSSRA_V : VSSHF_IV_V_X_I<"vssra", 0b101011, uimm5>; @@ -1531,4 +1525,19 @@ } } // Predicates = [HasVInstructionsI64, IsRV64] +let Predicates = [HasVInstructionMULHSMUL] in { + // NOTE: According to v-spec 1.0: + // All Zve* extensions support all vector fixed-point arithmetic + // instructions (Vector Fixed-Point Arithmetic Instructions), except that + // vsmul.vv and vsmul.vx are not supported for EEW=64 in Zve64*. + + // Vector Single-Width Integer Multiply Instructions + defm VMULH_V : VMUL_MV_V_X<"vmulh", 0b100111>; + defm VMULHU_V : VMUL_MV_V_X<"vmulhu", 0b100100>; + defm VMULHSU_V : VMUL_MV_V_X<"vmulhsu", 0b100110>; + + // Vector Single-Width Fractional Multiply with Rounding and Saturation + defm VSMUL_V : VSMUL_IV_V_X<"vsmul", 0b100111>; +} // Predicates = [HasVInstructionMULHSMUL] + include "RISCVInstrInfoVPseudos.td" diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -190,6 +190,7 @@ bool hasVInstructionsF64() const { return HasStdExtZve64d && HasStdExtD; } // F16 and F64 both require F32. bool hasVInstructionsAnyF() const { return hasVInstructionsF32(); } + bool hasVInstructionMULHSMUL() const { return HasStdExtV; } unsigned getMaxInterleaveFactor() const { return hasVInstructions() ? MaxInterleaveFactor : 1; } diff --git a/llvm/test/MC/RISCV/rvv/mul.s b/llvm/test/MC/RISCV/rvv/mul.s --- a/llvm/test/MC/RISCV/rvv/mul.s +++ b/llvm/test/MC/RISCV/rvv/mul.s @@ -32,78 +32,6 @@ # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) # CHECK-UNKNOWN: 57 64 45 96 -vmulh.vv v8, v4, v20, v0.t -# CHECK-INST: vmulh.vv v8, v4, v20, v0.t -# CHECK-ENCODING: [0x57,0x24,0x4a,0x9c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) -# CHECK-UNKNOWN: 57 24 4a 9c - -vmulh.vv v8, v4, v20 -# CHECK-INST: vmulh.vv v8, v4, v20 -# CHECK-ENCODING: [0x57,0x24,0x4a,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) -# CHECK-UNKNOWN: 57 24 4a 9e - -vmulh.vx v8, v4, a0, v0.t -# CHECK-INST: vmulh.vx v8, v4, a0, v0.t -# CHECK-ENCODING: [0x57,0x64,0x45,0x9c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) -# CHECK-UNKNOWN: 57 64 45 9c - -vmulh.vx v8, v4, a0 -# CHECK-INST: vmulh.vx v8, v4, a0 -# CHECK-ENCODING: [0x57,0x64,0x45,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) -# CHECK-UNKNOWN: 57 64 45 9e - -vmulhu.vv v8, v4, v20, v0.t -# CHECK-INST: vmulhu.vv v8, v4, v20, v0.t -# CHECK-ENCODING: [0x57,0x24,0x4a,0x90] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) -# CHECK-UNKNOWN: 57 24 4a 90 - -vmulhu.vv v8, v4, v20 -# CHECK-INST: vmulhu.vv v8, v4, v20 -# CHECK-ENCODING: [0x57,0x24,0x4a,0x92] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) -# CHECK-UNKNOWN: 57 24 4a 92 - -vmulhu.vx v8, v4, a0, v0.t -# CHECK-INST: vmulhu.vx v8, v4, a0, v0.t -# CHECK-ENCODING: [0x57,0x64,0x45,0x90] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) -# CHECK-UNKNOWN: 57 64 45 90 - -vmulhu.vx v8, v4, a0 -# CHECK-INST: vmulhu.vx v8, v4, a0 -# CHECK-ENCODING: [0x57,0x64,0x45,0x92] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) -# CHECK-UNKNOWN: 57 64 45 92 - -vmulhsu.vv v8, v4, v20, v0.t -# CHECK-INST: vmulhsu.vv v8, v4, v20, v0.t -# CHECK-ENCODING: [0x57,0x24,0x4a,0x98] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) -# CHECK-UNKNOWN: 57 24 4a 98 - -vmulhsu.vv v8, v4, v20 -# CHECK-INST: vmulhsu.vv v8, v4, v20 -# CHECK-ENCODING: [0x57,0x24,0x4a,0x9a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) -# CHECK-UNKNOWN: 57 24 4a 9a - -vmulhsu.vx v8, v4, a0, v0.t -# CHECK-INST: vmulhsu.vx v8, v4, a0, v0.t -# CHECK-ENCODING: [0x57,0x64,0x45,0x98] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) -# CHECK-UNKNOWN: 57 64 45 98 - -vmulhsu.vx v8, v4, a0 -# CHECK-INST: vmulhsu.vx v8, v4, a0 -# CHECK-ENCODING: [0x57,0x64,0x45,0x9a] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) -# CHECK-UNKNOWN: 57 64 45 9a - vwmul.vv v8, v4, v20, v0.t # CHECK-INST: vwmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xec] @@ -179,23 +107,95 @@ vsmul.vv v8, v4, v20, v0.t # CHECK-INST: vsmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x9c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) # CHECK-UNKNOWN: 57 04 4a 9c vsmul.vv v8, v4, v20 # CHECK-INST: vsmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) # CHECK-UNKNOWN: 57 04 4a 9e vsmul.vx v8, v4, a0, v0.t # CHECK-INST: vsmul.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x9c] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) # CHECK-UNKNOWN: 57 44 45 9c vsmul.vx v8, v4, a0 # CHECK-INST: vsmul.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x9e] -# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors) +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) # CHECK-UNKNOWN: 57 44 45 9e + +vmulh.vv v8, v4, v20, v0.t +# CHECK-INST: vmulh.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x9c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) +# CHECK-UNKNOWN: 57 24 4a 9c + +vmulh.vv v8, v4, v20 +# CHECK-INST: vmulh.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x9e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) +# CHECK-UNKNOWN: 57 24 4a 9e + +vmulh.vx v8, v4, a0, v0.t +# CHECK-INST: vmulh.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0x9c] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) +# CHECK-UNKNOWN: 57 64 45 9c + +vmulh.vx v8, v4, a0 +# CHECK-INST: vmulh.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0x9e] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) +# CHECK-UNKNOWN: 57 64 45 9e + +vmulhu.vv v8, v4, v20, v0.t +# CHECK-INST: vmulhu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x90] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) +# CHECK-UNKNOWN: 57 24 4a 90 + +vmulhu.vv v8, v4, v20 +# CHECK-INST: vmulhu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x92] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) +# CHECK-UNKNOWN: 57 24 4a 92 + +vmulhu.vx v8, v4, a0, v0.t +# CHECK-INST: vmulhu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0x90] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) +# CHECK-UNKNOWN: 57 64 45 90 + +vmulhu.vx v8, v4, a0 +# CHECK-INST: vmulhu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0x92] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) +# CHECK-UNKNOWN: 57 64 45 92 + +vmulhsu.vv v8, v4, v20, v0.t +# CHECK-INST: vmulhsu.vv v8, v4, v20, v0.t +# CHECK-ENCODING: [0x57,0x24,0x4a,0x98] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) +# CHECK-UNKNOWN: 57 24 4a 98 + +vmulhsu.vv v8, v4, v20 +# CHECK-INST: vmulhsu.vv v8, v4, v20 +# CHECK-ENCODING: [0x57,0x24,0x4a,0x9a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) +# CHECK-UNKNOWN: 57 24 4a 9a + +vmulhsu.vx v8, v4, a0, v0.t +# CHECK-INST: vmulhsu.vx v8, v4, a0, v0.t +# CHECK-ENCODING: [0x57,0x64,0x45,0x98] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) +# CHECK-UNKNOWN: 57 64 45 98 + +vmulhsu.vx v8, v4, a0 +# CHECK-INST: vmulhsu.vx v8, v4, a0 +# CHECK-ENCODING: [0x57,0x64,0x45,0x9a] +# CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) +# CHECK-UNKNOWN: 57 64 45 9a