diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -66,82 +66,82 @@ def FeatureStdExtZba : SubtargetFeature<"zba", "HasStdExtZba", "true", - "'Zba' (Address calculation 'B' Instructions)">; + "'Zba' (Address Generation Instructions)">; def HasStdExtZba : Predicate<"Subtarget->hasStdExtZba()">, AssemblerPredicate<(all_of FeatureStdExtZba), - "'Zba' (Address calculation 'B' Instructions)">; + "'Zba' (Address Generation Instructions)">; def NotHasStdExtZba : Predicate<"!Subtarget->hasStdExtZba()">; def FeatureStdExtZbb : SubtargetFeature<"zbb", "HasStdExtZbb", "true", - "'Zbb' (Base 'B' Instructions)">; + "'Zbb' (Basic Bit-Manipulation)">; def HasStdExtZbb : Predicate<"Subtarget->hasStdExtZbb()">, AssemblerPredicate<(all_of FeatureStdExtZbb), - "'Zbb' (Base 'B' Instructions)">; + "'Zbb' (Basic Bit-Manipulation)">; def FeatureStdExtZbc : SubtargetFeature<"zbc", "HasStdExtZbc", "true", - "'Zbc' (Carry-Less 'B' Instructions)">; + "'Zbc' (Carry-Less Multiplication)">; def HasStdExtZbc : Predicate<"Subtarget->hasStdExtZbc()">, AssemblerPredicate<(all_of FeatureStdExtZbc), - "'Zbc' (Carry-Less 'B' Instructions)">; + "'Zbc' (Carry-Less Multiplication)">; def FeatureStdExtZbe : SubtargetFeature<"experimental-zbe", "HasStdExtZbe", "true", - "'Zbe' (Extract-Deposit 'B' Instructions)">; + "'Zbe' (Extract-Deposit 'Zb' Instructions)">; def HasStdExtZbe : Predicate<"Subtarget->hasStdExtZbe()">, AssemblerPredicate<(all_of FeatureStdExtZbe), - "'Zbe' (Extract-Deposit 'B' Instructions)">; + "'Zbe' (Extract-Deposit 'Zb' Instructions)">; def FeatureStdExtZbf : SubtargetFeature<"experimental-zbf", "HasStdExtZbf", "true", - "'Zbf' (Bit-Field 'B' Instructions)">; + "'Zbf' (Bit-Field 'Zb' Instructions)">; def HasStdExtZbf : Predicate<"Subtarget->hasStdExtZbf()">, AssemblerPredicate<(all_of FeatureStdExtZbf), - "'Zbf' (Bit-Field 'B' Instructions)">; + "'Zbf' (Bit-Field 'Zb' Instructions)">; def FeatureStdExtZbm : SubtargetFeature<"experimental-zbm", "HasStdExtZbm", "true", - "'Zbm' (Matrix 'B' Instructions)">; + "'Zbm' (Matrix 'Zb' Instructions)">; def HasStdExtZbm : Predicate<"Subtarget->hasStdExtZbm()">, AssemblerPredicate<(all_of FeatureStdExtZbm), - "'Zbm' (Matrix 'B' Instructions)">; + "'Zbm' (Matrix 'Zb' Instructions)">; def FeatureStdExtZbp : SubtargetFeature<"experimental-zbp", "HasStdExtZbp", "true", - "'Zbp' (Permutation 'B' Instructions)">; + "'Zbp' (Permutation 'Zb' Instructions)">; def HasStdExtZbp : Predicate<"Subtarget->hasStdExtZbp()">, AssemblerPredicate<(all_of FeatureStdExtZbp), - "'Zbp' (Permutation 'B' Instructions)">; + "'Zbp' (Permutation 'Zb' Instructions)">; def FeatureStdExtZbr : SubtargetFeature<"experimental-zbr", "HasStdExtZbr", "true", - "'Zbr' (Polynomial Reduction 'B' Instructions)">; + "'Zbr' (Polynomial Reduction 'Zb' Instructions)">; def HasStdExtZbr : Predicate<"Subtarget->hasStdExtZbr()">, AssemblerPredicate<(all_of FeatureStdExtZbr), - "'Zbr' (Polynomial Reduction 'B' Instructions)">; + "'Zbr' (Polynomial Reduction 'Zb' Instructions)">; def FeatureStdExtZbs : SubtargetFeature<"zbs", "HasStdExtZbs", "true", - "'Zbs' (Single-Bit 'B' Instructions)">; + "'Zbs' (Single-Bit Instructions)">; def HasStdExtZbs : Predicate<"Subtarget->hasStdExtZbs()">, AssemblerPredicate<(all_of FeatureStdExtZbs), - "'Zbs' (Single-Bit 'B' Instructions)">; + "'Zbs' (Single-Bit Instructions)">; def FeatureStdExtZbt : SubtargetFeature<"experimental-zbt", "HasStdExtZbt", "true", - "'Zbt' (Ternary 'B' Instructions)">; + "'Zbt' (Ternary 'Zb' Instructions)">; def HasStdExtZbt : Predicate<"Subtarget->hasStdExtZbt()">, AssemblerPredicate<(all_of FeatureStdExtZbt), - "'Zbt' (Ternary 'B' Instructions)">; + "'Zbt' (Ternary 'Zb' Instructions)">; // Some instructions belong to both the basic and the permutation // subextensions. They should be enabled if either has been specified. def HasStdExtZbbOrZbp : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp()">, AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp), - "'Zbb' (Base 'B' Instructions) or " - "'Zbp' (Permutation 'B' Instructions)">; + "'Zbb' (Basic Bit-Manipulation) or " + "'Zbp' (Permutation 'Zb' Instructions)">; def FeatureStdExtZbkb : SubtargetFeature<"zbkb", "HasStdExtZbkb", "true", @@ -166,14 +166,14 @@ def HasStdExtZbpOrZbkb : Predicate<"Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">, AssemblerPredicate<(any_of FeatureStdExtZbp, FeatureStdExtZbkb), - "'Zbp' (Permutation 'B' Instructions) or " + "'Zbp' (Permutation 'Zb' Instructions) or " "'Zbkb' (Bitmanip instructions for Cryptography)">; def HasStdExtZbbOrZbpOrZbkb : Predicate<"Subtarget->hasStdExtZbb() || Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">, AssemblerPredicate<(any_of FeatureStdExtZbb, FeatureStdExtZbp, FeatureStdExtZbkb), - "'Zbb' (Base 'B' Instructions) or " - "'Zbp' (Permutation 'B' Instructions) or " + "'Zbb' (Basic Bit-Manipulation) or " + "'Zbp' (Permutation 'Zb' Instructions) or " "'Zbkb' (Bitmanip instructions for Cryptography)">; // The Carry-less multiply subextension for cryptography is a subset of basic carry-less multiply subextension. The former should be enabled if the latter is enabled. @@ -188,7 +188,7 @@ def HasStdExtZbcOrZbkc : Predicate<"Subtarget->hasStdExtZbc() || Subtarget->hasStdExtZbkc()">, AssemblerPredicate<(any_of FeatureStdExtZbc, FeatureStdExtZbkc), - "'Zbc' (Carry-Less 'B' Instructions) or " + "'Zbc' (Carry-Less Multiplication) or " "'Zbkc' (Carry-less multiply instructions for Cryptography)">; def FeatureStdExtZknd diff --git a/llvm/test/MC/RISCV/rv32i-invalid.s b/llvm/test/MC/RISCV/rv32i-invalid.s --- a/llvm/test/MC/RISCV/rv32i-invalid.s +++ b/llvm/test/MC/RISCV/rv32i-invalid.s @@ -173,6 +173,10 @@ amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'A' (Atomic Instructions) fadd.s ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'F' (Single-Precision Floating-Point) fadd.h ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) +sh1add a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zba' (Address Generation Instructions) +clz a0, a1 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbb' (Basic Bit-Manipulation) +clmul a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbc' (Carry-Less Multiplication) +bset a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbs' (Single-Bit Instructions) # Using floating point registers when integer registers are expected addi a2, ft0, 24 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv32zbkc-invalid.s b/llvm/test/MC/RISCV/rv32zbkc-invalid.s --- a/llvm/test/MC/RISCV/rv32zbkc-invalid.s +++ b/llvm/test/MC/RISCV/rv32zbkc-invalid.s @@ -6,4 +6,4 @@ clmulh t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Undefined zbc instruction in zbkc -clmulr t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbc' (Carry-Less 'B' Instructions) +clmulr t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbc' (Carry-Less Multiplication) diff --git a/llvm/test/MC/RISCV/rv32zbkx-invalid.s b/llvm/test/MC/RISCV/rv32zbkx-invalid.s --- a/llvm/test/MC/RISCV/rv32zbkx-invalid.s +++ b/llvm/test/MC/RISCV/rv32zbkx-invalid.s @@ -6,4 +6,4 @@ xperm4 t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction # Undefined Zbp instruction in Zbkx -xperm.h t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbp' (Permutation 'B' Instructions) \ No newline at end of file +xperm.h t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbp' (Permutation 'Zb' Instructions)