Index: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -497,6 +497,26 @@
   defm FMUL_ZZZ    : sve_fp_3op_u_zd<0b010, "fmul", fmul, AArch64fmul_p>;
 } // End HasSVEorStreamingSVE
 
+let Predicates = [HasSVE] in {
+  multiclass vselect_to_pred_inst<SDPatternOperator Op, string Inst, ValueType Ty, ValueType PredTy> {
+    def : Pat<(vselect (PredTy PPR:$Pg), (Ty ZPR:$Zn), (Ty (Op (PredTy (AArch64ptrue 31)), (Ty ZPR:$Zn), (Ty ZPR:$Zm)))),
+              (!cast<Instruction>(Inst) PPR:$Pg, ZPR:$Zn, ZPR:$Zm)>;
+}
+
+  defm : vselect_to_pred_inst<AArch64fmul_p, "FMUL_ZPmZ_H", nxv8f16, nxv8i1>;
+  defm : vselect_to_pred_inst<AArch64fmul_p, "FMUL_ZPmZ_S", nxv4f32, nxv4i1>;
+  defm : vselect_to_pred_inst<AArch64fmul_p, "FMUL_ZPmZ_D", nxv2f64, nxv2i1>;
+
+  defm : vselect_to_pred_inst<AArch64fadd_p, "FADD_ZPmZ_H", nxv8f16, nxv8i1>;
+  defm : vselect_to_pred_inst<AArch64fadd_p, "FADD_ZPmZ_S", nxv4f32, nxv4i1>;
+  defm : vselect_to_pred_inst<AArch64fadd_p, "FADD_ZPmZ_D", nxv2f64, nxv2i1>;
+
+  defm : vselect_to_pred_inst<AArch64fsub_p, "FSUB_ZPmZ_H", nxv8f16, nxv8i1>;
+  defm : vselect_to_pred_inst<AArch64fsub_p, "FSUB_ZPmZ_S", nxv4f32, nxv4i1>;
+  defm : vselect_to_pred_inst<AArch64fsub_p, "FSUB_ZPmZ_D", nxv2f64, nxv2i1>;
+
+} // End HasSVE
+
 let Predicates = [HasSVE] in {
   defm FTSMUL_ZZZ  : sve_fp_3op_u_zd_ftsmul<0b011, "ftsmul", int_aarch64_sve_ftsmul_x>;
 } // End HasSVE
Index: llvm/test/CodeGen/AArch64/sve-fp-reciprocal.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-fp-reciprocal.ll
+++ llvm/test/CodeGen/AArch64/sve-fp-reciprocal.ll
@@ -101,8 +101,7 @@
 ; CHECK-NEXT:    fmul z2.h, z1.h, z1.h
 ; CHECK-NEXT:    frsqrts z2.h, z0.h, z2.h
 ; CHECK-NEXT:    fmul z1.h, z1.h, z2.h
-; CHECK-NEXT:    fmul z1.h, z0.h, z1.h
-; CHECK-NEXT:    sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT:    fmul z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT:    ret
   %fsqrt = call fast <vscale x 8 x half> @llvm.sqrt.nxv8f16(<vscale x 8 x half> %a)
   ret <vscale x 8 x half> %fsqrt
@@ -130,8 +129,7 @@
 ; CHECK-NEXT:    fmul z2.s, z1.s, z1.s
 ; CHECK-NEXT:    frsqrts z2.s, z0.s, z2.s
 ; CHECK-NEXT:    fmul z1.s, z1.s, z2.s
-; CHECK-NEXT:    fmul z1.s, z0.s, z1.s
-; CHECK-NEXT:    sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT:    fmul z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    ret
   %fsqrt = call fast <vscale x 4 x float> @llvm.sqrt.nxv4f32(<vscale x 4 x float> %a)
   ret <vscale x 4 x float> %fsqrt
@@ -162,8 +160,7 @@
 ; CHECK-NEXT:    fmul z2.d, z1.d, z1.d
 ; CHECK-NEXT:    frsqrts z2.d, z0.d, z2.d
 ; CHECK-NEXT:    fmul z1.d, z1.d, z2.d
-; CHECK-NEXT:    fmul z1.d, z0.d, z1.d
-; CHECK-NEXT:    sel z0.d, p0, z0.d, z1.d
+; CHECK-NEXT:    fmul z0.d, p0/m, z0.d, z1.d
 ; CHECK-NEXT:    ret
   %fsqrt = call fast <vscale x 2 x double> @llvm.sqrt.nxv2f64(<vscale x 2 x double> %a)
   ret <vscale x 2 x double> %fsqrt
Index: llvm/test/CodeGen/AArch64/sve-fp-vselect.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-fp-vselect.ll
@@ -0,0 +1,92 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+define <vscale x 8 x half> @vselect_fmul_f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
+; CHECK-LABEL: vselect_fmul_f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmul z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    ret
+    %mul = fmul <vscale x 8 x half> %a, %b
+    %x = select <vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %mul
+    ret <vscale x 8 x half> %x
+}
+
+define <vscale x 4 x float> @vselect_fmul_f32(<vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
+; CHECK-LABEL: vselect_fmul_f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmul z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    ret
+    %mul = fmul <vscale x 4 x float> %a, %b
+    %x = select <vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %mul
+    ret <vscale x 4 x float> %x
+}
+
+define <vscale x 2 x double> @vselect_fmul_f64(<vscale x 2 x i1> %p, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
+; CHECK-LABEL: vselect_fmul_f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fmul z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT:    ret
+    %mul = fmul <vscale x 2 x double> %a, %b
+    %sel = select <vscale x 2 x i1> %p, <vscale x 2 x double> %a, <vscale x 2 x double> %mul
+    ret <vscale x 2 x double> %sel
+}
+
+define <vscale x 8 x half> @vselect_fadd_f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
+; CHECK-LABEL: vselect_fadd_f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fadd z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    ret
+    %mul = fadd <vscale x 8 x half> %a, %b
+    %x = select <vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %mul
+    ret <vscale x 8 x half> %x
+}
+
+define <vscale x 4 x float> @vselect_fadd_f32(<vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
+; CHECK-LABEL: vselect_fadd_f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fadd z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    ret
+    %mul = fadd <vscale x 4 x float> %a, %b
+    %x = select <vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %mul
+    ret <vscale x 4 x float> %x
+}
+
+define <vscale x 2 x double> @vselect_fadd_f64(<vscale x 2 x i1> %p, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
+; CHECK-LABEL: vselect_fadd_f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fadd z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT:    ret
+    %mul = fadd <vscale x 2 x double> %a, %b
+    %sel = select <vscale x 2 x i1> %p, <vscale x 2 x double> %a, <vscale x 2 x double> %mul
+    ret <vscale x 2 x double> %sel
+}
+
+define <vscale x 8 x half> @vselect_fsub_f16(<vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %b) {
+; CHECK-LABEL: vselect_fsub_f16:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fsub z0.h, p0/m, z0.h, z1.h
+; CHECK-NEXT:    ret
+    %mul = fsub <vscale x 8 x half> %a, %b
+    %x = select <vscale x 8 x i1> %p, <vscale x 8 x half> %a, <vscale x 8 x half> %mul
+    ret <vscale x 8 x half> %x
+}
+
+define <vscale x 4 x float> @vselect_fsub_f32(<vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %b) {
+; CHECK-LABEL: vselect_fsub_f32:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fsub z0.s, p0/m, z0.s, z1.s
+; CHECK-NEXT:    ret
+    %mul = fsub <vscale x 4 x float> %a, %b
+    %x = select <vscale x 4 x i1> %p, <vscale x 4 x float> %a, <vscale x 4 x float> %mul
+    ret <vscale x 4 x float> %x
+}
+
+define <vscale x 2 x double> @vselect_fsub_f64(<vscale x 2 x i1> %p, <vscale x 2 x double> %a, <vscale x 2 x double> %b) {
+; CHECK-LABEL: vselect_fsub_f64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fsub z0.d, p0/m, z0.d, z1.d
+; CHECK-NEXT:    ret
+    %mul = fsub <vscale x 2 x double> %a, %b
+    %sel = select <vscale x 2 x i1> %p, <vscale x 2 x double> %a, <vscale x 2 x double> %mul
+    ret <vscale x 2 x double> %sel
+}