diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h --- a/llvm/lib/Target/RISCV/RISCVISelLowering.h +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h @@ -26,7 +26,6 @@ enum NodeType : unsigned { FIRST_NUMBER = ISD::BUILTIN_OP_END, RET_FLAG, - URET_FLAG, SRET_FLAG, MRET_FLAG, CALL, diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -9077,7 +9077,7 @@ StringRef Kind = MF.getFunction().getFnAttribute("interrupt").getValueAsString(); - if (!(Kind == "user" || Kind == "supervisor" || Kind == "machine")) + if (!(Kind == "supervisor" || Kind == "machine")) report_fatal_error( "Function interrupt attribute argument not supported!"); } @@ -9694,9 +9694,7 @@ StringRef Kind = MF.getFunction().getFnAttribute("interrupt").getValueAsString(); - if (Kind == "user") - RetOpc = RISCVISD::URET_FLAG; - else if (Kind == "supervisor") + if (Kind == "supervisor") RetOpc = RISCVISD::SRET_FLAG; else RetOpc = RISCVISD::MRET_FLAG; @@ -9731,7 +9729,6 @@ case RISCVISD::FIRST_NUMBER: break; NODE_NAME_CASE(RET_FLAG) - NODE_NAME_CASE(URET_FLAG) NODE_NAME_CASE(SRET_FLAG) NODE_NAME_CASE(MRET_FLAG) NODE_NAME_CASE(CALL) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -57,8 +57,6 @@ SDNPVariadic]>; def riscv_ret_flag : SDNode<"RISCVISD::RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; -def riscv_uret_flag : SDNode<"RISCVISD::URET_FLAG", SDTNone, - [SDNPHasChain, SDNPOptInGlue]>; def riscv_sret_flag : SDNode<"RISCVISD::SRET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; def riscv_mret_flag : SDNode<"RISCVISD::MRET_FLAG", SDTNone, @@ -153,6 +151,11 @@ let OperandNamespace = "RISCVOp"; } +def immzero : Operand, + ImmLeaf { + let ParserMatchClass = ImmZeroAsmOperand; +} + def uimm2 : Operand { let ParserMatchClass = UImmAsmOperand<2>; let DecoderMethod = "decodeUImmOperand<2>"; @@ -437,20 +440,39 @@ let isTerminator = 1; } -let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in +let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in { class Load_ri funct3, string opcodestr> : RVInstI; +class HLoad_ri funct7, bits<3> funct3, string opcodestr> + : RVInstI<0b100, OPC_SYSTEM, (outs GPR:$rd), (ins GPR:$rs1, immzero:$imm2), + opcodestr, "$rd, ${imm2}(${rs1})"> { + bits<2> imm2; + let Inst{31-25} = funct7; + let Inst{24-23} = imm2; + let Inst{22-20} = funct3; +} +} + // Operands for stores are in the order srcreg, base, offset rather than // reflecting the order these fields are specified in the instruction // encoding. -let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in +let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in { class Store_rri funct3, string opcodestr> : RVInstS; +class HStore_ri funct7, string opcodestr> + : RVInstR, Sched<[]> { + bits<5> imm5; + let Inst{11-7} = imm5; +} +} + let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in class ALU_ri funct3, string opcodestr> : RVInstI, Sched<[]> { - let rd = 0; - let rs1 = 0; - let rs2 = 0b00010; -} - def SRET : Priv<"sret", 0b0001000>, Sched<[]> { let rd = 0; let rs1 = 0; @@ -684,11 +700,73 @@ let rs2 = 0b00101; } -let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in +let hasSideEffects = 1, mayLoad = 0, mayStore = 0 , rd = 0 in { def SFENCE_VMA : RVInstR<0b0001001, 0b000, OPC_SYSTEM, (outs), (ins GPR:$rs1, GPR:$rs2), - "sfence.vma", "$rs1, $rs2">, Sched<[]> { - let rd = 0; + "sfence.vma", "$rs1, $rs2">, Sched<[]>; +def SINVAL_VMA : RVInstR<0b0001011, 0b000, OPC_SYSTEM, (outs), + (ins GPR:$rs1, GPR:$rs2), + "sinval.vma", "$rs1, $rs2">, Sched<[]>; + +def SFENCE_W_INVAL : Priv<"sfence.w.inval", 0b0001100>, Sched<[]> { + let rs1 = 0; + let rs2 = 0; +} + +def SFENCE_INVAL_IR : Priv<"sfence.inval.ir", 0b0001100>, Sched<[]> { + let rs1 = 0; + let rs2 = 0b00001; +} + +def HFENCE_VVMA : RVInstR<0b0010001, 0b000, OPC_SYSTEM, (outs), + (ins GPR:$rs1, GPR:$rs2), + "hfence.vvma", "$rs1, $rs2">, Sched<[]>; + +def HFENCE_GVMA : RVInstR<0b0110001, 0b000, OPC_SYSTEM, (outs), + (ins GPR:$rs1, GPR:$rs2), + "hfence.gvma", "$rs1, $rs2">, Sched<[]>; + +def HINVAL_VVMA : RVInstR<0b0010011, 0b000, OPC_SYSTEM, (outs), + (ins GPR:$rs1, GPR:$rs2), + "hinval.vvma", "$rs1, $rs2">, Sched<[]>; + +def HINVAL_GVMA : RVInstR<0b0110011, 0b000, OPC_SYSTEM, (outs), + (ins GPR:$rs1, GPR:$rs2), + "hinval.gvma", "$rs1, $rs2">, Sched<[]>; +} + +def HLV_B : HLoad_ri<0b0110000, 0b000, "hlv.b">; +def HLV_BU : HLoad_ri<0b0110000, 0b001, "hlv.bu">; +def HLV_H : HLoad_ri<0b0110010, 0b000, "hlv.h">; +def HLV_HU : HLoad_ri<0b0110010, 0b001, "hlv.hu">; +def HLVX_HU : HLoad_ri<0b0110010, 0b011, "hlvx.hu">; +def HLV_W : HLoad_ri<0b0110100, 0b000, "hlv.w">; +def HLVX_WU : HLoad_ri<0b0110100, 0b011, "hlvx.wu">; +let Predicates = [IsRV64] in { +def HLV_WU : HLoad_ri<0b0110100, 0b001, "hlv.wu">; +def HLV_D : HLoad_ri<0b0110110, 0b000, "hlv.d">; +} + +def HSV_B : HStore_ri<0b0110001, "hsv.b">; +def HSV_H : HStore_ri<0b0110011, "hsv.h">; +def HSV_W : HStore_ri<0b0110101, "hsv.w">; +let Predicates = [IsRV64] in +def HSV_D : HStore_ri<0b0110111, "hsv.d">; + +let EmitPriority = 0 in { +def : InstAlias<"hlv.b $rd, (${rs1})", (HLV_B GPR:$rd, GPR:$rs1, 0)>; +def : InstAlias<"hlv.bu $rd, (${rs1})", (HLV_BU GPR:$rd, GPR:$rs1, 0)>; +def : InstAlias<"hlv.h $rd, (${rs1})", (HLV_H GPR:$rd, GPR:$rs1, 0)>; +def : InstAlias<"hlv.hu $rd, (${rs1})", (HLV_HU GPR:$rd, GPR:$rs1, 0)>; +def : InstAlias<"hlvx.hu $rd, (${rs1})", (HLVX_HU GPR:$rd, GPR:$rs1, 0)>; +def : InstAlias<"hlv.w $rd, (${rs1})", (HLV_W GPR:$rd, GPR:$rs1, 0)>; +def : InstAlias<"hlv.wu $rd, (${rs1})", (HLV_WU GPR:$rd, GPR:$rs1, 0)>; +def : InstAlias<"hlvx.wu $rd, (${rs1})", (HLVX_WU GPR:$rd, GPR:$rs1, 0)>; +def : InstAlias<"hlv.d $rd, (${rs1})", (HLV_D GPR:$rd, GPR:$rs1, 0)>; +def : InstAlias<"hsv.b $rs2, (${rs1})", (HSV_B GPR:$rs2, GPR:$rs1, 0)>; +def : InstAlias<"hsv.h $rs2, (${rs1})", (HSV_H GPR:$rs2, GPR:$rs1, 0)>; +def : InstAlias<"hsv.w $rs2, (${rs1})", (HSV_W GPR:$rs2, GPR:$rs1, 0)>; +def : InstAlias<"hsv.d $rs2, (${rs1})", (HSV_D GPR:$rs2, GPR:$rs1, 0)>; } //===----------------------------------------------------------------------===// @@ -831,6 +909,9 @@ def : InstAlias<"sfence.vma", (SFENCE_VMA X0, X0)>; def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>; +def : InstAlias<"hfence.gvma", (HFENCE_GVMA X0, X0)>; +def : InstAlias<"hfence.gvma $rs", (HFENCE_GVMA GPR:$rs, X0)>; + let EmitPriority = 0 in { def : InstAlias<"lb $rd, (${rs1})", (LB GPR:$rd, GPR:$rs1, 0)>; @@ -1203,7 +1284,6 @@ def : Pat<(riscv_call tglobaladdr:$func), (PseudoCALL tglobaladdr:$func)>; def : Pat<(riscv_call texternalsym:$func), (PseudoCALL texternalsym:$func)>; -def : Pat<(riscv_uret_flag), (URET X0, X0)>; def : Pat<(riscv_sret_flag), (SRET X0, X0)>; def : Pat<(riscv_mret_flag), (MRET X0, X0)>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td --- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td @@ -61,11 +61,6 @@ }]; } -def immzero : Operand, - ImmLeaf { - let ParserMatchClass = ImmZeroAsmOperand; -} - def CLUIImmAsmOperand : AsmOperandClass { let Name = "CLUIImm"; let RenderMethod = "addImmOperands"; diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -70,23 +70,6 @@ // 2.3, 2.4 and 2.5 in the RISC-V Instruction Set Manual // Volume II: Privileged Architecture. -//===----------------------------------------------------------------------===// -// User Trap Setup -//===----------------------------------------------------------------------===// -def : SysReg<"ustatus", 0x000>; -def : SysReg<"uie", 0x004>; -def : SysReg<"utvec", 0x005>; - -//===----------------------------------------------------------------------===// -// User Trap Handling -//===----------------------------------------------------------------------===// -def : SysReg<"uscratch", 0x040>; -def : SysReg<"uepc", 0x041>; -def : SysReg<"ucause", 0x042>; -let DeprecatedName = "ubadaddr" in -def : SysReg<"utval", 0x043>; -def : SysReg<"uip", 0x044>; - //===----------------------------------------------------------------------===// // User Floating-Point CSRs //===----------------------------------------------------------------------===// diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr-args-error.ll b/llvm/test/CodeGen/RISCV/interrupt-attr-args-error.ll --- a/llvm/test/CodeGen/RISCV/interrupt-attr-args-error.ll +++ b/llvm/test/CodeGen/RISCV/interrupt-attr-args-error.ll @@ -4,8 +4,8 @@ ; RUN: 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Functions with the interrupt attribute cannot have arguments! -define i32 @isr_user(i8 %n) #0 { +define i32 @isr_supervisor(i8 %n) #0 { ret i32 0 } -attributes #0 = { "interrupt"="user" } +attributes #0 = { "interrupt"="supervisor" } diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr-ret-error.ll b/llvm/test/CodeGen/RISCV/interrupt-attr-ret-error.ll --- a/llvm/test/CodeGen/RISCV/interrupt-attr-ret-error.ll +++ b/llvm/test/CodeGen/RISCV/interrupt-attr-ret-error.ll @@ -4,9 +4,9 @@ ; RUN: 2>&1 | FileCheck %s ; CHECK: LLVM ERROR: Functions with the interrupt attribute must have void return type! -define i32 @isr1_user() #0 { +define i32 @isr1_supervisor() #0 { ret i32 0 } -attributes #0 = { "interrupt"="user" } +attributes #0 = { "interrupt"="supervisor" } diff --git a/llvm/test/CodeGen/RISCV/interrupt-attr.ll b/llvm/test/CodeGen/RISCV/interrupt-attr.ll --- a/llvm/test/CodeGen/RISCV/interrupt-attr.ll +++ b/llvm/test/CodeGen/RISCV/interrupt-attr.ll @@ -16,21 +16,15 @@ ; ; Checking for special return instructions (uret, sret, mret). ; -define void @foo_user() #0 { -; CHECK-LABEL: foo_user: -; CHECK: # %bb.0: -; CHECK-NEXT: uret - ret void -} -define void @foo_supervisor() #1 { +define void @foo_supervisor() #0 { ; CHECK-LABEL: foo_supervisor: ; CHECK: # %bb.0: ; CHECK-NEXT: sret ret void } -define void @foo_machine() #2 { +define void @foo_machine() #1 { ; CHECK-LABEL: foo_machine: ; CHECK: # %bb.0: ; CHECK-NEXT: mret @@ -49,7 +43,7 @@ ; declare i32 @otherfoo(...) -define void @foo_with_call() #2 { +define void @foo_with_call() #1 { ; ; CHECK-RV32-LABEL: foo_with_call: ; CHECK-RV32: # %bb.0: @@ -547,7 +541,7 @@ ; ; Additionally check frame pointer and return address are properly saved. ; -define void @foo_fp_with_call() #3 { +define void @foo_fp_with_call() #2 { ; ; CHECK-RV32-LABEL: foo_fp_with_call: ; CHECK-RV32: # %bb.0: @@ -1060,7 +1054,6 @@ ret void } -attributes #0 = { nounwind "interrupt"="user" } -attributes #1 = { nounwind "interrupt"="supervisor" } -attributes #2 = { nounwind "interrupt"="machine" } -attributes #3 = { nounwind "interrupt"="machine" "frame-pointer"="all" } +attributes #0 = { nounwind "interrupt"="supervisor" } +attributes #1 = { nounwind "interrupt"="machine" } +attributes #2 = { nounwind "interrupt"="machine" "frame-pointer"="all" } diff --git a/llvm/test/CodeGen/RISCV/saverestore.ll b/llvm/test/CodeGen/RISCV/saverestore.ll --- a/llvm/test/CodeGen/RISCV/saverestore.ll +++ b/llvm/test/CodeGen/RISCV/saverestore.ll @@ -298,33 +298,3 @@ ret void } -; Check that functions with interrupt attribute do not use save/restore code - -declare i32 @foo(...) -define void @interrupt() nounwind "interrupt"="user" { -; RV32I-LABEL: interrupt: -; RV32I-NOT: call t0, __riscv_save -; RV32I-NOT: tail __riscv_restore -; -; RV64I-LABEL: interrupt: -; RV64I-NOT: call t0, __riscv_save -; RV64I-NOT: tail __riscv_restore -; -; RV32I-SR-LABEL: interrupt: -; RV32I-SR-NOT: call t0, __riscv_save -; RV32I-SR-NOT: tail __riscv_restore -; -; RV64I-SR-LABEL: interrupt: -; RV64I-SR-NOT: call t0, __riscv_save -; RV64I-SR-NOT: tail __riscv_restore -; -; RV32I-FP-SR-LABEL: interrupt: -; RV32I-FP-SR-NOT: call t0, __riscv_save -; RV32I-FP-SR-NOT: tail __riscv_restore -; -; RV64I-FP-SR-LABEL: interrupt: -; RV64I-FP-SR-NOT: call t0, __riscv_save -; RV64I-FP-SR-NOT: tail __riscv_restore - %call = call i32 bitcast (i32 (...)* @foo to i32 ()*)() - ret void -} diff --git a/llvm/test/MC/RISCV/deprecated-csr-names.s b/llvm/test/MC/RISCV/deprecated-csr-names.s --- a/llvm/test/MC/RISCV/deprecated-csr-names.s +++ b/llvm/test/MC/RISCV/deprecated-csr-names.s @@ -44,22 +44,6 @@ # CHECK-WARN: warning: 'mbadaddr' is a deprecated alias for 'mtval' -# ubadaddr -# name -# CHECK-INST: csrrw zero, utval, zero -# CHECK-ENC: encoding: [0x73,0x10,0x30,0x04] -# CHECK-INST-ALIAS: csrw utval, zero -# uimm12 -# CHECK-INST: csrrw zero, utval, zero -# CHECK-ENC: encoding: [0x73,0x10,0x30,0x04] -# CHECK-INST-ALIAS: csrw utval, zero -# name -csrw ubadaddr, zero -# uimm12 -csrrw zero, 0x043, zero - -# CHECK-WARN: warning: 'ubadaddr' is a deprecated alias for 'utval' - # sptbr # name # CHECK-INST: csrrw zero, satp, zero diff --git a/llvm/test/MC/RISCV/priv-aliases-valid.s b/llvm/test/MC/RISCV/priv-aliases-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/priv-aliases-valid.s @@ -0,0 +1,50 @@ +# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ +# RUN: | llvm-objdump -M no-aliases -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ +# RUN: | llvm-objdump -M no-aliases -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s + +# CHECK-INST: hlv.b a0, 0(a1) +# CHECK: encoding: [0x73,0xc5,0x05,0x60] +hlv.b a0, (a1) + +# CHECK-INST: hlv.bu a0, 0(a1) +# CHECK: encoding: [0x73,0xc5,0x15,0x60] +hlv.bu a0, (a1) + +# CHECK-INST: hlv.h a1, 0(a2) +# CHECK: encoding: [0xf3,0x45,0x06,0x64] +hlv.h a1, (a2) + +# CHECK-INST: hlv.hu a1, 0(a1) +# CHECK: encoding: [0xf3,0xc5,0x15,0x64] +hlv.hu a1, (a1) + +# CHECK-INST: hlvx.hu a1, 0(a2) +# CHECK: encoding: [0xf3,0x45,0x36,0x64] +hlvx.hu a1, (a2) + +# CHECK-INST: hlv.w a2, 0(a2) +# CHECK: encoding: [0x73,0x46,0x06,0x68] +hlv.w a2, (a2) + +# CHECK-INST: hlvx.wu a2, 0(a3) +# CHECK: encoding: [0x73,0xc6,0x36,0x68] +hlvx.wu a2, (a3) + +# CHECK-INST: hsv.b a0, 0(a1) +# CHECK: encoding: [0x73,0xc0,0xa5,0x62] +hsv.b a0, (a1) + +# CHECK-INST: hsv.h a0, 0(a1) +# CHECK: encoding: [0x73,0xc0,0xa5,0x66] +hsv.h a0, (a1) + +# CHECK-INST: hsv.w a0, 0(a1) +# CHECK: encoding: [0x73,0xc0,0xa5,0x6a] +hsv.w a0, (a1) diff --git a/llvm/test/MC/RISCV/priv-invalid.s b/llvm/test/MC/RISCV/priv-invalid.s --- a/llvm/test/MC/RISCV/priv-invalid.s +++ b/llvm/test/MC/RISCV/priv-invalid.s @@ -1,7 +1,79 @@ -# RUN: not llvm-mc -triple riscv32 < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple riscv64 < %s 2>&1 | FileCheck %s mret 0x10 # CHECK: :[[@LINE]]:6: error: invalid operand for instruction sfence.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction sfence.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction + +sinval.vma zero, a1, a2 # CHECK: :[[@LINE]]:22: error: invalid operand for instruction + +sinval.vma a0, 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction + +sfence.w.inval 0x10 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction + +sfence.inval.ir 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction + +hfence.vvma zero, a1, a2 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction + +hfence.vvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction + +hfence.gvma zero, a1, a2 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction + +hfence.gvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction + +hinval.vvma zero, a1, a2 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction + +hinval.vvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction + +hinval.gvma zero, a1, a2 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction + +hinval.gvma a0, 0x10 # CHECK: :[[@LINE]]:17: error: invalid operand for instruction + +hlv.b a0, 0x10 # CHECK: :[[@LINE]]:11: error: immediate must be zero + +hlv.b a0, 1(a1) # CHECK: :[[@LINE]]:11: error: immediate must be zero + +hlv.bu a0, 0x10 # CHECK: :[[@LINE]]:12: error: immediate must be zero + +hlv.bu a0, 1(a1) # CHECK: :[[@LINE]]:12: error: immediate must be zero + +hlv.h a0, 0x10 # CHECK: :[[@LINE]]:11: error: immediate must be zero + +hlv.h a0, 1(a1) # CHECK: :[[@LINE]]:11: error: immediate must be zero + +hlv.hu a0, 0x10 # CHECK: :[[@LINE]]:12: error: immediate must be zero + +hlv.hu a0, 1(a1) # CHECK: :[[@LINE]]:12: error: immediate must be zero + +hlvx.hu a0, 0x10 # CHECK: :[[@LINE]]:13: error: immediate must be zero + +hlvx.hu a0, 1(a1) # CHECK: :[[@LINE]]:13: error: immediate must be zero + +hlv.w a0, 0x10 # CHECK: :[[@LINE]]:11: error: immediate must be zero + +hlv.w a0, 1(a1) # CHECK: :[[@LINE]]:11: error: immediate must be zero + +hlv.wu a0, 0x10 # CHECK: :[[@LINE]]:12: error: immediate must be zero + +hlv.wu a0, 1(a1) # CHECK: :[[@LINE]]:12: error: immediate must be zero + +hlv.d a0, 0x10 # CHECK: :[[@LINE]]:11: error: immediate must be zero + +hlv.d a0, 1(a1) # CHECK: :[[@LINE]]:11: error: immediate must be zero + +hsv.b a0, 0x10 # CHECK: :[[@LINE]]:11: error: immediate must be zero + +hsv.b a0, 1(a1) # CHECK: :[[@LINE]]:11: error: immediate must be zero + +hsv.h a0, 0x10 # CHECK: :[[@LINE]]:11: error: immediate must be zero + +hsv.h a0, 1(a1) # CHECK: :[[@LINE]]:11: error: immediate must be zero + +hsv.w a0, 0x10 # CHECK: :[[@LINE]]:11: error: immediate must be zero + +hsv.w a0, 1(a1) # CHECK: :[[@LINE]]:11: error: immediate must be zero + +hsv.d a0, 0x10 # CHECK: :[[@LINE]]:11: error: immediate must be zero + +hsv.d a0, 1(a1) # CHECK: :[[@LINE]]:11: error: immediate must be zero diff --git a/llvm/test/MC/RISCV/priv-rv64-valid.s b/llvm/test/MC/RISCV/priv-rv64-valid.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/priv-rv64-valid.s @@ -0,0 +1,21 @@ +# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ +# RUN: | llvm-objdump -M no-aliases -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s + +# CHECK-INST: hlv.wu a0, 0(a1) +# CHECK: encoding: [0x73,0xc5,0x15,0x68] +hlv.wu a0, (a1) + +# CHECK-INST: hlv.wu a0, 0(a1) +# CHECK: encoding: [0x73,0xc5,0x15,0x68] +hlv.wu a0, 0(a1) + +# CHECK-INST: hlv.d a0, 0(a1) +# CHECK: encoding: [0x73,0xc5,0x05,0x6c] +hlv.d a0, (a1) + +# CHECK-INST: hsv.d a0, 0(a1) +# CHECK: encoding: [0x73,0xc0,0xa5,0x6e] +hsv.d a0, (a1) diff --git a/llvm/test/MC/RISCV/priv-valid.s b/llvm/test/MC/RISCV/priv-valid.s --- a/llvm/test/MC/RISCV/priv-valid.s +++ b/llvm/test/MC/RISCV/priv-valid.s @@ -9,10 +9,6 @@ # RUN: | llvm-objdump -M no-aliases -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST %s -# CHECK-INST: uret -# CHECK: encoding: [0x73,0x00,0x20,0x00] -uret - # CHECK-INST: sret # CHECK: encoding: [0x73,0x00,0x20,0x10] sret @@ -32,3 +28,91 @@ # CHECK-INST: sfence.vma a0, a1 # CHECK: encoding: [0x73,0x00,0xb5,0x12] sfence.vma a0, a1 + +# CHECK-INST: sinval.vma zero, zero +# CHECK: encoding: [0x73,0x00,0x00,0x16] +sinval.vma zero, zero + +# CHECK-INST: sinval.vma a0, a1 +# CHECK: encoding: [0x73,0x00,0xb5,0x16] +sinval.vma a0, a1 + +# CHECK-INST: sfence.w.inval +# CHECK: encoding: [0x73,0x00,0x00,0x18] +sfence.w.inval + +# CHECK-INST: sfence.inval.ir +# CHECK: encoding: [0x73,0x00,0x10,0x18] +sfence.inval.ir + +# CHECK-INST: hfence.vvma zero, zero +# CHECK: encoding: [0x73,0x00,0x00,0x22] +hfence.vvma zero, zero + +# CHECK-INST: hfence.vvma a0, a1 +# CHECK: encoding: [0x73,0x00,0xb5,0x22] +hfence.vvma a0, a1 + +# CHECK-INST: hfence.gvma zero, zero +# CHECK: encoding: [0x73,0x00,0x00,0x62] +hfence.gvma zero, zero + +# CHECK-INST: hfence.gvma a0, a1 +# CHECK: encoding: [0x73,0x00,0xb5,0x62] +hfence.gvma a0, a1 + +# CHECK-INST: hinval.vvma zero, zero +# CHECK: encoding: [0x73,0x00,0x00,0x26] +hinval.vvma zero, zero + +# CHECK-INST: hinval.vvma a0, a1 +# CHECK: encoding: [0x73,0x00,0xb5,0x26] +hinval.vvma a0, a1 + +# CHECK-INST: hinval.gvma zero, zero +# CHECK: encoding: [0x73,0x00,0x00,0x66] +hinval.gvma zero, zero + +# CHECK-INST: hinval.gvma a0, a1 +# CHECK: encoding: [0x73,0x00,0xb5,0x66] +hinval.gvma a0, a1 + +# CHECK-INST: hlv.b a0, 0(a1) +# CHECK: encoding: [0x73,0xc5,0x05,0x60] +hlv.b a0, 0(a1) + +# CHECK-INST: hlv.bu a0, 0(a1) +# CHECK: encoding: [0x73,0xc5,0x15,0x60] +hlv.bu a0, 0(a1) + +# CHECK-INST: hlv.h a1, 0(a2) +# CHECK: encoding: [0xf3,0x45,0x06,0x64] +hlv.h a1, 0(a2) + +# CHECK-INST: hlv.hu a1, 0(a1) +# CHECK: encoding: [0xf3,0xc5,0x15,0x64] +hlv.hu a1, 0(a1) + +# CHECK-INST: hlvx.hu a1, 0(a2) +# CHECK: encoding: [0xf3,0x45,0x36,0x64] +hlvx.hu a1, 0(a2) + +# CHECK-INST: hlv.w a2, 0(a2) +# CHECK: encoding: [0x73,0x46,0x06,0x68] +hlv.w a2, 0(a2) + +# CHECK-INST: hlvx.wu a2, 0(a3) +# CHECK: encoding: [0x73,0xc6,0x36,0x68] +hlvx.wu a2, 0(a3) + +# CHECK-INST: hsv.b a0, 0(a1) +# CHECK: encoding: [0x73,0xc0,0xa5,0x62] +hsv.b a0, 0(a1) + +# CHECK-INST: hsv.h a0, 0(a1) +# CHECK: encoding: [0x73,0xc0,0xa5,0x66] +hsv.h a0, 0(a1) + +# CHECK-INST: hsv.w a0, 0(a1) +# CHECK: encoding: [0x73,0xc0,0xa5,0x6a] +hsv.w a0, 0(a1) diff --git a/llvm/test/MC/RISCV/rv32e-valid.s b/llvm/test/MC/RISCV/rv32e-valid.s --- a/llvm/test/MC/RISCV/rv32e-valid.s +++ b/llvm/test/MC/RISCV/rv32e-valid.s @@ -111,10 +111,6 @@ csrrs s0, 0xc00, x0 # CHECK-ASM-AND-OBJ: csrrs s0, fflags, a5 csrrs s0, 0x001, a5 -# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra -csrrc sp, 0x000, ra -# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0 -csrrwi a5, 0x000, 0 # CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31 csrrsi t2, 0xfff, 31 # CHECK-ASM-AND-OBJ: csrrci t1, sscratch, 5 diff --git a/llvm/test/MC/RISCV/rv32i-valid.s b/llvm/test/MC/RISCV/rv32i-valid.s --- a/llvm/test/MC/RISCV/rv32i-valid.s +++ b/llvm/test/MC/RISCV/rv32i-valid.s @@ -361,12 +361,6 @@ # CHECK-ASM-AND-OBJ: csrrs s3, fflags, s5 # CHECK-ASM: encoding: [0xf3,0xa9,0x1a,0x00] csrrs s3, 0x001, s5 -# CHECK-ASM-AND-OBJ: csrrc sp, ustatus, ra -# CHECK-ASM: encoding: [0x73,0xb1,0x00,0x00] -csrrc sp, 0x000, ra -# CHECK-ASM-AND-OBJ: csrrwi a5, ustatus, 0 -# CHECK-ASM: encoding: [0xf3,0x57,0x00,0x00] -csrrwi a5, 0x000, 0 # CHECK-ASM-AND-OBJ: csrrsi t2, 4095, 31 # CHECK-ASM: encoding: [0xf3,0xe3,0xff,0xff] csrrsi t2, 0xfff, 31 diff --git a/llvm/test/MC/RISCV/rvi-aliases-valid.s b/llvm/test/MC/RISCV/rvi-aliases-valid.s --- a/llvm/test/MC/RISCV/rvi-aliases-valid.s +++ b/llvm/test/MC/RISCV/rvi-aliases-valid.s @@ -256,6 +256,12 @@ # CHECK-S-OBJ-NOALIAS: sfence.vma a0, zero # CHECK-S-OBJ: sfence.vma a0 sfence.vma a0 +# CHECK-S-OBJ-NOALIAS: hfence.gvma zero, zero +# CHECK-S-OBJ: hfence.gvma +hfence.gvma +# CHECK-S-OBJ-NOALIAS: hfence.gvma a0, zero +# CHECK-S-OBJ: hfence.gvma a0 +hfence.gvma a0 # The following aliases are accepted as input but the canonical form # of the instruction will always be printed. diff --git a/llvm/test/MC/RISCV/user-csr-names.s b/llvm/test/MC/RISCV/user-csr-names.s --- a/llvm/test/MC/RISCV/user-csr-names.s +++ b/llvm/test/MC/RISCV/user-csr-names.s @@ -10,125 +10,6 @@ # RUN: | llvm-objdump -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s -################################## -# User Trap Setup -################################## - -# ustatus -# name -# CHECK-INST: csrrs t1, ustatus, zero -# CHECK-ENC: encoding: [0x73,0x23,0x00,0x00] -# CHECK-INST-ALIAS: csrr t1, ustatus -# uimm12 -# CHECK-INST: csrrs t2, ustatus, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x00] -# CHECK-INST-ALIAS: csrr t2, ustatus -csrrs t1, ustatus, zero -# uimm12 -csrrs t2, 0x000, zero - -# uie -# name -# CHECK-INST: csrrs t1, uie, zero -# CHECK-ENC: encoding: [0x73,0x23,0x40,0x00] -# CHECK-INST-ALIAS: csrr t1, uie -# uimm12 -# CHECK-INST: csrrs t2, uie, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x00] -# CHECK-INST-ALIAS: csrr t2, uie -# name -csrrs t1, uie, zero -# uimm12 -csrrs t2, 0x004, zero - -# utvec -# name -# CHECK-INST: csrrs t1, utvec, zero -# CHECK-ENC: encoding: [0x73,0x23,0x50,0x00] -# CHECK-INST-ALIAS: csrr t1, utvec -# uimm12 -# CHECK-INST: csrrs t2, utvec, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x00] -# CHECK-INST-ALIAS: csrr t2, utvec -# name -csrrs t1, utvec, zero -# uimm12 -csrrs t2, 0x005, zero - -################################## -# User Trap Handling -################################## - -# uscratch -# name -# CHECK-INST: csrrs t1, uscratch, zero -# CHECK-ENC: encoding: [0x73,0x23,0x00,0x04] -# CHECK-INST-ALIAS: csrr t1, uscratch -# uimm12 -# CHECK-INST: csrrs t2, uscratch, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x04] -# CHECK-INST-ALIAS: csrr t2, uscratch -# name -csrrs t1, uscratch, zero -# uimm12 -csrrs t2, 0x040, zero - -# uepc -# name -# CHECK-INST: csrrs t1, uepc, zero -# CHECK-ENC: encoding: [0x73,0x23,0x10,0x04] -# CHECK-INST-ALIAS: csrr t1, uepc -# uimm12 -# CHECK-INST: csrrs t2, uepc, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x04] -# CHECK-INST-ALIAS: csrr t2, uepc -# name -csrrs t1, uepc, zero -# uimm12 -csrrs t2, 0x041, zero - -# ucause -# name -# CHECK-INST: csrrs t1, ucause, zero -# CHECK-ENC: encoding: [0x73,0x23,0x20,0x04] -# CHECK-INST-ALIAS: csrr t1, ucause -# uimm12 -# CHECK-INST: csrrs t2, ucause, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x04] -# CHECK-INST-ALIAS: csrr t2, ucause -# name -csrrs t1, ucause, zero -# uimm12 -csrrs t2, 0x042, zero - -# utval -# name -# CHECK-INST: csrrs t1, utval, zero -# CHECK-ENC: encoding: [0x73,0x23,0x30,0x04] -# CHECK-INST-ALIAS: csrr t1, utval -# uimm12 -# CHECK-INST: csrrs t2, utval, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x04] -# CHECK-INST-ALIAS: csrr t2, utval -# name -csrrs t1, utval, zero -# uimm12 -csrrs t2, 0x043, zero - -# uip -# name -# CHECK-INST: csrrs t1, uip, zero -# CHECK-ENC: encoding: [0x73,0x23,0x40,0x04] -# CHECK-INST-ALIAS: csrr t1, uip -# uimm12 -# CHECK-INST: csrrs t2, uip, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x04] -# CHECK-INST-ALIAS: csrr t2, uip -#name -csrrs t1, uip, zero -# uimm12 -csrrs t2, 0x044, zero - ################################## # User Floating Pont CSRs ##################################