diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -125,6 +125,9 @@
 def : SysReg<"sie", 0x104>;
 def : SysReg<"stvec", 0x105>;
 def : SysReg<"scounteren", 0x106>;
+def : SysReg<"stimecmp", 0x14D>;
+let isRV32Only = 1 in
+def : SysReg<"stimecmph", 0x15D>;
 
 //===----------------------------------------------------------------------===//
 // Supervisor Configuration
@@ -221,6 +224,9 @@
 def : SysReg<"vscause", 0x242>;
 def : SysReg<"vstval", 0x243>;
 def : SysReg<"vsip", 0x244>;
+def : SysReg<"vstimecmp", 0x24D>;
+let isRV32Only = 1 in
+def : SysReg<"vstimecmph", 0x25D>;
 def : SysReg<"vsatp", 0x280>;
 
 //===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/RISCV/hypervisor-csr-names.s b/llvm/test/MC/RISCV/hypervisor-csr-names.s
--- a/llvm/test/MC/RISCV/hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/hypervisor-csr-names.s
@@ -360,6 +360,20 @@
 # uimm12
 csrrs t2, 0x244, zero
 
+# vstimecmp
+# name
+# CHECK-INST: csrrs t1, vstimecmp, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x24]
+# CHECK-INST-ALIAS: csrr t1, vstimecmp
+# uimm12
+# CHECK-INST: csrrs t2, vstimecmp, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x24]
+# CHECK-INST-ALIAS: csrr t2, vstimecmp
+# name
+csrrs t1, vstimecmp, zero
+# uimm12
+csrrs t2, 0x24D, zero
+
 # vsatp
 # name
 # CHECK-INST: csrrs t1, vsatp, zero
diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
--- a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -40,6 +40,24 @@
 # uimm12
 csrrs t2, 0x615, zero
 
+################################
+# Virtual Supervisor Registers
+################################
+
+# vstimecmph
+# name
+# CHECK-INST: csrrs t1, vstimecmph, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x25]
+# CHECK-INST-ALIAS: csrr t1, vstimecmph
+# uimm12
+# CHECK-INST: csrrs t2, vstimecmph, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x25]
+# CHECK-INST-ALIAS: csrr t2, vstimecmph
+# name
+csrrs t1, vstimecmph, zero
+# uimm12
+csrrs t2, 0x25D, zero
+
 #########################################
 # State Enable Extension (Smstateen)
 #########################################
diff --git a/llvm/test/MC/RISCV/rv32-only-csr-names.s b/llvm/test/MC/RISCV/rv32-only-csr-names.s
--- a/llvm/test/MC/RISCV/rv32-only-csr-names.s
+++ b/llvm/test/MC/RISCV/rv32-only-csr-names.s
@@ -128,3 +128,6 @@
 csrrs t1, hstateen1h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
 csrrs t1, hstateen3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
 csrrs t1, hstateen3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+
+csrrs t1, stimecmph, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
+csrrs t1, vstimecmph, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled
diff --git a/llvm/test/MC/RISCV/rv32-supervisor-csr-names.s b/llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
new file mode 100644
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
@@ -0,0 +1,23 @@
+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:     | llvm-objdump -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST-ALIAS %s
+
+##################################
+# Supervisor Trap Setup
+##################################
+
+# stimecmph
+# name
+# CHECK-INST: csrrs t1, stimecmph, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x15]
+# CHECK-INST-ALIAS: csrr t1, stimecmph
+# uimm12
+# CHECK-INST: csrrs t2, stimecmph, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x15]
+# CHECK-INST-ALIAS: csrr t2, stimecmph
+# name
+csrrs t1, stimecmph, zero
+# uimm12
+csrrs t2, 0x15D, zero
diff --git a/llvm/test/MC/RISCV/supervisor-csr-names.s b/llvm/test/MC/RISCV/supervisor-csr-names.s
--- a/llvm/test/MC/RISCV/supervisor-csr-names.s
+++ b/llvm/test/MC/RISCV/supervisor-csr-names.s
@@ -98,6 +98,20 @@
 # uimm12
 csrrs t2, 0x106, zero
 
+# stimecmp
+# name
+# CHECK-INST: csrrs t1, stimecmp, zero
+# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x14]
+# CHECK-INST-ALIAS: csrr t1, stimecmp
+# uimm12
+# CHECK-INST: csrrs t2, stimecmp, zero
+# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x14]
+# CHECK-INST-ALIAS: csrr t2, stimecmp
+# name
+csrrs t1, stimecmp, zero
+# uimm12
+csrrs t2, 0x14D, zero
+
 ##################################
 # Supervisor Configuration
 ##################################