diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -1023,12 +1023,16 @@
           (SH3ADD (SH2ADD GPR:$r, GPR:$r), GPR:$r)>;
 def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 73)),
           (SH3ADD (SH3ADD GPR:$r, GPR:$r), GPR:$r)>;
-def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 27)),
-          (SH1ADD (SH3ADD GPR:$r, GPR:$r), (SH3ADD GPR:$r, GPR:$r))>;
-def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 45)),
-          (SH2ADD (SH3ADD GPR:$r, GPR:$r), (SH3ADD GPR:$r, GPR:$r))>;
-def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 81)),
-          (SH3ADD (SH3ADD GPR:$r, GPR:$r), (SH3ADD GPR:$r, GPR:$r))>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 23)),
+          (SH2ADD (SH2ADD GPR:$r, GPR:$r), (SH1ADD GPR:$r, GPR:$r))>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 43)),
+          (SH3ADD (SH2ADD GPR:$r, GPR:$r), (SH1ADD GPR:$r, GPR:$r))>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 39)),
+          (SH2ADD (SH3ADD GPR:$r, GPR:$r), (SH1ADD GPR:$r, GPR:$r))>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 75)),
+          (SH3ADD (SH3ADD GPR:$r, GPR:$r), (SH1ADD GPR:$r, GPR:$r))>;
+def : Pat<(mul_const_oneuse GPR:$r, (XLenVT 77)),
+          (SH3ADD (SH3ADD GPR:$r, GPR:$r), (SH2ADD GPR:$r, GPR:$r))>;
 } // Predicates = [HasStdExtZba]
 
 let Predicates = [HasStdExtZba, IsRV64] in {
diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll
--- a/llvm/test/CodeGen/RISCV/rv64zba.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zba.ll
@@ -861,51 +861,88 @@
   ret i64 %c
 }
 
-define i64 @mul27(i64 %a) {
-; RV64I-LABEL: mul27:
+define i64 @mul23(i64 %a) {
+; RV64I-LABEL: mul23:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, 27
+; RV64I-NEXT:    li a1, 23
 ; RV64I-NEXT:    mul a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBA-LABEL: mul27:
+; RV64ZBA-LABEL: mul23:
 ; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    sh3add a0, a0, a0
-; RV64ZBA-NEXT:    sh1add a0, a0, a0
+; RV64ZBA-NEXT:    sh1add a1, a0, a0
+; RV64ZBA-NEXT:    sh2add a0, a0, a0
+; RV64ZBA-NEXT:    sh2add a0, a0, a1
 ; RV64ZBA-NEXT:    ret
-  %c = mul i64 %a, 27
+  %c = mul i64 %a, 23
   ret i64 %c
 }
 
-define i64 @mul45(i64 %a) {
-; RV64I-LABEL: mul45:
+define i64 @mul43(i64 %a) {
+; RV64I-LABEL: mul43:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, 45
+; RV64I-NEXT:    li a1, 43
 ; RV64I-NEXT:    mul a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBA-LABEL: mul45:
+; RV64ZBA-LABEL: mul43:
 ; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    sh3add a0, a0, a0
+; RV64ZBA-NEXT:    sh1add a1, a0, a0
 ; RV64ZBA-NEXT:    sh2add a0, a0, a0
+; RV64ZBA-NEXT:    sh3add a0, a0, a1
 ; RV64ZBA-NEXT:    ret
-  %c = mul i64 %a, 45
+  %c = mul i64 %a, 43
   ret i64 %c
 }
 
-define i64 @mul81(i64 %a) {
-; RV64I-LABEL: mul81:
+define i64 @mul39(i64 %a) {
+; RV64I-LABEL: mul39:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    li a1, 81
+; RV64I-NEXT:    li a1, 39
 ; RV64I-NEXT:    mul a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
-; RV64ZBA-LABEL: mul81:
+; RV64ZBA-LABEL: mul39:
 ; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    sh1add a1, a0, a0
 ; RV64ZBA-NEXT:    sh3add a0, a0, a0
+; RV64ZBA-NEXT:    sh2add a0, a0, a1
+; RV64ZBA-NEXT:    ret
+  %c = mul i64 %a, 39
+  ret i64 %c
+}
+
+define i64 @mul75(i64 %a) {
+; RV64I-LABEL: mul75:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a1, 75
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64ZBA-LABEL: mul75:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    sh1add a1, a0, a0
+; RV64ZBA-NEXT:    sh3add a0, a0, a0
+; RV64ZBA-NEXT:    sh3add a0, a0, a1
+; RV64ZBA-NEXT:    ret
+  %c = mul i64 %a, 75
+  ret i64 %c
+}
+
+define i64 @mul77(i64 %a) {
+; RV64I-LABEL: mul77:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a1, 77
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64ZBA-LABEL: mul77:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    sh2add a1, a0, a0
 ; RV64ZBA-NEXT:    sh3add a0, a0, a0
+; RV64ZBA-NEXT:    sh3add a0, a0, a1
 ; RV64ZBA-NEXT:    ret
-  %c = mul i64 %a, 81
+  %c = mul i64 %a, 77
   ret i64 %c
 }