Index: lib/Target/AMDGPU/SIRegisterInfo.td
===================================================================
--- lib/Target/AMDGPU/SIRegisterInfo.td
+++ lib/Target/AMDGPU/SIRegisterInfo.td
@@ -184,6 +184,7 @@
 
 // Special register classes for predicates and the M0 register
 def SCCReg : RegisterClass<"AMDGPU", [i32, i1], 32, (add SCC)> {
+  let isAllocatable = 0;
   let CopyCost = -1; // Theoretically it is possible to read from SCC,
                      // but it should never be necessary.
 }