diff --git a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
--- a/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
+++ b/llvm/lib/Target/M68k/M68kISelDAGToDAG.cpp
@@ -181,6 +181,7 @@
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
+  bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
 
 private:
   /// Keep a pointer to the M68kSubtarget around so that we can
@@ -311,6 +312,24 @@
 };
 } // namespace
 
+bool M68kDAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
+                                          SDNode *Root) const {
+  if (OptLevel == CodeGenOpt::None)
+    return false;
+
+  if (U == Root) {
+    switch (U->getOpcode()) {
+    default:
+      return true;
+    case M68kISD::SUB:
+    case ISD::SUB:
+      return false;
+    }
+  }
+
+  return true;
+}
+
 bool M68kDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
   Subtarget = &static_cast<const M68kSubtarget &>(MF.getSubtarget());
   return SelectionDAGISel::runOnMachineFunction(MF);
diff --git a/llvm/test/CodeGen/M68k/Arith/imul-neg.ll b/llvm/test/CodeGen/M68k/Arith/imul-neg.ll
--- a/llvm/test/CodeGen/M68k/Arith/imul-neg.ll
+++ b/llvm/test/CodeGen/M68k/Arith/imul-neg.ll
@@ -1,14 +1,12 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=m68k-linux | FileCheck %s
-; FIXME: When using SelectionDAGISel, the following cases use
-; `sub` rather than the expected `neg`
 
 define i32 @mul4294967295_32(i32 %A) {
 ; CHECK-LABEL: mul4294967295_32:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0:
-; CHECK-NEXT:    move.l #0, %d0
-; CHECK-NEXT:    sub.l (4,%sp), %d0
+; CHECK-NEXT:    move.l	(4,%sp), %d0
+; CHECK-NEXT:    neg.l	%d0
 ; CHECK-NEXT:    rts
     %mul = mul i32 %A, 4294967295
     ret i32 %mul
@@ -19,10 +17,10 @@
 ; CHECK-LABEL: mul18446744073709551615_64:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0:
-; CHECK-NEXT:    move.l (4,%sp), %d0
-; CHECK-NEXT:    move.l #0, %d1
-; CHECK-NEXT:    sub.l (8,%sp), %d1
-; CHECK-NEXT:    negx.l %d0
+; CHECK-NEXT:    move.l	(4,%sp), %d0
+; CHECK-NEXT:    move.l	(8,%sp), %d1
+; CHECK-NEXT:    neg.l	%d1
+; CHECK-NEXT:    negx.l	%d0
 ; CHECK-NEXT:    rts
     %mul = mul i64 %A, 18446744073709551615
     ret i64 %mul
diff --git a/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll
--- a/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll
+++ b/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll
@@ -12,8 +12,9 @@
 ; CHECK-LABEL: func1:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    suba.l #12, %sp
+; CHECK-NEXT:    move.l	(20,%sp), %d1
 ; CHECK-NEXT:    move.l (16,%sp), %d0
-; CHECK-NEXT:    sub.l (20,%sp), %d0
+; CHECK-NEXT:    sub.l	%d1, %d0
 ; CHECK-NEXT:    bvc .LBB0_1
 ; CHECK-NEXT:  ; %bb.2: ; %overflow
 ; CHECK-NEXT:    lea (no,%pc), %a0
@@ -49,8 +50,9 @@
 ; CHECK-LABEL: func2:
 ; CHECK:       ; %bb.0: ; %entry
 ; CHECK-NEXT:    suba.l #12, %sp
-; CHECK-NEXT:    move.l (16,%sp), %d0
-; CHECK-NEXT:    sub.l (20,%sp), %d0
+; CHECK-NEXT:    move.l	(20,%sp), %d1
+; CHECK-NEXT:    move.l	(16,%sp), %d0
+; CHECK-NEXT:    sub.l	%d1, %d0
 ; CHECK-NEXT:    bcc .LBB1_1
 ; CHECK-NEXT:  ; %bb.2: ; %carry
 ; CHECK-NEXT:    lea (no,%pc), %a0
diff --git a/llvm/test/CodeGen/M68k/Control/cmp.ll b/llvm/test/CodeGen/M68k/Control/cmp.ll
--- a/llvm/test/CodeGen/M68k/Control/cmp.ll
+++ b/llvm/test/CodeGen/M68k/Control/cmp.ll
@@ -230,17 +230,23 @@
 ; CHECK-LABEL: test15:
 ; CHECK:         .cfi_startproc
 ; CHECK-NEXT:  ; %bb.0:
-; CHECK-NEXT:    move.l #16, %d0
-; CHECK-NEXT:    move.l (4,%sp), %d1
-; CHECK-NEXT:    lsr.l %d0, %d1
-; CHECK-NEXT:    move.l %d1, %d0
-; CHECK-NEXT:    sub.l (8,%sp), %d0
+; CHECK-NEXT:    suba.l	#4, %sp
+; CHECK-NEXT:    .cfi_def_cfa_offset -8
+; CHECK-NEXT:    movem.l	%d2, (0,%sp)
+; CHECK-NEXT:    move.l	#16, %d0
+; CHECK-NEXT:    move.l	(8,%sp), %d1
+; CHECK-NEXT:    lsr.l	%d0, %d1
+; CHECK-NEXT:    move.l	(12,%sp), %d0
+; CHECK-NEXT:    move.l	%d1, %d2
+; CHECK-NEXT:    sub.l	%d0, %d2
 ; CHECK-NEXT:    scc %d0
 ; CHECK-NEXT:    cmpi.l #0, %d1
 ; CHECK-NEXT:    seq %d1
 ; CHECK-NEXT:    or.b %d0, %d1
 ; CHECK-NEXT:    move.l %d1, %d0
 ; CHECK-NEXT:    and.l #255, %d0
+; CHECK-NEXT:    movem.l	(0,%sp), %d2
+; CHECK-NEXT:    adda.l	#4, %sp
 ; CHECK-NEXT:    rts
   %bf.lshr = lshr i32 %bf.load, 16
   %cmp2 = icmp eq i32 %bf.lshr, 0