Index: lib/Target/Mips/MicroMips32r6InstrFormats.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrFormats.td +++ lib/Target/Mips/MicroMips32r6InstrFormats.td @@ -287,3 +287,33 @@ let Inst{10} = rotate; let Inst{9-0} = funct; } + +class ABS_FM_MMR6 fmt, bits<7> funct> : MMR6Arch, MipsR6Inst { + bits<5> ft; + bits<5> fs; + + bits<32> Inst; + + let Inst{31-26} = 0b010101; + let Inst{25-21} = ft; + let Inst{20-16} = fs; + let Inst{15} = 0; + let Inst{14-13} = fmt; + let Inst{12-6} = funct; + let Inst{5-0} = 0b111011; +} + +class FLOOR_FM_MMR6 fmt, bits<8> funct> : MMR6Arch, MipsR6Inst { + bits<5> ft; + bits<5> fs; + + bits<32> Inst; + + let Inst{31-26} = 0b010101; + let Inst{25-21} = ft; + let Inst{20-16} = fs; + let Inst{15} = 0; + let Inst{14} = fmt; + let Inst{13-6} = funct; + let Inst{5-0} = 0b111011; +} Index: lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrInfo.td +++ lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -68,6 +68,26 @@ class SUBU_MMR6_ENC : ARITH_FM_MMR6<"subu", 0x1d0>; class XOR_MMR6_ENC : ARITH_FM_MMR6<"xor", 0x310>; class XORI_MMR6_ENC : ADDI_FM_MMR6<"xori", 0x1c>; +class ABS_MMR6_S_ENC : ABS_FM_MMR6<"abs.s", 0, 0b0001101>; +class ABS_MMR6_ENC : ABS_FM_MMR6<"abs.d", 1, 0b0001101>; +class FLOOR_L_MMR6_S_ENC : FLOOR_FM_MMR6<"floor.l.s", 0, 0b00001100>; +class FLOOR_L_MMR6_ENC : FLOOR_FM_MMR6<"floor.l.d", 1, 0b00001100>; +class FLOOR_W_S_MMR6_ENC : FLOOR_FM_MMR6<"floor.w.s", 0, 0b00101100>; +class FLOOR_W_MMR6_ENC : FLOOR_FM_MMR6<"floor.w.d", 1, 0b00101100>; +class CEIL_L_S_MMR6_ENC : FLOOR_FM_MMR6<"ceil.l.s", 0, 0b01001100>; +class CEIL_L_MMR6_ENC : FLOOR_FM_MMR6<"ceil.l.d", 1, 0b01001100>; +class CEIL_W_S_MMR6_ENC : FLOOR_FM_MMR6<"ceil.w.s", 0, 0b01101100>; +class CEIL_W_MMR6_ENC : FLOOR_FM_MMR6<"ceil.w.d", 1, 0b01101100>; +class TRUNC_L_S_MMR6_ENC : FLOOR_FM_MMR6<"trunc.l.s", 0, 0b10001100>; +class TRUNC_L_MMR6_ENC : FLOOR_FM_MMR6<"trunc.l.d", 1, 0b10001100>; +class TRUNC_W_S_MMR6_ENC : FLOOR_FM_MMR6<"trunc.w.s", 0, 0b10101100>; +class TRUNC_W_MMR6_ENC : FLOOR_FM_MMR6<"trunc.w.d", 1, 0b10101100>; + +class SQRT_S_MMR6_ENC : FLOOR_FM_MMR6<"sqrt.s", 0, 0b00101000>; +class SQRT_MMR6_ENC : FLOOR_FM_MMR6<"sqrt.d", 1, 0b00101000>; +class RSQRT_S_MMR6_ENC : FLOOR_FM_MMR6<"rsqrt.s", 0, 0b00001000>; +class RSQRT_MMR6_ENC : FLOOR_FM_MMR6<"rsqrt.d", 1, 0b00001000>; + class CMP_CBR_RT_Z_MMR6_DESC_BASE @@ -277,6 +297,58 @@ class XOR_MMR6_DESC : ArithLogicR<"xor", GPR32Opnd>; class XORI_MMR6_DESC : ArithLogicI<"xori", simm16, GPR32Opnd>; +class ABSS_FT_MMR6_DESC_BASE + : HARDFLOAT, NeverHasSideEffects { + dag OutOperandList = (outs DstRC:$ft); + dag InOperandList = (ins SrcRC:$fs); + string AsmString = !strconcat(instr_asm, "\t$ft, $fs"); + list Pattern = [(set DstRC:$ft, (OpNode SrcRC:$fs))]; + InstrItinClass Itinerary = Itin; + Format Form = FrmFR; + list EncodingPredicates = [HasStdEnc]; +} + +class ABS_MMR6_S_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.s", FGR32Opnd, FGR32Opnd, + II_ABS, fabs>; +class ABS_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"abs.d", AFGR64Opnd, AFGR64Opnd, + II_ABS, fabs>; + +class FLOOR_MMR6_S_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.s", FGR64Opnd, + FGR32Opnd, II_FLOOR>; +class FLOOR_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.l.d", FGR64Opnd, + FGR64Opnd, II_FLOOR>; +class FLOOR_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.s", FGR32Opnd, + FGR32Opnd, II_FLOOR>; +class FLOOR_W_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"floor.w.d", FGR32Opnd, + AFGR64Opnd, II_FLOOR>; +class CEIL_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.s", FGR64Opnd, + FGR32Opnd, II_CEIL>; +class CEIL_L_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.l.d", FGR64Opnd, + FGR64Opnd, II_CEIL>; +class CEIL_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.s", FGR32Opnd, + FGR32Opnd, II_CEIL>; +class CEIL_W_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"ceil.w.d", FGR32Opnd, + AFGR64Opnd, II_CEIL>; +class TRUNC_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.s", FGR64Opnd, + FGR32Opnd, II_TRUNC>; +class TRUNC_L_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.l.d", FGR64Opnd, + FGR64Opnd, II_TRUNC>; +class TRUNC_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.s", FGR32Opnd, + FGR32Opnd, II_TRUNC>; +class TRUNC_W_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"trunc.w.d", FGR32Opnd, + AFGR64Opnd, II_TRUNC>; + +class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd, + II_SQRT_S, fsqrt>; +class SQRT_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd, + II_SQRT_D, fsqrt>; +class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd, + FGR32Opnd, II_TRUNC>; +class RSQRT_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd, + AFGR64Opnd, II_TRUNC>; + //===----------------------------------------------------------------------===// // // Instruction Definitions @@ -348,6 +420,41 @@ def SUBU_MMR6 : StdMMR6Rel, SUBU_MMR6_DESC, SUBU_MMR6_ENC, ISA_MICROMIPS32R6; def XOR_MMR6 : StdMMR6Rel, XOR_MMR6_DESC, XOR_MMR6_ENC, ISA_MICROMIPS32R6; def XORI_MMR6 : StdMMR6Rel, XORI_MMR6_DESC, XORI_MMR6_ENC, ISA_MICROMIPS32R6; +def ABS_S_MMR6 : StdMMR6Rel, ABS_MMR6_S_ENC, ABS_MMR6_S_DESC, ISA_MICROMIPS32R6; +def ABS_MMR6 : StdMMR6Rel, ABS_MMR6_ENC, ABS_MMR6_DESC, ISA_MICROMIPS32R6; +def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_MMR6_S_ENC, FLOOR_MMR6_S_DESC, + ISA_MICROMIPS32R6; +def FLOOR_L_MMR6 : StdMMR6Rel, FLOOR_L_MMR6_ENC, FLOOR_MMR6_DESC, + ISA_MICROMIPS32R6; +def FLOOR_W_S_MMR6 : StdMMR6Rel, FLOOR_W_S_MMR6_ENC, FLOOR_W_S_MMR6_DESC, + ISA_MICROMIPS32R6; +def FLOOR_W_MMR6 : StdMMR6Rel, FLOOR_W_MMR6_ENC, FLOOR_W_MMR6_DESC, + ISA_MICROMIPS32R6; +def CEIL_L_S_MMR6 : StdMMR6Rel, CEIL_L_S_MMR6_ENC, CEIL_L_S_MMR6_DESC, + ISA_MICROMIPS32R6; +def CEIL_L_MMR6 : StdMMR6Rel, CEIL_L_MMR6_ENC, CEIL_L_MMR6_DESC, + ISA_MICROMIPS32R6; +def CEIL_W_S_MMR6 : StdMMR6Rel, CEIL_W_S_MMR6_ENC, CEIL_W_S_MMR6_DESC, + ISA_MICROMIPS32R6; +def CEIL_W_MMR6 : StdMMR6Rel, CEIL_W_MMR6_ENC, CEIL_W_MMR6_DESC, + ISA_MICROMIPS32R6; +def TRUNC_L_S_MMR6 : StdMMR6Rel, TRUNC_L_S_MMR6_ENC, TRUNC_L_S_MMR6_DESC, + ISA_MICROMIPS32R6; +def TRUNC_L_MMR6 : StdMMR6Rel, TRUNC_L_MMR6_ENC, TRUNC_L_MMR6_DESC, + ISA_MICROMIPS32R6; +def TRUNC_W_S_MMR6 : StdMMR6Rel, TRUNC_W_S_MMR6_ENC, TRUNC_W_S_MMR6_DESC, + ISA_MICROMIPS32R6; +def TRUNC_W_MMR6 : StdMMR6Rel, TRUNC_W_MMR6_ENC, TRUNC_W_MMR6_DESC, + ISA_MICROMIPS32R6; + +def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC, + ISA_MICROMIPS32R6; +def SQRT_MMR6 : StdMMR6Rel, SQRT_MMR6_ENC, SQRT_MMR6_DESC, + ISA_MICROMIPS32R6; +def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC, + ISA_MICROMIPS32R6; +def RSQRT_W_MMR6 : StdMMR6Rel, RSQRT_MMR6_ENC, RSQRT_MMR6_DESC, + ISA_MICROMIPS32R6; } //===----------------------------------------------------------------------===// Index: lib/Target/Mips/MipsInstrFPU.td =================================================================== --- lib/Target/Mips/MipsInstrFPU.td +++ lib/Target/Mips/MipsInstrFPU.td @@ -269,12 +269,14 @@ //===----------------------------------------------------------------------===// def ROUND_W_S : MMRel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd, II_ROUND>, ABSS_FM<0xc, 16>, ISA_MIPS2; -def TRUNC_W_S : MMRel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, +let AdditionalPredicates = [NotMips32r6] in { +def TRUNC_W_S : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, FGR32Opnd, II_TRUNC>, ABSS_FM<0xd, 16>, ISA_MIPS2; -def CEIL_W_S : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, +def CEIL_W_S : MMRel, StdMMR6Rel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, ABSS_FM<0xe, 16>, ISA_MIPS2; -def FLOOR_W_S : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>, +def FLOOR_W_S : MMRel, StdMMR6Rel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, II_FLOOR>, ABSS_FM<0xf, 16>, ISA_MIPS2; +} def CVT_W_S : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>, ABSS_FM<0x24, 16>; @@ -289,6 +291,7 @@ ABSS_FM<0x8, 16>, FGR_64; def ROUND_L_D64 : ABSS_FT<"round.l.d", FGR64Opnd, FGR64Opnd, II_ROUND>, ABSS_FM<0x8, 17>, FGR_64; + let AdditionalPredicates = [NotMips32r6] in { def TRUNC_L_S : ABSS_FT<"trunc.l.s", FGR64Opnd, FGR32Opnd, II_TRUNC>, ABSS_FM<0x9, 16>, FGR_64; def TRUNC_L_D64 : ABSS_FT<"trunc.l.d", FGR64Opnd, FGR64Opnd, II_TRUNC>, @@ -301,6 +304,7 @@ ABSS_FM<0xb, 16>, FGR_64; def FLOOR_L_D64 : ABSS_FT<"floor.l.d", FGR64Opnd, FGR64Opnd, II_FLOOR>, ABSS_FM<0xb, 17>, FGR_64; + } } def CVT_S_W : MMRel, ABSS_FT<"cvt.s.w", FGR32Opnd, FGR32Opnd, II_CVT>, @@ -345,8 +349,11 @@ defm FABS : ABSS_M<"abs.d", II_ABS, fabs>, ABSS_FM<0x5, 17>; defm FNEG : ABSS_M<"neg.d", II_NEG, fneg>, ABSS_FM<0x7, 17>; +let AdditionalPredicates = [NotMips32r6] in { def FSQRT_S : MMRel, ABSS_FT<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>, ABSS_FM<0x4, 16>, ISA_MIPS2; +} + defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2; // The odd-numbered registers are only referenced when doing loads, Index: test/MC/Disassembler/Mips/micromips32r6.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r6.txt +++ test/MC/Disassembler/Mips/micromips32r6.txt @@ -112,3 +112,39 @@ 0x00 0x64 0x3b 0x3c # CHECK: seh $3, $4 +0x54 0x65 0x03 0x7b # CHECK: abs.s $f3, $f5 + +0x54 0x44 0x23 0x7b # CHECK: abs.d $f2, $f4 + +0x54 0x65 0x03 0x3b # CHECK: floor.l.s $f3, $f5 + +0x54 0x44 0x43 0x3b # CHECK: floor.l.d $f2, $f4 + +0x54 0x65 0x0b 0x3b # CHECK: floor.w.s $f3, $f5 + +0x54 0x44 0x4b 0x3b # CHECK: floor.w.d $f2, $f4 + +0x54 0x65 0x13 0x3b # CHECK: ceil.l.s $f3, $f5 + +0x54 0x44 0x53 0x3b # CHECK: ceil.l.d $f2, $f4 + +0x54 0x65 0x1b 0x3b # CHECK: ceil.w.s $f3, $f5 + +0x54 0x44 0x5b 0x3b # CHECK: ceil.w.d $f2, $f4 + +0x54 0x65 0x23 0x3b # CHECK: trunc.l.s $f3, $f5 + +0x54 0x44 0x63 0x3b # CHECK: trunc.l.d $f2, $f4 + +0x54 0x65 0x2b 0x3b # CHECK: trunc.w.s $f3, $f5 + +0x54 0x44 0x6b 0x3b # CHECK: trunc.w.d $f2, $f4 + +0x54 0x65 0x0a 0x3b # CHECK: sqrt.s $f3, $f5 + +0x54 0x44 0x4a 0x3b # CHECK: sqrt.d $f2, $f4 + +0x54 0x65 0x02 0x3b # CHECK: rsqrt.s $f3, $f5 + +0x54 0x44 0x42 0x3b # CHECK: rsqrt.d $f2, $f4 + Index: test/MC/Disassembler/Mips/micromips64r6.txt =================================================================== --- test/MC/Disassembler/Mips/micromips64r6.txt +++ test/MC/Disassembler/Mips/micromips64r6.txt @@ -13,3 +13,39 @@ 0x59 0x26 0x30 0xd4 # CHECK: dextu $9, $6, 3, 7 0x58 0x43 0x25 0x1c # CHECK: dalign $4, $2, $3, 5 + +0x54 0x65 0x03 0x7b # CHECK: abs.s $f3, $f5 + +0x54 0x44 0x23 0x7b # CHECK: abs.d $f2, $f4 + +0x54 0x65 0x03 0x3b # CHECK: floor.l.s $f3, $f5 + +0x54 0x44 0x43 0x3b # CHECK: floor.l.d $f2, $f4 + +0x54 0x65 0x0b 0x3b # CHECK: floor.w.s $f3, $f5 + +0x54 0x44 0x4b 0x3b # CHECK: floor.w.d $f2, $f4 + +0x54 0x65 0x13 0x3b # CHECK: ceil.l.s $f3, $f5 + +0x54 0x44 0x53 0x3b # CHECK: ceil.l.d $f2, $f4 + +0x54 0x65 0x1b 0x3b # CHECK: ceil.w.s $f3, $f5 + +0x54 0x44 0x5b 0x3b # CHECK: ceil.w.d $f2, $f4 + +0x54 0x65 0x23 0x3b # CHECK: trunc.l.s $f3, $f5 + +0x54 0x44 0x63 0x3b # CHECK: trunc.l.d $f2, $f4 + +0x54 0x65 0x2b 0x3b # CHECK: trunc.w.s $f3, $f5 + +0x54 0x44 0x6b 0x3b # CHECK: trunc.w.d $f2, $f4 + +0x54 0x65 0x0a 0x3b # CHECK: sqrt.s $f3, $f5 + +0x54 0x44 0x4a 0x3b # CHECK: sqrt.d $f2, $f4 + +0x54 0x65 0x02 0x3b # CHECK: rsqrt.s $f3, $f5 + +0x54 0x44 0x42 0x3b # CHECK: rsqrt.d $f2, $f4 Index: test/MC/Mips/micromips32r6/valid.s =================================================================== --- test/MC/Mips/micromips32r6/valid.s +++ test/MC/Mips/micromips32r6/valid.s @@ -58,4 +58,21 @@ subu $3, $4, $5 # CHECK: subu $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xd0] xor $3, $4, $5 # CHECK: xor $3, $4, $5 # encoding: [0x00,0xa4,0x1b,0x10] xori $3, $4, 1234 # CHECK: xori $3, $4, 1234 # encoding: [0x70,0x64,0x04,0xd2] - + abs.s $f3, $f5 # CHECK: abs.s $f3, $f5 # encoding: [0x54,0x65,0x03,0x7b] + abs.d $f2, $f4 # CHECK: abs.d $f2, $f4 # encoding: [0x54,0x44,0x23,0x7b] + floor.l.s $f3, $f5 # CHECK: floor.l.s $f3, $f5 # encoding: [0x54,0x65,0x03,0x3b] + floor.l.d $f2, $f4 # CHECK: floor.l.d $f2, $f4 # encoding: [0x54,0x44,0x43,0x3b] + floor.w.s $f3, $f5 # CHECK: floor.w.s $f3, $f5 # encoding: [0x54,0x65,0x0b,0x3b] + floor.w.d $f2, $f4 # CHECK: floor.w.d $f2, $f4 # encoding: [0x54,0x44,0x4b,0x3b] + ceil.l.s $f3, $f5 # CHECK: ceil.l.s $f3, $f5 # encoding: [0x54,0x65,0x13,0x3b] + ceil.l.d $f2, $f4 # CHECK: ceil.l.d $f2, $f4 # encoding: [0x54,0x44,0x53,0x3b] + ceil.w.s $f3, $f5 # CHECK: ceil.w.s $f3, $f5 # encoding: [0x54,0x65,0x1b,0x3b] + ceil.w.d $f2, $f4 # CHECK: ceil.w.d $f2, $f4 # encoding: [0x54,0x44,0x5b,0x3b] + trunc.l.s $f3, $f5 # CHECK: trunc.l.s $f3, $f5 # encoding: [0x54,0x65,0x23,0x3b] + trunc.l.d $f2, $f4 # CHECK: trunc.l.d $f2, $f4 # encoding: [0x54,0x44,0x63,0x3b] + trunc.w.s $f3, $f5 # CHECK: trunc.w.s $f3, $f5 # encoding: [0x54,0x65,0x2b,0x3b] + trunc.w.d $f2, $f4 # CHECK: trunc.w.d $f2, $f4 # encoding: [0x54,0x44,0x6b,0x3b] + sqrt.s $f3, $f5 # CHECK: sqrt.s $f3, $f5 # encoding: [0x54,0x65,0x0a,0x3b] + sqrt.d $f2, $f4 # CHECK: sqrt.d $f2, $f4 # encoding: [0x54,0x44,0x4a,0x3b] + rsqrt.s $f3, $f5 # CHECK: rsqrt.s $f3, $f5 # encoding: [0x54,0x65,0x02,0x3b] + rsqrt.d $f2, $f4 # CHECK: rsqrt.d $f2, $f4 # encoding: [0x54,0x44,0x42,0x3b] Index: test/MC/Mips/micromips64r6/valid.s =================================================================== --- test/MC/Mips/micromips64r6/valid.s +++ test/MC/Mips/micromips64r6/valid.s @@ -8,5 +8,23 @@ dextm $9, $6, 3, 7 # CHECK: dextm $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xe4] dextu $9, $6, 3, 7 # CHECK: dextu $9, $6, 3, 7 # encoding: [0x59,0x26,0x30,0xd4] dalign $4, $2, $3, 5 # CHECK: dalign $4, $2, $3, 5 # encoding: [0x58,0x43,0x25,0x1c] + abs.s $f3, $f5 # CHECK: abs.s $f3, $f5 # encoding: [0x54,0x65,0x03,0x7b] + abs.d $f2, $f4 # CHECK: abs.d $f2, $f4 # encoding: [0x54,0x44,0x23,0x7b] + floor.l.s $f3, $f5 # CHECK: floor.l.s $f3, $f5 # encoding: [0x54,0x65,0x03,0x3b] + floor.l.d $f2, $f4 # CHECK: floor.l.d $f2, $f4 # encoding: [0x54,0x44,0x43,0x3b] + floor.w.s $f3, $f5 # CHECK: floor.w.s $f3, $f5 # encoding: [0x54,0x65,0x0b,0x3b] + floor.w.d $f2, $f4 # CHECK: floor.w.d $f2, $f4 # encoding: [0x54,0x44,0x4b,0x3b] + ceil.l.s $f3, $f5 # CHECK: ceil.l.s $f3, $f5 # encoding: [0x54,0x65,0x13,0x3b] + ceil.l.d $f2, $f4 # CHECK: ceil.l.d $f2, $f4 # encoding: [0x54,0x44,0x53,0x3b] + ceil.w.s $f3, $f5 # CHECK: ceil.w.s $f3, $f5 # encoding: [0x54,0x65,0x1b,0x3b] + ceil.w.d $f2, $f4 # CHECK: ceil.w.d $f2, $f4 # encoding: [0x54,0x44,0x5b,0x3b] + trunc.l.s $f3, $f5 # CHECK: trunc.l.s $f3, $f5 # encoding: [0x54,0x65,0x23,0x3b] + trunc.l.d $f2, $f4 # CHECK: trunc.l.d $f2, $f4 # encoding: [0x54,0x44,0x63,0x3b] + trunc.w.s $f3, $f5 # CHECK: trunc.w.s $f3, $f5 # encoding: [0x54,0x65,0x2b,0x3b] + trunc.w.d $f2, $f4 # CHECK: trunc.w.d $f2, $f4 # encoding: [0x54,0x44,0x6b,0x3b] + sqrt.s $f3, $f5 # CHECK: sqrt.s $f3, $f5 # encoding: [0x54,0x65,0x0a,0x3b] + sqrt.d $f2, $f4 # CHECK: sqrt.d $f2, $f4 # encoding: [0x54,0x44,0x4a,0x3b] + rsqrt.s $f3, $f5 # CHECK: rsqrt.s $f3, $f5 # encoding: [0x54,0x65,0x02,0x3b] + rsqrt.d $f2, $f4 # CHECK: rsqrt.d $f2, $f4 # encoding: [0x54,0x44,0x42,0x3b] 1: