diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -1,4 +1,4 @@ -//===- RISCVSystemOperands.td ----------------------------*- tablegen -*-===// +//===- RISCVSystemOperands.td ------------------------------*- tablegen -*-===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -172,12 +172,16 @@ // Supervisor Trap Setup //===-------------------------- def : SysReg<"sstatus", 0x100>; -def : SysReg<"sedeleg", 0x102>; -def : SysReg<"sideleg", 0x103>; def : SysReg<"sie", 0x104>; def : SysReg<"stvec", 0x105>; def : SysReg<"scounteren", 0x106>; +//===-------------------------------------------------------------------------// +// Supervisor Trap Setup +//===-------------------------------------------------------------------------// + +def : SysReg<"senvcfg", 0x10A>; + //===-------------------------- // Supervisor Trap Handling //===-------------------------- @@ -194,6 +198,74 @@ let DeprecatedName = "sptbr" in def : SysReg<"satp", 0x180>; +//===-------------------------------------------------------------------------// +// Debug/Trace Registers +//===-------------------------------------------------------------------------// + +def : SysReg<"scontext", 0x5A8>; + +//===-------------------------------------------------------------------------// +// Hypervisor Trap Setup +//===-------------------------------------------------------------------------// + +def : SysReg<"hstatus", 0x600>; +def : SysReg<"hedeleg", 0x602>; +def : SysReg<"hideleg", 0x603>; +def : SysReg<"hie", 0x604>; +def : SysReg<"hcounteren", 0x606>; +def : SysReg<"hgeie", 0x607>; + +//===-------------------------------------------------------------------------// +// Hypervisor Trap Handling +//===-------------------------------------------------------------------------// + +def : SysReg<"htval", 0x643>; +def : SysReg<"hip", 0x644>; +def : SysReg<"hvip", 0x645>; +def : SysReg<"htinst", 0x64A>; +def : SysReg<"hgeip", 0xE12>; + +//===-------------------------------------------------------------------------// +// Hypervisor Configuration +//===-------------------------------------------------------------------------// + +def : SysReg<"henvcfg", 0x60A>; +let isRV32Only = 1 in +def : SysReg<"henvcfgh", 0x61A>; + +//===-------------------------------------------------------------------------// +// Hypervisor Protection and Translation +//===-------------------------------------------------------------------------// + +def : SysReg<"hgatp", 0x680>; + +//===-------------------------------------------------------------------------// +// Debug/Trace Registers +//===-------------------------------------------------------------------------// + +def : SysReg<"hcontext", 0x6A8>; + +//===-------------------------------------------------------------------------// +// Hypervisor Counter/Timer Virtualization Registers +//===-------------------------------------------------------------------------// + +def : SysReg<"htimedelta", 0x605>; +def : SysReg<"htimedeltah", 0x615>; + +//===-------------------------------------------------------------------------// +// Virtual Supervisor Registers +//===-------------------------------------------------------------------------// + +def : SysReg<"vsstatus", 0x200>; +def : SysReg<"vsie", 0x204>; +def : SysReg<"vstvec", 0x205>; +def : SysReg<"vsscratch", 0x240>; +def : SysReg<"vsepc", 0x241>; +def : SysReg<"vscause", 0x242>; +def : SysReg<"vstval", 0x243>; +def : SysReg<"vsip", 0x244>; +def : SysReg<"vsatp", 0x280>; + //===----------------------------- // Machine Information Registers //===----------------------------- @@ -202,6 +274,7 @@ def : SysReg<"marchid", 0xF12>; def : SysReg<"mimpid", 0xF13>; def : SysReg<"mhartid", 0xF14>; +def : SysReg<"mconfigptr", 0xF15>; //===----------------------------- // Machine Trap Setup @@ -213,6 +286,8 @@ def : SysReg<"mie", 0x304>; def : SysReg<"mtvec", 0x305>; def : SysReg<"mcounteren", 0x306>; +let isRV32Only = 1 in +def : SysReg<"mstatush", 0x310>; //===----------------------------- // Machine Trap Handling @@ -223,16 +298,47 @@ let DeprecatedName = "mbadaddr" in def : SysReg<"mtval", 0x343>; def : SysReg<"mip", 0x344>; +def : SysReg<"mtinst", 0x34A>; +def : SysReg<"mtval2", 0x34B>; + +//===----------------------------- +// Machine Configuration +//===----------------------------- + +def : SysReg<"menvcfg", 0x30A>; +let isRV32Only = 1 in +def : SysReg<"menvcfgh", 0x31A>; +def : SysReg<"mseccfg", 0x747>; +let isRV32Only = 1 in +def : SysReg<"mseccfgh", 0x757>; //===---------------------------------- // Machine Protection and Translation //===---------------------------------- def : SysReg<"pmpcfg0", 0x3A0>; -def : SysReg<"pmpcfg2", 0x3A2>; -let isRV32Only = 1 in { +let isRV32Only = 1 in def : SysReg<"pmpcfg1", 0x3A1>; +def : SysReg<"pmpcfg2", 0x3A2>; +let isRV32Only = 1 in def : SysReg<"pmpcfg3", 0x3A3>; -} +def : SysReg<"pmpcfg4", 0x3A4>; +let isRV32Only = 1 in +def : SysReg<"pmpcfg5", 0x3A5>; +def : SysReg<"pmpcfg6", 0x3A6>; +let isRV32Only = 1 in +def : SysReg<"pmpcfg7", 0x3A7>; +def : SysReg<"pmpcfg8", 0x3A8>; +let isRV32Only = 1 in +def : SysReg<"pmpcfg9", 0x3A9>; +def : SysReg<"pmpcfg10", 0x3AA>; +let isRV32Only = 1 in +def : SysReg<"pmpcfg11", 0x3AB>; +def : SysReg<"pmpcfg12", 0x3AC>; +let isRV32Only = 1 in +def : SysReg<"pmpcfg13", 0x3AD>; +def : SysReg<"pmpcfg14", 0x3AE>; +let isRV32Only = 1 in +def : SysReg<"pmpcfg15", 0x3AF>; def : SysReg<"pmpaddr0", 0x3B0>; def : SysReg<"pmpaddr1", 0x3B1>; @@ -250,6 +356,54 @@ def : SysReg<"pmpaddr13", 0x3BD>; def : SysReg<"pmpaddr14", 0x3BE>; def : SysReg<"pmpaddr15", 0x3BF>; +def : SysReg<"pmpaddr16", 0x3C0>; +def : SysReg<"pmpaddr17", 0x3C1>; +def : SysReg<"pmpaddr18", 0x3C2>; +def : SysReg<"pmpaddr19", 0x3C3>; +def : SysReg<"pmpaddr20", 0x3C4>; +def : SysReg<"pmpaddr21", 0x3C5>; +def : SysReg<"pmpaddr22", 0x3C6>; +def : SysReg<"pmpaddr23", 0x3C7>; +def : SysReg<"pmpaddr24", 0x3C8>; +def : SysReg<"pmpaddr25", 0x3C9>; +def : SysReg<"pmpaddr26", 0x3CA>; +def : SysReg<"pmpaddr27", 0x3CB>; +def : SysReg<"pmpaddr28", 0x3CC>; +def : SysReg<"pmpaddr29", 0x3CD>; +def : SysReg<"pmpaddr30", 0x3CE>; +def : SysReg<"pmpaddr31", 0x3CF>; +def : SysReg<"pmpaddr32", 0x3D0>; +def : SysReg<"pmpaddr33", 0x3D1>; +def : SysReg<"pmpaddr34", 0x3D2>; +def : SysReg<"pmpaddr35", 0x3D3>; +def : SysReg<"pmpaddr36", 0x3D4>; +def : SysReg<"pmpaddr37", 0x3D5>; +def : SysReg<"pmpaddr38", 0x3D6>; +def : SysReg<"pmpaddr39", 0x3D7>; +def : SysReg<"pmpaddr40", 0x3D8>; +def : SysReg<"pmpaddr41", 0x3D9>; +def : SysReg<"pmpaddr42", 0x3DA>; +def : SysReg<"pmpaddr43", 0x3DB>; +def : SysReg<"pmpaddr44", 0x3DC>; +def : SysReg<"pmpaddr45", 0x3DD>; +def : SysReg<"pmpaddr46", 0x3DE>; +def : SysReg<"pmpaddr47", 0x3DF>; +def : SysReg<"pmpaddr48", 0x3E0>; +def : SysReg<"pmpaddr49", 0x3E1>; +def : SysReg<"pmpaddr50", 0x3E2>; +def : SysReg<"pmpaddr51", 0x3E3>; +def : SysReg<"pmpaddr52", 0x3E4>; +def : SysReg<"pmpaddr53", 0x3E5>; +def : SysReg<"pmpaddr54", 0x3E6>; +def : SysReg<"pmpaddr55", 0x3E7>; +def : SysReg<"pmpaddr56", 0x3E8>; +def : SysReg<"pmpaddr57", 0x3E9>; +def : SysReg<"pmpaddr58", 0x3EA>; +def : SysReg<"pmpaddr59", 0x3EB>; +def : SysReg<"pmpaddr60", 0x3EC>; +def : SysReg<"pmpaddr61", 0x3ED>; +def : SysReg<"pmpaddr62", 0x3EE>; +def : SysReg<"pmpaddr63", 0x3EF>; //===-------------------------- @@ -366,6 +520,7 @@ def : SysReg<"tdata1", 0x7A1>; def : SysReg<"tdata2", 0x7A2>; def : SysReg<"tdata3", 0x7A3>; +def : SysReg<"mcontext", 0x7A8>; //===----------------------------------------------- // Debug Mode Registers diff --git a/llvm/test/MC/RISCV/hypervisor-csr-names.s b/llvm/test/MC/RISCV/hypervisor-csr-names.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/hypervisor-csr-names.s @@ -0,0 +1,389 @@ +# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s +# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ +# RUN: | llvm-objdump -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s +# +# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s +# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \ +# RUN: | llvm-objdump -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s + +################################## +# Hypervisor Trap Setup +################################## + +# hstatus +# name +# CHECK-INST: csrrs t1, hstatus, zero +# CHECK-ENC: encoding: [0x73,0x23,0x00,0x60] +# CHECK-INST-ALIAS: csrr t1, hstatus +# uimm12 +# CHECK-INST: csrrs t2, hstatus, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x60] +# CHECK-INST-ALIAS: csrr t2, hstatus +# name +csrrs t1, hstatus, zero +# uimm12 +csrrs t2, 0x600, zero + +# hedeleg +# name +# CHECK-INST: csrrs t1, hedeleg, zero +# CHECK-ENC: encoding: [0x73,0x23,0x20,0x60] +# CHECK-INST-ALIAS: csrr t1, hedeleg +# uimm12 +# CHECK-INST: csrrs t2, hedeleg, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x60] +# CHECK-INST-ALIAS: csrr t2, hedeleg +# name +csrrs t1, hedeleg, zero +# uimm12 +csrrs t2, 0x602, zero + +# hideleg +# name +# CHECK-INST: csrrs t1, hideleg, zero +# CHECK-ENC: encoding: [0x73,0x23,0x30,0x60] +# CHECK-INST-ALIAS: csrr t1, hideleg +# uimm12 +# CHECK-INST: csrrs t2, hideleg, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x60] +# CHECK-INST-ALIAS: csrr t2, hideleg +# name +csrrs t1, hideleg, zero +# uimm12 +csrrs t2, 0x603, zero + +# hie +# name +# CHECK-INST: csrrs t1, hie, zero +# CHECK-ENC: encoding: [0x73,0x23,0x40,0x60] +# CHECK-INST-ALIAS: csrr t1, hie +# uimm12 +# CHECK-INST: csrrs t2, hie, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x60] +# CHECK-INST-ALIAS: csrr t2, hie +# name +csrrs t1, hie, zero +# uimm12 +csrrs t2, 0x604, zero + +# hcounteren +# name +# CHECK-INST: csrrs t1, hcounteren, zero +# CHECK-ENC: encoding: [0x73,0x23,0x60,0x60] +# CHECK-INST-ALIAS: csrr t1, hcounteren +# uimm12 +# CHECK-INST: csrrs t2, hcounteren, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x60] +# CHECK-INST-ALIAS: csrr t2, hcounteren +# name +csrrs t1, hcounteren, zero +# uimm12 +csrrs t2, 0x606, zero + +# hgeie +# name +# CHECK-INST: csrrs t1, hgeie, zero +# CHECK-ENC: encoding: [0x73,0x23,0x70,0x60] +# CHECK-INST-ALIAS: csrr t1, hgeie +# uimm12 +# CHECK-INST: csrrs t2, hgeie, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x60] +# CHECK-INST-ALIAS: csrr t2, hgeie +# name +csrrs t1, hgeie, zero +# uimm12 +csrrs t2, 0x607, zero + +################################## +# Hypervisor Trap Handling +################################## + +# htval +# name +# CHECK-INST: csrrs t1, htval, zero +# CHECK-ENC: encoding: [0x73,0x23,0x30,0x64] +# CHECK-INST-ALIAS: csrr t1, htval +# uimm12 +# CHECK-INST: csrrs t2, htval, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x64] +# CHECK-INST-ALIAS: csrr t2, htval +# name +csrrs t1, htval, zero +# uimm12 +csrrs t2, 0x643, zero + +# hip +# name +# CHECK-INST: csrrs t1, hip, zero +# CHECK-ENC: encoding: [0x73,0x23,0x40,0x64] +# CHECK-INST-ALIAS: csrr t1, hip +# uimm12 +# CHECK-INST: csrrs t2, hip, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x64] +# CHECK-INST-ALIAS: csrr t2, hip +# name +csrrs t1, hip, zero +# uimm12 +csrrs t2, 0x644, zero + +# hvip +# name +# CHECK-INST: csrrs t1, hvip, zero +# CHECK-ENC: encoding: [0x73,0x23,0x50,0x64] +# CHECK-INST-ALIAS: csrr t1, hvip +# uimm12 +# CHECK-INST: csrrs t2, hvip, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x64] +# CHECK-INST-ALIAS: csrr t2, hvip +# name +csrrs t1, hvip, zero +# uimm12 +csrrs t2, 0x645, zero + +# htinst +# name +# CHECK-INST: csrrs t1, htinst, zero +# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x64] +# CHECK-INST-ALIAS: csrr t1, htinst +# uimm12 +# CHECK-INST: csrrs t2, htinst, zero +# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x64] +# CHECK-INST-ALIAS: csrr t2, htinst +# name +csrrs t1, htinst, zero +# uimm12 +csrrs t2, 0x64A, zero + +# hgeip +# name +# CHECK-INST: csrrs t1, hgeip, zero +# CHECK-ENC: encoding: [0x73,0x23,0x20,0xe1] +# CHECK-INST-ALIAS: csrr t1, hgeip +# uimm12 +# CHECK-INST: csrrs t2, hgeip, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x20,0xe1] +# CHECK-INST-ALIAS: csrr t2, hgeip +# name +csrrs t1, hgeip, zero +# uimm12 +csrrs t2, 0xE12, zero + +################################## +# Hypervisor Configuration +################################## + +# henvcfg +# name +# CHECK-INST: csrrs t1, henvcfg, zero +# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x60] +# CHECK-INST-ALIAS: csrr t1, henvcfg +# uimm12 +# CHECK-INST: csrrs t2, henvcfg, zero +# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x60] +# CHECK-INST-ALIAS: csrr t2, henvcfg +# name +csrrs t1, henvcfg, zero +# uimm12 +csrrs t2, 0x60A, zero + +######################################## +# Hypervisor Protection and Translation +######################################## + +# hgatp +# name +# CHECK-INST: csrrs t1, hgatp, zero +# CHECK-ENC: encoding: [0x73,0x23,0x00,0x68] +# CHECK-INST-ALIAS: csrr t1, hgatp +# uimm12 +# CHECK-INST: csrrs t2, hgatp, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x68] +# CHECK-INST-ALIAS: csrr t2, hgatp +# name +csrrs t1, hgatp, zero +# uimm12 +csrrs t2, 0x680, zero + +########################## +# Debug/Trace Registers +########################## + +# hcontext +# name +# CHECK-INST: csrrs t1, hcontext, zero +# CHECK-ENC: encoding: [0x73,0x23,0x80,0x6a] +# CHECK-INST-ALIAS: csrr t1, hcontext +# uimm12 +# CHECK-INST: csrrs t2, hcontext, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x6a] +# CHECK-INST-ALIAS: csrr t2, hcontext +# name +csrrs t1, hcontext, zero +# uimm12 +csrrs t2, 0x6A8, zero + +#################################################### +# Hypervisor Counter/Timer Virtualization Registers +#################################################### + +# htimedelta +# name +# CHECK-INST: csrrs t1, htimedelta, zero +# CHECK-ENC: encoding: [0x73,0x23,0x50,0x60] +# CHECK-INST-ALIAS: csrr t1, htimedelta +# uimm12 +# CHECK-INST: csrrs t2, htimedelta, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x60] +# CHECK-INST-ALIAS: csrr t2, htimedelta +# name +csrrs t1, htimedelta, zero +# uimm12 +csrrs t2, 0x605, zero + +# htimedeltah +# name +# CHECK-INST: csrrs t1, htimedeltah, zero +# CHECK-ENC: encoding: [0x73,0x23,0x50,0x61] +# CHECK-INST-ALIAS: csrr t1, htimedeltah +# uimm12 +# CHECK-INST: csrrs t2, htimedeltah, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x61] +# CHECK-INST-ALIAS: csrr t2, htimedeltah +# name +csrrs t1, htimedeltah, zero +# uimm12 +csrrs t2, 0x615, zero + +################################ +# Virtual Supervisor Registers +################################ + +# vsstatus +# name +# CHECK-INST: csrrs t1, vsstatus, zero +# CHECK-ENC: encoding: [0x73,0x23,0x00,0x20] +# CHECK-INST-ALIAS: csrr t1, vsstatus +# uimm12 +# CHECK-INST: csrrs t2, vsstatus, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x20] +# CHECK-INST-ALIAS: csrr t2, vsstatus +# name +csrrs t1, vsstatus, zero +# uimm12 +csrrs t2, 0x200, zero + +# vsie +# name +# CHECK-INST: csrrs t1, vsie, zero +# CHECK-ENC: encoding: [0x73,0x23,0x40,0x20] +# CHECK-INST-ALIAS: csrr t1, vsie +# uimm12 +# CHECK-INST: csrrs t2, vsie, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x20] +# CHECK-INST-ALIAS: csrr t2, vsie +# name +csrrs t1, vsie, zero +# uimm12 +csrrs t2, 0x204, zero + +# vstvec +# name +# CHECK-INST: csrrs t1, vstvec, zero +# CHECK-ENC: encoding: [0x73,0x23,0x50,0x20] +# CHECK-INST-ALIAS: csrr t1, vstvec +# uimm12 +# CHECK-INST: csrrs t2, vstvec, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x20] +# CHECK-INST-ALIAS: csrr t2, vstvec +# name +csrrs t1, vstvec, zero +# uimm12 +csrrs t2, 0x205, zero + +# vsscratch +# name +# CHECK-INST: csrrs t1, vsscratch, zero +# CHECK-ENC: encoding: [0x73,0x23,0x00,0x24] +# CHECK-INST-ALIAS: csrr t1, vsscratch +# uimm12 +# CHECK-INST: csrrs t2, vsscratch, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x24] +# CHECK-INST-ALIAS: csrr t2, vsscratch +# name +csrrs t1, vsscratch, zero +# uimm12 +csrrs t2, 0x240, zero + +# vsepc +# name +# CHECK-INST: csrrs t1, vsepc, zero +# CHECK-ENC: encoding: [0x73,0x23,0x10,0x24] +# CHECK-INST-ALIAS: csrr t1, vsepc +# uimm12 +# CHECK-INST: csrrs t2, vsepc, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x10,0x24] +# CHECK-INST-ALIAS: csrr t2, vsepc +# name +csrrs t1, vsepc, zero +# uimm12 +csrrs t2, 0x241, zero + +# vscause +# name +# CHECK-INST: csrrs t1, vscause, zero +# CHECK-ENC: encoding: [0x73,0x23,0x20,0x24] +# CHECK-INST-ALIAS: csrr t1, vscause +# uimm12 +# CHECK-INST: csrrs t2, vscause, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x24] +# CHECK-INST-ALIAS: csrr t2, vscause +# name +csrrs t1, vscause, zero +# uimm12 +csrrs t2, 0x242, zero + +# vstval +# name +# CHECK-INST: csrrs t1, vstval, zero +# CHECK-ENC: encoding: [0x73,0x23,0x30,0x24] +# CHECK-INST-ALIAS: csrr t1, vstval +# uimm12 +# CHECK-INST: csrrs t2, vstval, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x24] +# CHECK-INST-ALIAS: csrr t2, vstval +# name +csrrs t1, vstval, zero +# uimm12 +csrrs t2, 0x243, zero + +# vsip +# name +# CHECK-INST: csrrs t1, vsip, zero +# CHECK-ENC: encoding: [0x73,0x23,0x40,0x24] +# CHECK-INST-ALIAS: csrr t1, vsip +# uimm12 +# CHECK-INST: csrrs t2, vsip, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x24] +# CHECK-INST-ALIAS: csrr t2, vsip +# name +csrrs t1, vsip, zero +# uimm12 +csrrs t2, 0x244, zero + +# vsatp +# name +# CHECK-INST: csrrs t1, vsatp, zero +# CHECK-ENC: encoding: [0x73,0x23,0x00,0x28] +# CHECK-INST-ALIAS: csrr t1, vsatp +# uimm12 +# CHECK-INST: csrrs t2, vsatp, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x28] +# CHECK-INST-ALIAS: csrr t2, vsatp +# name +csrrs t1, vsatp, zero +# uimm12 +csrrs t2, 0x280, zero diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s --- a/llvm/test/MC/RISCV/machine-csr-names.s +++ b/llvm/test/MC/RISCV/machine-csr-names.s @@ -69,6 +69,20 @@ # uimm12 csrrs t2, 0xF14, zero +# mconfigptr +# name +# CHECK-INST: csrrs t1, mconfigptr, zero +# CHECK-ENC: encoding: [0x73,0x23,0x50,0xf1] +# CHECK-INST-ALIAS: csrr t1, mconfigptr +# uimm12 +# CHECK-INST: csrrs t2, mconfigptr, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x50,0xf1] +# CHECK-INST-ALIAS: csrr t2, mconfigptr +# name +csrrs t1, mconfigptr, zero +# uimm12 +csrrs t2, 0xF15, zero + ################################## # Machine Trap Setup ################################## @@ -276,6 +290,90 @@ # uimm12 csrrs t2, 0x3A2, zero +# pmpcfg4 +# name +# CHECK-INST: csrrs t1, pmpcfg4, zero +# CHECK-ENC: encoding: [0x73,0x23,0x40,0x3a] +# CHECK-INST-ALIAS: csrr t1, pmpcfg4 +# uimm12 +# CHECK-INST: csrrs t2, pmpcfg4, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x40,0x3a] +# CHECK-INST-ALIAS: csrr t2, pmpcfg4 +# name +csrrs t1, pmpcfg4, zero +# uimm12 +csrrs t2, 0x3A4, zero + +# pmpcfg6 +# name +# CHECK-INST: csrrs t1, pmpcfg6, zero +# CHECK-ENC: encoding: [0x73,0x23,0x60,0x3a] +# CHECK-INST-ALIAS: csrr t1, pmpcfg6 +# uimm12 +# CHECK-INST: csrrs t2, pmpcfg6, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x60,0x3a] +# CHECK-INST-ALIAS: csrr t2, pmpcfg6 +# name +csrrs t1, pmpcfg6, zero +# uimm12 +csrrs t2, 0x3A6, zero + +# pmpcfg8 +# name +# CHECK-INST: csrrs t1, pmpcfg8, zero +# CHECK-ENC: encoding: [0x73,0x23,0x80,0x3a] +# CHECK-INST-ALIAS: csrr t1, pmpcfg8 +# uimm12 +# CHECK-INST: csrrs t2, pmpcfg8, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x3a] +# CHECK-INST-ALIAS: csrr t2, pmpcfg8 +# name +csrrs t1, pmpcfg8, zero +# uimm12 +csrrs t2, 0x3A8, zero + +# pmpcfg10 +# name +# CHECK-INST: csrrs t1, pmpcfg10, zero +# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x3a] +# CHECK-INST-ALIAS: csrr t1, pmpcfg10 +# uimm12 +# CHECK-INST: csrrs t2, pmpcfg10, zero +# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x3a] +# CHECK-INST-ALIAS: csrr t2, pmpcfg10 +# name +csrrs t1, pmpcfg10, zero +# uimm12 +csrrs t2, 0x3AA, zero + +# pmpcfg12 +# name +# CHECK-INST: csrrs t1, pmpcfg12, zero +# CHECK-ENC: encoding: [0x73,0x23,0xc0,0x3a] +# CHECK-INST-ALIAS: csrr t1, pmpcfg12 +# uimm12 +# CHECK-INST: csrrs t2, pmpcfg12, zero +# CHECK-ENC: encoding: [0xf3,0x23,0xc0,0x3a] +# CHECK-INST-ALIAS: csrr t2, pmpcfg12 +# name +csrrs t1, pmpcfg12, zero +# uimm12 +csrrs t2, 0x3AC, zero + +# pmpcfg14 +# name +# CHECK-INST: csrrs t1, pmpcfg14, zero +# CHECK-ENC: encoding: [0x73,0x23,0xe0,0x3a] +# CHECK-INST-ALIAS: csrr t1, pmpcfg14 +# uimm12 +# CHECK-INST: csrrs t2, pmpcfg14, zero +# CHECK-ENC: encoding: [0xf3,0x23,0xe0,0x3a] +# CHECK-INST-ALIAS: csrr t2, pmpcfg14 +# name +csrrs t1, pmpcfg14, zero +# uimm12 +csrrs t2, 0x3AE, zero + ###################################### # Machine Counter and Timers @@ -352,7 +450,7 @@ # uimm12 csrrs t2, 0x7A2, zero -#tdata3 +# tdata3 # name # CHECK-INST: csrrs t1, tdata3, zero # CHECK-ENC: encoding: [0x73,0x23,0x30,0x7a] @@ -366,6 +464,20 @@ # uimm12 csrrs t2, 0x7A3, zero +# mcontext +# name +# CHECK-INST: csrrs t1, mcontext, zero +# CHECK-ENC: encoding: [0x73,0x23,0x80,0x7a] +# CHECK-INST-ALIAS: csrr t1, mcontext +# uimm12 +# CHECK-INST: csrrs t2, mcontext, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x7a] +# CHECK-INST-ALIAS: csrr t2, mcontext +# name +csrrs t1, mcontext, zero +# uimm12 +csrrs t2, 0x7A8, zero + ####################### # Debug Mode Registers ######################## diff --git a/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s new file mode 100644 --- /dev/null +++ b/llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s @@ -0,0 +1,23 @@ +# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s +# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \ +# RUN: | llvm-objdump -d - \ +# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s + +################################## +# Hypervisor Configuration +################################## + +# henvcfgh +# name +# CHECK-INST: csrrs t1, henvcfgh, zero +# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x61] +# CHECK-INST-ALIAS: csrr t1, henvcfgh +# uimm12 +# CHECK-INST: csrrs t2, henvcfgh, zero +# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x61] +# CHECK-INST-ALIAS: csrr t2, henvcfgh +# name +csrrs t1, henvcfgh, zero +# uimm12 +csrrs t2, 0x61A, zero diff --git a/llvm/test/MC/RISCV/rv32-machine-csr-names.s b/llvm/test/MC/RISCV/rv32-machine-csr-names.s --- a/llvm/test/MC/RISCV/rv32-machine-csr-names.s +++ b/llvm/test/MC/RISCV/rv32-machine-csr-names.s @@ -4,6 +4,56 @@ # RUN: | llvm-objdump -d - \ # RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s +###################################### +# Machine Trap Setup +###################################### + +# mstatush +# name +# CHECK-INST: csrrs t1, mstatush, zero +# CHECK-ENC: encoding: [0x73,0x23,0x00,0x31] +# CHECK-INST-ALIAS: csrr t1, mstatush +# uimm12 +# CHECK-INST: csrrs t2, mstatush, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x31] +# CHECK-INST-ALIAS: csrr t2, mstatush +# name +csrrs t1, mstatush, zero +# uimm12 +csrrs t2, 0x310, zero + +######################### +# Machine Configuration +######################### + +# menvcfgh +# name +# CHECK-INST: csrrs t1, menvcfgh, zero +# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x31] +# CHECK-INST-ALIAS: csrr t1, menvcfgh +# uimm12 +# CHECK-INST: csrrs t2, menvcfgh, zero +# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x31] +# CHECK-INST-ALIAS: csrr t2, menvcfgh +# name +csrrs t1, menvcfgh, zero +# uimm12 +csrrs t2, 0x31A, zero + +# mseccfgh +# name +# CHECK-INST: csrrs t1, mseccfgh, zero +# CHECK-ENC: encoding: [0x73,0x23,0x70,0x75] +# CHECK-INST-ALIAS: csrr t1, mseccfgh +# uimm12 +# CHECK-INST: csrrs t2, mseccfgh, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x75] +# CHECK-INST-ALIAS: csrr t2, mseccfgh +# name +csrrs t1, mseccfgh, zero +# uimm12 +csrrs t2, 0x757, zero + ###################################### # Machine Protection and Translation ###################################### @@ -36,6 +86,90 @@ # uimm12 csrrs t2, 0x3A3, zero +# pmpcfg5 +# name +# CHECK-INST: csrrs t1, pmpcfg5, zero +# CHECK-ENC: encoding: [0x73,0x23,0x50,0x3a] +# CHECK-INST-ALIAS: csrr t1, pmpcfg5 +# uimm12 +# CHECK-INST: csrrs t2, pmpcfg5, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x50,0x3a] +# CHECK-INST-ALIAS: csrr t2, pmpcfg5 +# name +csrrs t1, pmpcfg5, zero +# uimm12 +csrrs t2, 0x3A5, zero + +# pmpcfg7 +# name +# CHECK-INST: csrrs t1, pmpcfg7, zero +# CHECK-ENC: encoding: [0x73,0x23,0x70,0x3a] +# CHECK-INST-ALIAS: csrr t1, pmpcfg7 +# uimm12 +# CHECK-INST: csrrs t2, pmpcfg7, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x70,0x3a] +# CHECK-INST-ALIAS: csrr t2, pmpcfg7 +# name +csrrs t1, pmpcfg7, zero +# uimm12 +csrrs t2, 0x3A7, zero + +# pmpcfg9 +# name +# CHECK-INST: csrrs t1, pmpcfg9, zero +# CHECK-ENC: encoding: [0x73,0x23,0x90,0x3a] +# CHECK-INST-ALIAS: csrr t1, pmpcfg9 +# uimm12 +# CHECK-INST: csrrs t2, pmpcfg9, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x90,0x3a] +# CHECK-INST-ALIAS: csrr t2, pmpcfg9 +# name +csrrs t1, pmpcfg9, zero +# uimm12 +csrrs t2, 0x3A9, zero + +# pmpcfg11 +# name +# CHECK-INST: csrrs t1, pmpcfg11, zero +# CHECK-ENC: encoding: [0x73,0x23,0xb0,0x3a] +# CHECK-INST-ALIAS: csrr t1, pmpcfg11 +# uimm12 +# CHECK-INST: csrrs t2, pmpcfg11, zero +# CHECK-ENC: encoding: [0xf3,0x23,0xb0,0x3a] +# CHECK-INST-ALIAS: csrr t2, pmpcfg11 +# name +csrrs t1, pmpcfg11, zero +# uimm12 +csrrs t2, 0x3AB, zero + +# pmpcfg13 +# name +# CHECK-INST: csrrs t1, pmpcfg13, zero +# CHECK-ENC: encoding: [0x73,0x23,0xd0,0x3a] +# CHECK-INST-ALIAS: csrr t1, pmpcfg13 +# uimm12 +# CHECK-INST: csrrs t2, pmpcfg13, zero +# CHECK-ENC: encoding: [0xf3,0x23,0xd0,0x3a] +# CHECK-INST-ALIAS: csrr t2, pmpcfg13 +# name +csrrs t1, pmpcfg13, zero +# uimm12 +csrrs t2, 0x3AD, zero + +# pmpcfg15 +# name +# CHECK-INST: csrrs t1, pmpcfg15, zero +# CHECK-ENC: encoding: [0x73,0x23,0xf0,0x3a] +# CHECK-INST-ALIAS: csrr t1, pmpcfg15 +# uimm12 +# CHECK-INST: csrrs t2, pmpcfg15, zero +# CHECK-ENC: encoding: [0xf3,0x23,0xf0,0x3a] +# CHECK-INST-ALIAS: csrr t2, pmpcfg15 +# name +csrrs t1, pmpcfg15, zero +# uimm12 +csrrs t2, 0x3AF, zero + ###################################### # Machine Counter and Timers ###################################### @@ -471,4 +605,3 @@ csrrs t1, mhpmcounter31h, zero # uimm12 csrrs t2, 0xB9F, zero - diff --git a/llvm/test/MC/RISCV/supervisor-csr-names.s b/llvm/test/MC/RISCV/supervisor-csr-names.s --- a/llvm/test/MC/RISCV/supervisor-csr-names.s +++ b/llvm/test/MC/RISCV/supervisor-csr-names.s @@ -28,34 +28,6 @@ # uimm12 csrrs t2, 0x100, zero -# sedeleg -# name -# CHECK-INST: csrrs t1, sedeleg, zero -# CHECK-ENC: encoding: [0x73,0x23,0x20,0x10] -# CHECK-INST-ALIAS: csrr t1, sedeleg -# uimm12 -# CHECK-INST: csrrs t2, sedeleg, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x20,0x10] -# CHECK-INST-ALIAS: csrr t2, sedeleg -# name -csrrs t1, sedeleg, zero -# uimm12 -csrrs t2, 0x102, zero - -# sideleg -# name -# CHECK-INST: csrrs t1, sideleg, zero -# CHECK-ENC: encoding: [0x73,0x23,0x30,0x10] -# CHECK-INST-ALIAS: csrr t1, sideleg -# uimm12 -# CHECK-INST: csrrs t2, sideleg, zero -# CHECK-ENC: encoding: [0xf3,0x23,0x30,0x10] -# CHECK-INST-ALIAS: csrr t2, sideleg -# name -csrrs t1, sideleg, zero -# uimm12 -csrrs t2, 0x103, zero - # sie # name # CHECK-INST: csrrs t1, sie, zero @@ -98,6 +70,24 @@ # uimm12 csrrs t2, 0x106, zero +################################## +# Supervisor Configuration +################################## + +# senvcfg +# name +# CHECK-INST: csrrs t1, senvcfg, zero +# CHECK-ENC: encoding: [0x73,0x23,0xa0,0x10] +# CHECK-INST-ALIAS: csrr t1, senvcfg +# uimm12 +# CHECK-INST: csrrs t2, senvcfg, zero +# CHECK-ENC: encoding: [0xf3,0x23,0xa0,0x10] +# CHECK-INST-ALIAS: csrr t2, senvcfg +# name +csrrs t1, senvcfg, zero +# uimm12 +csrrs t2, 0x10A, zero + ################################## # Supervisor Trap Handling ################################## @@ -191,3 +181,21 @@ csrrs t1, satp, zero # uimm12 csrrs t2, 0x180, zero + +######################################### +# Debug/Trace Registers +######################################### + +# scontext +# name +# CHECK-INST: csrrs t1, scontext, zero +# CHECK-ENC: encoding: [0x73,0x23,0x80,0x5a] +# CHECK-INST-ALIAS: csrr t1, scontext +# uimm12 +# CHECK-INST: csrrs t2, scontext, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x80,0x5a] +# CHECK-INST-ALIAS: csrr t2, scontext +# name +csrrs t1, scontext, zero +# uimm12 +csrrs t2, 0x5A8, zero diff --git a/llvm/test/MC/RISCV/user-csr-names-invalid.s b/llvm/test/MC/RISCV/user-csr-names-invalid.s --- a/llvm/test/MC/RISCV/user-csr-names-invalid.s +++ b/llvm/test/MC/RISCV/user-csr-names-invalid.s @@ -36,3 +36,53 @@ csrrs t1, hpmcounter29h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, hpmcounter30h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled csrrs t1, hpmcounter31h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled + +csrrs t1, henvcfgh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled + +csrrs t1, mstatush, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled + +csrrs t1, menvcfgh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled + +csrrs t1, mseccfgh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled + +csrrs t1, pmpcfg1, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, pmpcfg3, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, pmpcfg5, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, pmpcfg7, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, pmpcfg9, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, pmpcfg11, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, pmpcfg13, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, pmpcfg15, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled + +csrrs t1, mcycleh, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, minstreth, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled + +csrrs t1, mhpmcounter3h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter4h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter5h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter6h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter7h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter8h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter9h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter10h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter11h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter12h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter13h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter14h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter15h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter16h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter17h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter18h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter19h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter20h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter21h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter22h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter23h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter24h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter25h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter26h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter27h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter28h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter29h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter30h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled +csrrs t1, mhpmcounter31h, zero # CHECK-NEED-RV32: :[[@LINE]]:11: error: system register use requires an option to be enabled