diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -141,6 +141,24 @@
     Res.push_back(RISCVMatInt::Inst(RISCV::ADDI, Lo12));
 }
 
+static unsigned extractRotateInfo(int64_t Val) {
+  // for case: 0b111..1..xxxxxx1..1..
+  unsigned LeadingOnes = countLeadingOnes((uint64_t)Val);
+  unsigned TrailingOnes = countTrailingOnes((uint64_t)Val);
+  if (TrailingOnes > 0 && TrailingOnes < 64 &&
+      (LeadingOnes + TrailingOnes) > (64 - 12))
+    return 64 - TrailingOnes;
+
+  // for case: 0bxxx1..1..1...xxx
+  unsigned UpperTrailingOnes = countTrailingOnes(Hi_32(Val));
+  unsigned LowerLeadingOnes = countLeadingOnes(Lo_32(Val));
+  if (UpperTrailingOnes < 32 &&
+      (UpperTrailingOnes + LowerLeadingOnes) > (64 - 12))
+    return 32 - UpperTrailingOnes;
+
+  return 0;
+}
+
 namespace llvm {
 namespace RISCVMatInt {
 InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
@@ -312,6 +330,18 @@
     }
   }
 
+  // Perform optimization with rori in the Zbb extension.
+  if (Res.size() > 2 && ActiveFeatures[RISCV::FeatureStdExtZbb]) {
+    if (unsigned Rotate = extractRotateInfo(Val)) {
+      RISCVMatInt::InstSeq TmpSeq;
+      uint64_t NegImm12 =
+          ((uint64_t)Val >> (64 - Rotate)) | ((uint64_t)Val << Rotate);
+      assert(isInt<12>(NegImm12));
+      TmpSeq.push_back(RISCVMatInt::Inst(RISCV::ADDI, NegImm12));
+      TmpSeq.push_back(RISCVMatInt::Inst(RISCV::RORI, Rotate));
+      Res = TmpSeq;
+    }
+  }
   return Res;
 }
 
diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll
--- a/llvm/test/CodeGen/RISCV/imm.ll
+++ b/llvm/test/CodeGen/RISCV/imm.ll
@@ -5,6 +5,8 @@
 ; RUN:   | FileCheck %s -check-prefix=RV64I
 ; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -mattr=+experimental-zba \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IZBA
+; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -mattr=+experimental-zbb \
+; RUN:   -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IZBB
 ; RUN: llc -mtriple=riscv64 -riscv-disable-using-constant-pool-for-large-ints -mattr=+experimental-zbs \
 ; RUN:   -verify-machineinstrs < %s | FileCheck %s -check-prefix=RV64IZBS
 
@@ -30,6 +32,11 @@
 ; RV64IZBA-NEXT:    li a0, 0
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: zero:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, 0
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: zero:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    li a0, 0
@@ -53,6 +60,11 @@
 ; RV64IZBA-NEXT:    li a0, 2047
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: pos_small:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, 2047
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: pos_small:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    li a0, 2047
@@ -76,6 +88,11 @@
 ; RV64IZBA-NEXT:    li a0, -2048
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: neg_small:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, -2048
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: neg_small:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    li a0, -2048
@@ -102,6 +119,12 @@
 ; RV64IZBA-NEXT:    addiw a0, a0, -1297
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: pos_i32:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 423811
+; RV64IZBB-NEXT:    addiw a0, a0, -1297
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: pos_i32:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 423811
@@ -129,6 +152,12 @@
 ; RV64IZBA-NEXT:    addiw a0, a0, -273
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: neg_i32:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 912092
+; RV64IZBB-NEXT:    addiw a0, a0, -273
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: neg_i32:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 912092
@@ -153,6 +182,11 @@
 ; RV64IZBA-NEXT:    lui a0, 16
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: pos_i32_hi20_only:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 16
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: pos_i32_hi20_only:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 16
@@ -176,6 +210,11 @@
 ; RV64IZBA-NEXT:    lui a0, 1048560
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: neg_i32_hi20_only:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 1048560
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: neg_i32_hi20_only:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 1048560
@@ -204,6 +243,12 @@
 ; RV64IZBA-NEXT:    addiw a0, a0, -64
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_left_shifted_addi:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 32
+; RV64IZBB-NEXT:    addiw a0, a0, -64
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_left_shifted_addi:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 32
@@ -233,6 +278,12 @@
 ; RV64IZBA-NEXT:    addiw a0, a0, -1
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_right_shifted_addi:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 524288
+; RV64IZBB-NEXT:    addiw a0, a0, -1
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_right_shifted_addi:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 524288
@@ -262,6 +313,12 @@
 ; RV64IZBA-NEXT:    addiw a0, a0, 580
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_right_shifted_lui:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 56
+; RV64IZBB-NEXT:    addiw a0, a0, 580
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_right_shifted_lui:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 56
@@ -289,6 +346,12 @@
 ; RV64IZBA-NEXT:    slli a0, a0, 31
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm64_1:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, 1
+; RV64IZBB-NEXT:    slli a0, a0, 31
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm64_1:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    li a0, 1
@@ -316,6 +379,12 @@
 ; RV64IZBA-NEXT:    srli a0, a0, 32
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm64_2:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, -1
+; RV64IZBB-NEXT:    srli a0, a0, 32
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm64_2:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    li a0, -1
@@ -343,6 +412,12 @@
 ; RV64IZBA-NEXT:    slli a0, a0, 32
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm64_3:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, 1
+; RV64IZBB-NEXT:    slli a0, a0, 32
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm64_3:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    li a0, 1
@@ -370,6 +445,12 @@
 ; RV64IZBA-NEXT:    slli a0, a0, 63
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm64_4:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, -1
+; RV64IZBB-NEXT:    slli a0, a0, 63
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm64_4:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    li a0, -1
@@ -397,6 +478,12 @@
 ; RV64IZBA-NEXT:    slli a0, a0, 63
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm64_5:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, -1
+; RV64IZBB-NEXT:    slli a0, a0, 63
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm64_5:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    li a0, -1
@@ -427,6 +514,13 @@
 ; RV64IZBA-NEXT:    slli a0, a0, 35
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm64_6:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 9321
+; RV64IZBB-NEXT:    addiw a0, a0, -1329
+; RV64IZBB-NEXT:    slli a0, a0, 35
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm64_6:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 9321
@@ -462,6 +556,15 @@
 ; RV64IZBA-NEXT:    addi a0, a0, 15
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm64_7:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, 7
+; RV64IZBB-NEXT:    slli a0, a0, 36
+; RV64IZBB-NEXT:    addi a0, a0, 11
+; RV64IZBB-NEXT:    slli a0, a0, 24
+; RV64IZBB-NEXT:    addi a0, a0, 15
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm64_7:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    li a0, 7
@@ -508,6 +611,18 @@
 ; RV64IZBA-NEXT:    addi a0, a0, -272
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm64_8:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 583
+; RV64IZBB-NEXT:    addiw a0, a0, -1875
+; RV64IZBB-NEXT:    slli a0, a0, 14
+; RV64IZBB-NEXT:    addi a0, a0, -947
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, 1511
+; RV64IZBB-NEXT:    slli a0, a0, 13
+; RV64IZBB-NEXT:    addi a0, a0, -272
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm64_8:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 583
@@ -539,6 +654,11 @@
 ; RV64IZBA-NEXT:    li a0, -1
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm64_9:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, -1
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm64_9:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    li a0, -1
@@ -568,6 +688,12 @@
 ; RV64IZBA-NEXT:    slli a0, a0, 1
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_left_shifted_lui_1:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 262145
+; RV64IZBB-NEXT:    slli a0, a0, 1
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_left_shifted_lui_1:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 262145
@@ -595,6 +721,12 @@
 ; RV64IZBA-NEXT:    slli a0, a0, 2
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_left_shifted_lui_2:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 262145
+; RV64IZBB-NEXT:    slli a0, a0, 2
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_left_shifted_lui_2:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 262145
@@ -623,6 +755,12 @@
 ; RV64IZBA-NEXT:    slli a0, a0, 20
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_left_shifted_lui_3:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 4097
+; RV64IZBB-NEXT:    slli a0, a0, 20
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_left_shifted_lui_3:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 4097
@@ -655,6 +793,12 @@
 ; RV64IZBA-NEXT:    srli a0, a0, 16
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_right_shifted_lui_1:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 983056
+; RV64IZBB-NEXT:    srli a0, a0, 16
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_right_shifted_lui_1:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 983056
@@ -685,6 +829,13 @@
 ; RV64IZBA-NEXT:    srli a0, a0, 24
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_right_shifted_lui_2:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 1044481
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    srli a0, a0, 24
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_right_shifted_lui_2:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 1044481
@@ -718,6 +869,13 @@
 ; RV64IZBA-NEXT:    addi a0, a0, -3
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_decoupled_lui_addi:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 4097
+; RV64IZBB-NEXT:    slli a0, a0, 20
+; RV64IZBB-NEXT:    addi a0, a0, -3
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_decoupled_lui_addi:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 4097
@@ -755,6 +913,15 @@
 ; RV64IZBA-NEXT:    addi a0, a0, -1
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_end_xori_1:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, -1
+; RV64IZBB-NEXT:    slli a0, a0, 36
+; RV64IZBB-NEXT:    addi a0, a0, 1
+; RV64IZBB-NEXT:    slli a0, a0, 25
+; RV64IZBB-NEXT:    addi a0, a0, -1
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_end_xori_1:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    li a0, -1
@@ -795,6 +962,15 @@
 ; RV64IZBA-NEXT:    addi a0, a0, 2047
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_end_2addi_1:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, -2047
+; RV64IZBB-NEXT:    slli a0, a0, 27
+; RV64IZBB-NEXT:    addi a0, a0, -1
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, 2047
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_end_2addi_1:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    li a0, -2047
@@ -839,6 +1015,17 @@
 ; RV64IZBA-NEXT:    addi a0, a0, 1656
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_2reg_1:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, -1
+; RV64IZBB-NEXT:    slli a0, a0, 35
+; RV64IZBB-NEXT:    addi a0, a0, 9
+; RV64IZBB-NEXT:    slli a0, a0, 13
+; RV64IZBB-NEXT:    addi a0, a0, 837
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, 1656
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_2reg_1:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 74565
@@ -871,6 +1058,12 @@
 ; RV64IZBA-NEXT:    sh a1, 0(a0)
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_store_i16_neg1:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a1, -1
+; RV64IZBB-NEXT:    sh a1, 0(a0)
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_store_i16_neg1:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    li a1, -1
@@ -900,6 +1093,12 @@
 ; RV64IZBA-NEXT:    sw a1, 0(a0)
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_store_i32_neg1:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a1, -1
+; RV64IZBB-NEXT:    sw a1, 0(a0)
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_store_i32_neg1:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    li a1, -1
@@ -932,6 +1131,14 @@
 ; RV64IZBA-NEXT:    addi a0, a0, -795
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_5372288229:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 160
+; RV64IZBB-NEXT:    addiw a0, a0, 437
+; RV64IZBB-NEXT:    slli a0, a0, 13
+; RV64IZBB-NEXT:    addi a0, a0, -795
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_5372288229:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 263018
@@ -964,6 +1171,14 @@
 ; RV64IZBA-NEXT:    sh1add a0, a0, a0
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_neg_5372288229:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 1048416
+; RV64IZBB-NEXT:    addiw a0, a0, -437
+; RV64IZBB-NEXT:    slli a0, a0, 13
+; RV64IZBB-NEXT:    addi a0, a0, 795
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_neg_5372288229:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 785558
@@ -996,6 +1211,14 @@
 ; RV64IZBA-NEXT:    sh2add a0, a0, a0
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_8953813715:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 267
+; RV64IZBB-NEXT:    addiw a0, a0, -637
+; RV64IZBB-NEXT:    slli a0, a0, 13
+; RV64IZBB-NEXT:    addi a0, a0, -1325
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_8953813715:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 88838
@@ -1028,6 +1251,14 @@
 ; RV64IZBA-NEXT:    sh2add a0, a0, a0
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_neg_8953813715:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 1048309
+; RV64IZBB-NEXT:    addiw a0, a0, 637
+; RV64IZBB-NEXT:    slli a0, a0, 13
+; RV64IZBB-NEXT:    addi a0, a0, 1325
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_neg_8953813715:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 959738
@@ -1060,6 +1291,14 @@
 ; RV64IZBA-NEXT:    sh3add a0, a0, a0
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_16116864687:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 961
+; RV64IZBB-NEXT:    addiw a0, a0, -1475
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, 1711
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_16116864687:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 961
@@ -1093,6 +1332,14 @@
 ; RV64IZBA-NEXT:    sh3add a0, a0, a0
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_neg_16116864687:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 1047615
+; RV64IZBB-NEXT:    addiw a0, a0, 1475
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, -1711
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_neg_16116864687:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 1047615
@@ -1125,6 +1372,13 @@
 ; RV64IZBA-NEXT:    addi a0, a0, -1093
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_2344336315:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 143087
+; RV64IZBB-NEXT:    slli a0, a0, 2
+; RV64IZBB-NEXT:    addi a0, a0, -1093
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_2344336315:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 143087
@@ -1162,6 +1416,16 @@
 ; RV64IZBA-NEXT:    addi a0, a0, -1093
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_70370820078523:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 256
+; RV64IZBB-NEXT:    addiw a0, a0, 31
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, -273
+; RV64IZBB-NEXT:    slli a0, a0, 14
+; RV64IZBB-NEXT:    addi a0, a0, -1093
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_70370820078523:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 506812
@@ -1201,6 +1465,17 @@
 ; RV64IZBA-NEXT:    addi a0, a0, -1093
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_neg_9223372034778874949:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, -1
+; RV64IZBB-NEXT:    slli a0, a0, 37
+; RV64IZBB-NEXT:    addi a0, a0, 31
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, -273
+; RV64IZBB-NEXT:    slli a0, a0, 14
+; RV64IZBB-NEXT:    addi a0, a0, -1093
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_neg_9223372034778874949:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 506812
@@ -1240,6 +1515,17 @@
 ; RV64IZBA-NEXT:    addi a0, a0, -1093
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_neg_9223301666034697285:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 917505
+; RV64IZBB-NEXT:    slli a0, a0, 8
+; RV64IZBB-NEXT:    addi a0, a0, 31
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, -273
+; RV64IZBB-NEXT:    slli a0, a0, 14
+; RV64IZBB-NEXT:    addi a0, a0, -1093
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_neg_9223301666034697285:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 506812
@@ -1272,6 +1558,13 @@
 ; RV64IZBA-NEXT:    addi a0, a0, -1093
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_neg_2219066437:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 913135
+; RV64IZBB-NEXT:    slli a0, a0, 2
+; RV64IZBB-NEXT:    addi a0, a0, -1093
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_neg_2219066437:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 913135
@@ -1306,6 +1599,14 @@
 ; RV64IZBA-NEXT:    addi a0, a0, -1093
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_neg_8798043653189:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 917475
+; RV64IZBB-NEXT:    addiw a0, a0, -273
+; RV64IZBB-NEXT:    slli a0, a0, 14
+; RV64IZBB-NEXT:    addi a0, a0, -1093
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_neg_8798043653189:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 572348
@@ -1342,6 +1643,15 @@
 ; RV64IZBA-NEXT:    srli a0, a0, 1
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_9223372034904144827:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 1048343
+; RV64IZBB-NEXT:    addiw a0, a0, 1911
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, 1911
+; RV64IZBB-NEXT:    srli a0, a0, 1
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_9223372034904144827:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 572348
@@ -1382,6 +1692,17 @@
 ; RV64IZBA-NEXT:    addi a0, a0, -1093
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_neg_9223354442718100411:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 524287
+; RV64IZBB-NEXT:    slli a0, a0, 6
+; RV64IZBB-NEXT:    addi a0, a0, -29
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, -273
+; RV64IZBB-NEXT:    slli a0, a0, 14
+; RV64IZBB-NEXT:    addi a0, a0, -1093
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_neg_9223354442718100411:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 572348
@@ -1415,6 +1736,14 @@
 ; RV64IZBA-NEXT:    zext.w a0, a0
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_2863311530:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 171
+; RV64IZBB-NEXT:    addiw a0, a0, -1365
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, -1366
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_2863311530:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 174763
@@ -1447,6 +1776,14 @@
 ; RV64IZBA-NEXT:    sh2add a0, a0, a0
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_neg_2863311530:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 1048405
+; RV64IZBB-NEXT:    addiw a0, a0, 1365
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, 1366
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_neg_2863311530:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 873813
@@ -1478,6 +1815,13 @@
 ; RV64IZBA-NEXT:    addi a0, a0, 1365
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_2147486378:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, 1
+; RV64IZBB-NEXT:    slli a0, a0, 31
+; RV64IZBB-NEXT:    addi a0, a0, 1365
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_2147486378:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    li a0, 1365
@@ -1508,6 +1852,13 @@
 ; RV64IZBA-NEXT:    addi a0, a0, -1365
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_neg_2147485013:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, -1
+; RV64IZBB-NEXT:    slli a0, a0, 31
+; RV64IZBB-NEXT:    addi a0, a0, -1365
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_neg_2147485013:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    li a0, -1365
@@ -1540,6 +1891,14 @@
 ; RV64IZBA-NEXT:    addi a0, a0, 1979
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_12900924131259:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 188
+; RV64IZBB-NEXT:    addiw a0, a0, -1093
+; RV64IZBB-NEXT:    slli a0, a0, 24
+; RV64IZBB-NEXT:    addi a0, a0, 1979
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_12900924131259:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 188
@@ -1570,6 +1929,13 @@
 ; RV64IZBA-NEXT:    slli.uw a0, a0, 4
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_50394234880:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 188
+; RV64IZBB-NEXT:    addiw a0, a0, -1093
+; RV64IZBB-NEXT:    slli a0, a0, 16
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_50394234880:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 188
@@ -1605,6 +1971,15 @@
 ; RV64IZBA-NEXT:    addi a0, a0, 1911
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_12900936431479:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 192239
+; RV64IZBB-NEXT:    slli a0, a0, 2
+; RV64IZBB-NEXT:    addi a0, a0, -1093
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, 1911
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_12900936431479:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 192239
@@ -1643,6 +2018,16 @@
 ; RV64IZBA-NEXT:    addi a0, a0, -1366
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_12900918536874:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 188
+; RV64IZBB-NEXT:    addiw a0, a0, -1093
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, -1365
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, -1366
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_12900918536874:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 188
@@ -1682,6 +2067,16 @@
 ; RV64IZBA-NEXT:    addi a0, a0, 273
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_12900925247761:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 188
+; RV64IZBB-NEXT:    addiw a0, a0, -1093
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, 273
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, 273
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_12900925247761:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 188
@@ -1717,6 +2112,14 @@
 ; RV64IZBA-NEXT:    addi a0, a0, 1
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_7158272001:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 427
+; RV64IZBB-NEXT:    addiw a0, a0, -1367
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, 1
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_7158272001:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 427
@@ -1750,6 +2153,14 @@
 ; RV64IZBA-NEXT:    addi a0, a0, 1
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_12884889601:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 768
+; RV64IZBB-NEXT:    addiw a0, a0, -3
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, 1
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_12884889601:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 768
@@ -1783,6 +2194,14 @@
 ; RV64IZBA-NEXT:    addi a0, a0, 1
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_neg_3435982847:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 1048371
+; RV64IZBB-NEXT:    addiw a0, a0, 817
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, 1
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_neg_3435982847:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 734001
@@ -1815,6 +2234,14 @@
 ; RV64IZBA-NEXT:    addi a0, a0, 1
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_neg_5726842879:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 1048235
+; RV64IZBB-NEXT:    addiw a0, a0, -1419
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, 1
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_neg_5726842879:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 698997
@@ -1847,6 +2274,14 @@
 ; RV64IZBA-NEXT:    addi a0, a0, 1
 ; RV64IZBA-NEXT:    ret
 ;
+; RV64IZBB-LABEL: imm_neg_10307948543:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    lui a0, 1047962
+; RV64IZBB-NEXT:    addiw a0, a0, -1645
+; RV64IZBB-NEXT:    slli a0, a0, 12
+; RV64IZBB-NEXT:    addi a0, a0, 1
+; RV64IZBB-NEXT:    ret
+;
 ; RV64IZBS-LABEL: imm_neg_10307948543:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 629139
@@ -1855,3 +2290,114 @@
 ; RV64IZBS-NEXT:    ret
   ret i64 -10307948543 ; 0xffff_fffd_9999_3001
 }
+
+define i64 @li_rori_1() {
+; RV32I-LABEL: li_rori_1:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a0, 1048567
+; RV32I-NEXT:    addi a1, a0, 2047
+; RV32I-NEXT:    li a0, -1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: li_rori_1:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a0, -17
+; RV64I-NEXT:    slli a0, a0, 43
+; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    ret
+;
+; RV64IZBA-LABEL: li_rori_1:
+; RV64IZBA:       # %bb.0:
+; RV64IZBA-NEXT:    li a0, -17
+; RV64IZBA-NEXT:    slli a0, a0, 43
+; RV64IZBA-NEXT:    addi a0, a0, -1
+; RV64IZBA-NEXT:    ret
+;
+; RV64IZBB-LABEL: li_rori_1:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, -18
+; RV64IZBB-NEXT:    rori a0, a0, 21
+; RV64IZBB-NEXT:    ret
+;
+; RV64IZBS-LABEL: li_rori_1:
+; RV64IZBS:       # %bb.0:
+; RV64IZBS-NEXT:    li a0, -17
+; RV64IZBS-NEXT:    slli a0, a0, 43
+; RV64IZBS-NEXT:    addi a0, a0, -1
+; RV64IZBS-NEXT:    ret
+  ret i64 -149533581377537
+}
+
+define i64 @li_rori_2() {
+; RV32I-LABEL: li_rori_2:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a0, 720896
+; RV32I-NEXT:    addi a1, a0, -1
+; RV32I-NEXT:    li a0, -6
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: li_rori_2:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a0, -5
+; RV64I-NEXT:    slli a0, a0, 60
+; RV64I-NEXT:    addi a0, a0, -6
+; RV64I-NEXT:    ret
+;
+; RV64IZBA-LABEL: li_rori_2:
+; RV64IZBA:       # %bb.0:
+; RV64IZBA-NEXT:    li a0, -5
+; RV64IZBA-NEXT:    slli a0, a0, 60
+; RV64IZBA-NEXT:    addi a0, a0, -6
+; RV64IZBA-NEXT:    ret
+;
+; RV64IZBB-LABEL: li_rori_2:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, -86
+; RV64IZBB-NEXT:    rori a0, a0, 4
+; RV64IZBB-NEXT:    ret
+;
+; RV64IZBS-LABEL: li_rori_2:
+; RV64IZBS:       # %bb.0:
+; RV64IZBS-NEXT:    li a0, -5
+; RV64IZBS-NEXT:    slli a0, a0, 60
+; RV64IZBS-NEXT:    addi a0, a0, -6
+; RV64IZBS-NEXT:    ret
+  ret i64 -5764607523034234886
+}
+
+define i64 @li_rori_3() {
+; RV32I-LABEL: li_rori_3:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a0, 491520
+; RV32I-NEXT:    addi a0, a0, -1
+; RV32I-NEXT:    li a1, -1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: li_rori_3:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    li a0, -17
+; RV64I-NEXT:    slli a0, a0, 27
+; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    ret
+;
+; RV64IZBA-LABEL: li_rori_3:
+; RV64IZBA:       # %bb.0:
+; RV64IZBA-NEXT:    li a0, -17
+; RV64IZBA-NEXT:    slli a0, a0, 27
+; RV64IZBA-NEXT:    addi a0, a0, -1
+; RV64IZBA-NEXT:    ret
+;
+; RV64IZBB-LABEL: li_rori_3:
+; RV64IZBB:       # %bb.0:
+; RV64IZBB-NEXT:    li a0, -18
+; RV64IZBB-NEXT:    rori a0, a0, 37
+; RV64IZBB-NEXT:    ret
+;
+; RV64IZBS-LABEL: li_rori_3:
+; RV64IZBS:       # %bb.0:
+; RV64IZBS-NEXT:    li a0, -17
+; RV64IZBS-NEXT:    slli a0, a0, 27
+; RV64IZBS-NEXT:    addi a0, a0, -1
+; RV64IZBS-NEXT:    ret
+  ret i64 -2281701377
+}
diff --git a/llvm/test/MC/RISCV/rv64zbb-valid.s b/llvm/test/MC/RISCV/rv64zbb-valid.s
--- a/llvm/test/MC/RISCV/rv64zbb-valid.s
+++ b/llvm/test/MC/RISCV/rv64zbb-valid.s
@@ -14,3 +14,13 @@
 # CHECK-ASM-AND-OBJ: cpopw t0, t1
 # CHECK-ASM: encoding: [0x9b,0x12,0x23,0x60]
 cpopw t0, t1
+
+# CHECK-ASM-AND-OBJ: addi t0, zero, -18
+# CHECK-ASM-AND-OBJ: rori t0, t0, 21
+li t0, -149533581377537
+# CHECK-ASM-AND-OBJ: addi t0, zero, -86
+# CHECK-ASM-AND-OBJ: rori t0, t0, 4
+li t0, -5764607523034234886
+# CHECK-ASM-AND-OBJ: addi t0, zero, -18
+# CHECK-ASM-AND-OBJ: rori t0, t0, 37
+li t0, -2281701377