Index: lib/Target/Mips/Disassembler/MipsDisassembler.cpp =================================================================== --- lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -284,6 +284,11 @@ uint64_t Address, const void *Decoder); +static DecodeStatus DecodeMemMMImm9(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, @@ -1303,6 +1308,24 @@ return MCDisassembler::Success; } +static DecodeStatus DecodeMemMMImm9(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder) { + int Offset = SignExtend32<16>(Insn & 0x1ff); + unsigned Reg = fieldFromInstruction(Insn, 21, 5); + unsigned Base = fieldFromInstruction(Insn, 16, 5); + + Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg); + Base = getReg(Decoder, Mips::GPR32RegClassID, Base); + + Inst.addOperand(MCOperand::createReg(Reg)); + Inst.addOperand(MCOperand::createReg(Base)); + Inst.addOperand(MCOperand::createImm(Offset)); + + return MCDisassembler::Success; +} + static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn, uint64_t Address, Index: lib/Target/Mips/MicroMipsInstrFormats.td =================================================================== --- lib/Target/Mips/MicroMipsInstrFormats.td +++ lib/Target/Mips/MicroMipsInstrFormats.td @@ -402,6 +402,20 @@ let Inst{11-0} = addr{11-0}; } +class STEVA_LDEVA_FM_MM type, bits<3> funct> { + bits<5> rt; + bits<21> addr; + + bits<32> Inst; + + let Inst{31-26} = 0x18; + let Inst{25-21} = rt; + let Inst{20-16} = addr{20-16}; + let Inst{15-12} = type; + let Inst{11-9} = funct; + let Inst{8-0} = addr{8-0}; +} + class CMov_F_I_FM_MM func> : MMArch { bits<5> rd; bits<5> rs; Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -714,6 +714,16 @@ LWL_FM_MM<0x8>; def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>, LWL_FM_MM<0x9>; + let DecoderMethod = "DecodeMemMMImm9" in { + def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_12>, + STEVA_LDEVA_FM_MM<0x6, 0x2>; + def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_12>, + STEVA_LDEVA_FM_MM<0x6, 0x3>; + def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_12>, + STEVA_LDEVA_FM_MM<0xa, 0x0>; + def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_12>, + STEVA_LDEVA_FM_MM<0xa, 0x1>, ISA_MIPS1_NOT_32R6_64R6; + } /// Load and Store Instructions - multiple def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>; Index: test/MC/Disassembler/Mips/micromips.txt =================================================================== --- test/MC/Disassembler/Mips/micromips.txt +++ test/MC/Disassembler/Mips/micromips.txt @@ -340,3 +340,11 @@ 0x00 0x00 0x57 0x7c # CHECK: ei 0x00 0x0a 0x57 0x7c # CHECK: ei $10 + +0x63 0x03 0xa2 0x05 # CHECK: swre $24, 5($3) + +0x63 0x03 0xa0 0x05 # CHECK: swle $24, 5($3) + +0x63 0x03 0x66 0x05 # CHECK: lwre $24, 5($3) + +0x63 0x04 0x64 0x02 # CHECK: lwle $24, 2($4) Index: test/MC/Disassembler/Mips/micromips_le.txt =================================================================== --- test/MC/Disassembler/Mips/micromips_le.txt +++ test/MC/Disassembler/Mips/micromips_le.txt @@ -340,3 +340,11 @@ 0x00 0x00 0x7c 0x57 # CHECK: ei 0x0a 0x00 0x7c 0x57 # CHECK: ei $10 + +0x03 0x63 0x05 0xa2 # CHECK: swre $24, 5($3) + +0x03 0x63 0x05 0xa0 # CHECK: swle $24, 5($3) + +0x03 0x63 0x05 0x66 # CHECK: lwre $24, 5($3) + +0x04 0x63 0x02 0x64 # CHECK: lwle $24, 2($4) Index: test/MC/Mips/micromips-control-instructions.s =================================================================== --- test/MC/Mips/micromips-control-instructions.s +++ test/MC/Mips/micromips-control-instructions.s @@ -39,6 +39,10 @@ # CHECK-EL: tlbr # encoding: [0x00,0x00,0x7c,0x13] # CHECK-EL: tlbwi # encoding: [0x00,0x00,0x7c,0x23] # CHECK-EL: tlbwr # encoding: [0x00,0x00,0x7c,0x33] +# CHECK-EL: swre $24, 5($3) # encoding: [0x03,0x63,0x05,0xa2] +# CHECK-EL: swle $24, 5($3) # encoding: [0x03,0x63,0x05,0xa0] +# CHECK-EL: lwre $24, 5($3) # encoding: [0x03,0x63,0x05,0x66] +# CHECK-EL: lwle $24, 2($4) # encoding: [0x04,0x63,0x02,0x64] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -72,6 +76,10 @@ # CHECK-EB: tlbr # encoding: [0x00,0x00,0x13,0x7c] # CHECK-EB: tlbwi # encoding: [0x00,0x00,0x23,0x7c] # CHECK-EB: tlbwr # encoding: [0x00,0x00,0x33,0x7c] +# CHECK-EB: swre $24, 5($3) # encoding: [0x63,0x03,0xa2,0x05] +# CHECK-EB: swle $24, 5($3) # encoding: [0x63,0x03,0xa0,0x05] +# CHECK-EB: lwre $24, 5($3) # encoding: [0x63,0x03,0x66,0x05] +# CHECK-EB: lwle $24, 2($4) # encoding: [0x63,0x04,0x64,0x02] sdbbp sdbbp 34 @@ -100,3 +108,7 @@ tlbr tlbwi tlbwr + swre $24, 5($3) + swle $24, 5($3) + lwre $24, 5($3) + lwle $24, 2($4) Index: test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s =================================================================== --- test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s +++ test/MC/Mips/mips32r6/invalid-mips1-wrong-error.s @@ -11,7 +11,8 @@ lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $24, 5($3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction Index: test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s =================================================================== --- test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s +++ test/MC/Mips/mips64r6/invalid-mips1-wrong-error.s @@ -11,7 +11,7 @@ lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction Index: test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s =================================================================== --- test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s +++ test/MC/Mips/mips64r6/invalid-mips3-wrong-error.s @@ -17,7 +17,7 @@ lwr $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swl $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction swr $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + lwle $s4,-4231($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwre $zero,-19147($gp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swle $15,13694($s3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swre $s1,-26590($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction